Changeset 54496 in vbox for trunk/src/VBox/VMM/VMMSwitcher

Timestamp:

Feb 25, 2015 2:33:18 PM (10 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

98605

Message:

VMMSwitcher: test code for disabling the Extended LVT APIC registers on newer AMD boxes

File:

• trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac (modified) (3 diffs)

trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac

@@ -131 +131 @@
     and     dword [r8 + APIC_REG_LVT_CMCI], ~APIC_REG_LVT_MASKED
 gth64_nocmci:
+    shr     ecx, 1
+    jnc     gth64_noeilvt0
+    and     dword [r8 + APIC_REG_EILVT0], ~APIC_REG_LVT_MASKED
+gth64_noeilvt0:
+    shr     ecx, 1
+    jnc     gth64_noeilvt1
+    and     dword [r8 + APIC_REG_EILVT1], ~APIC_REG_LVT_MASKED
+gth64_noeilvt1:
+    shr     ecx, 1
+    jnc     gth64_noeilvt2
+    and     dword [r8 + APIC_REG_EILVT2], ~APIC_REG_LVT_MASKED
+gth64_noeilvt2:
+    shr     ecx, 1
+    jnc     gth64_noeilvt3
+    and     dword [r8 + APIC_REG_EILVT3], ~APIC_REG_LVT_MASKED
+gth64_noeilvt3:
+
     jmp     gth64_apic_done
 
@@ -376 +393 @@
     mov     eax, [rbx + APIC_REG_VERSION]
     shr     eax, 16
+    push    rax
     cmp     al, 5
     jb      htg_notherm
@@ -399 +417 @@
     mov     eax, [rbx + APIC_REG_LVT_THMR] ; write completion
 htg_notherm:
+    pop     rax
+    test    ah, ah
+    jns     htg_noeilvt
+
+    ; AMD Extended LVT registers
+    mov     eax, [rbx + APIC_REG_EILVT0]
+    mov     ecx, eax
+    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
+    cmp     ecx, APIC_REG_LVT_MODE_NMI
+    jne     htg_noeilvt0
+    or      edi, 0x20
+    or      eax, APIC_REG_LVT_MASKED
+    mov     [rbx + APIC_REG_EILVT0], eax
+    mov     eax, [rbx + APIC_REG_EILVT0] ; write completion
+htg_noeilvt0:
+    mov     eax, [rbx + APIC_REG_EILVT1]
+    mov     ecx, eax
+    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
+    cmp     ecx, APIC_REG_LVT_MODE_NMI
+    jne     htg_noeilvt1
+    or      edi, 0x40
+    or      eax, APIC_REG_LVT_MASKED
+    mov     [rbx + APIC_REG_EILVT1], eax
+    mov     eax, [rbx + APIC_REG_EILVT1] ; write completion
+htg_noeilvt1:
+    mov     eax, [rbx + APIC_REG_EILVT2]
+    mov     ecx, eax
+    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
+    cmp     ecx, APIC_REG_LVT_MODE_NMI
+    jne     htg_noeilvt2
+    or      edi, 0x80
+    or      eax, APIC_REG_LVT_MASKED
+    mov     [rbx + APIC_REG_EILVT2], eax
+    mov     eax, [rbx + APIC_REG_EILVT2] ; write completion
+htg_noeilvt2:
+    mov     eax, [rbx + APIC_REG_EILVT3]
+    mov     ecx, eax
+    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
+    cmp     ecx, APIC_REG_LVT_MODE_NMI
+    jne     htg_noeilvt
+    or      edi, 0x100
+    or      eax, APIC_REG_LVT_MASKED
+    mov     [rbx + APIC_REG_EILVT3], eax
+    mov     eax, [rbx + APIC_REG_EILVT3] ; write completion
+
+htg_noeilvt:
     mov     [rdx + r8 + CPUMCPU.fApicDisVectors], edi
     jmp     htg_apic_done