Changeset 54537 in vbox

Timestamp:

Feb 26, 2015 4:55:58 PM (10 years ago)

Author:

vboxsync

Message:

VMMSwitcher: fixed code for disabling the Extended LVT APIC registers

Location:

trunk/src/VBox/VMM

Files:

• VMMR0/CPUMR0.cpp (modified) (1 diff)
• VMMSwitcher/AMD64andLegacy.mac (modified) (1 diff)

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -878 +878 @@
                         ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
                         ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
-            uint32_t u32EBX, u32ECX, u32EDX;
-            uint32_t uMaxExtLeaf;
-            ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
-            if (   uMaxExtLeaf >= UINT32_C(0x8000001b)
-                && ASMIsValidExtRange(uMaxExtLeaf))
+            if (uApicVersion & 0x80000000)
             {
-                uint32_t uIbsFeatures;
-                ASMCpuId(0x8000001b, &uIbsFeatures, &u32EBX, &u32ECX, &u32EDX);
-                if (uIbsFeatures & 1)
-                {
-                    SUPR0Printf("CPUM: APIC %02u: IBS available. 400=%08x eilvt0=%08x %08x %08x %08x\n",
-                                iCpu,
-                                ApicRegRead(g_aLApics[iCpu].pv, 0x400),
-                                ApicRegRead(g_aLApics[iCpu].pv, 0x500),
-                                ApicRegRead(g_aLApics[iCpu].pv, 0x510),
-                                ApicRegRead(g_aLApics[iCpu].pv, 0x520),
-                                ApicRegRead(g_aLApics[iCpu].pv, 0x530));
-                }
+                uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
+                uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
+                SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
+                            iCpu,
+                            ApicRegRead(g_aLApics[iCpu].pv, 0x400),
+                            cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
+                            cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
+                            cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
+                            cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
             }
         }

trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac

@@ -422 +422 @@
 
     ; AMD Extended LVT registers
+    mov     esi, [rbx + 0x400]
+    shr     esi, 16
+    and     esi, 0xff
+    jz      htg_noeilvt
+    mov     ebp, 0x20
+htg_tsteilvtx:
     mov     eax, [rbx + APIC_REG_EILVT0]
     mov     ecx, eax
     and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
     cmp     ecx, APIC_REG_LVT_MODE_NMI
-    jne     htg_noeilvt0
-    or      edi, 0x20
+    jne     htg_noeilvtx
+    or      edi, ebp
     or      eax, APIC_REG_LVT_MASKED
     mov     [rbx + APIC_REG_EILVT0], eax
     mov     eax, [rbx + APIC_REG_EILVT0] ; write completion
-htg_noeilvt0:
-    mov     eax, [rbx + APIC_REG_EILVT1]
-    mov     ecx, eax
-    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
-    cmp     ecx, APIC_REG_LVT_MODE_NMI
-    jne     htg_noeilvt1
-    or      edi, 0x40
-    or      eax, APIC_REG_LVT_MASKED
-    mov     [rbx + APIC_REG_EILVT1], eax
-    mov     eax, [rbx + APIC_REG_EILVT1] ; write completion
-htg_noeilvt1:
-    mov     eax, [rbx + APIC_REG_EILVT2]
-    mov     ecx, eax
-    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
-    cmp     ecx, APIC_REG_LVT_MODE_NMI
-    jne     htg_noeilvt2
-    or      edi, 0x80
-    or      eax, APIC_REG_LVT_MASKED
-    mov     [rbx + APIC_REG_EILVT2], eax
-    mov     eax, [rbx + APIC_REG_EILVT2] ; write completion
-htg_noeilvt2:
-    mov     eax, [rbx + APIC_REG_EILVT3]
-    mov     ecx, eax
-    and     ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
-    cmp     ecx, APIC_REG_LVT_MODE_NMI
-    jne     htg_noeilvt
-    or      edi, 0x100
-    or      eax, APIC_REG_LVT_MASKED
-    mov     [rbx + APIC_REG_EILVT3], eax
-    mov     eax, [rbx + APIC_REG_EILVT3] ; write completion
+htg_noeilvtx:
+    add     rbx, 0x10                    ; clobbers rbx!
+    shl     ebp, 1
+    dec     esi
+    jnz     htg_tsteilvtx
 
 htg_noeilvt: