Changeset 54844 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Mar 19, 2015 12:48:29 AM (10 years ago)
- svn:sync-xref-src-repo-rev:
- 99048
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (6 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
r54822 r54844 4363 4363 4364 4364 4365 /** CPUID(1).EDX field descriptions. */ 4366 static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] = 4367 { 4368 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0), 4369 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0), 4370 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0), 4371 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0), 4372 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0), 4373 DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0), 4374 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0), 4375 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0), 4376 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0), 4377 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0), 4378 DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0), 4379 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0), 4380 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0), 4381 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0), 4382 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move Instructions", 15, 1, 0), 4383 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0), 4384 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0), 4385 DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0), 4386 DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH Instruction", 19, 1, 0), 4387 DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0), 4388 DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0), 4389 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0), 4390 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0), 4391 DBGFREGSUBFIELD_RO("SSE\0" "SSE Support", 25, 1, 0), 4392 DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 Support", 26, 1, 0), 4393 DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0), 4394 DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0), 4395 DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0), 4396 DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0), 4397 DBGFREGSUBFIELD_TERMINATOR() 4398 }; 4399 4400 /** CPUID(1).ECX field descriptions. */ 4401 static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] = 4402 { 4403 DBGFREGSUBFIELD_RO("SSE3\0" "Supports SSE3 or not", 0, 1, 0), 4404 DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0), 4405 DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0), 4406 DBGFREGSUBFIELD_RO("MONITOR\0" "Supports MONITOR/MWAIT", 3, 1, 0), 4407 DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0), 4408 DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Technology", 5, 1, 0), 4409 DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0), 4410 DBGFREGSUBFIELD_RO("EST\0" "Enh. SpeedStep Tech", 7, 1, 0), 4411 DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0), 4412 DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0), 4413 DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0), 4414 DBGFREGSUBFIELD_RO("FMA\0" "FMA Support", 12, 1, 0), 4415 DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B", 13, 1, 0), 4416 DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0), 4417 DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0), 4418 DBGFREGSUBFIELD_RO("PCID\0" "Process-context identifiers", 17, 1, 0), 4419 DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0), 4420 DBGFREGSUBFIELD_RO("SSE4_1\0" "Supports SSE4_1 or not", 19, 1, 0), 4421 DBGFREGSUBFIELD_RO("SSE4_2\0" "Supports SSE4_2 or not", 20, 1, 0), 4422 DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0), 4423 DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0), 4424 DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0), 4425 DBGFREGSUBFIELD_RO("TSCDEADL\0" "TSC-Deadline", 24, 1, 0), 4426 DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0), 4427 DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0), 4428 DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0), 4429 DBGFREGSUBFIELD_RO("AVX\0" "AVX", 28, 1, 0), 4430 DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instr", 29, 1, 0), 4431 DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0), 4432 DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0), 4433 DBGFREGSUBFIELD_TERMINATOR() 4434 }; 4435 4436 /** CPUID(7,0).EBX field descriptions. */ 4437 static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] = 4438 { 4439 DBGFREGSUBFIELD_RO("FSGSBASE\0" "Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE", 0, 1, 0), 4440 DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0), 4441 DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0), 4442 DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0), 4443 DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0), 4444 DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0), 4445 DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0), 4446 DBGFREGSUBFIELD_RO("ERMS\0" "Supports Enhanced REP MOVSB/STOSB", 9, 1, 0), 4447 DBGFREGSUBFIELD_RO("INVPCID\0" "Supports INVPCID", 10, 1, 0), 4448 DBGFREGSUBFIELD_RO("RTM\0" "Supports Restricted Transactional Memory", 11, 1, 0), 4449 DBGFREGSUBFIELD_RO("PQM\0" "Supports Platform Quality of Service Monitoring", 12, 1, 0), 4450 DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0), 4451 DBGFREGSUBFIELD_RO("MPE\0" "Supports Intel Memory Protection Extensions", 14, 1, 0), 4452 DBGFREGSUBFIELD_RO("PQE\0" "Supports Platform Quality of Service Enforcement", 15, 1, 0), 4453 DBGFREGSUBFIELD_RO("AVX512F\0" "Supports AVX512F", 16, 1, 0), 4454 DBGFREGSUBFIELD_RO("RDSEED\0" "Supports RDSEED", 18, 1, 0), 4455 DBGFREGSUBFIELD_RO("ADX\0" "Supports ADCX/ADOX", 19, 1, 0), 4456 DBGFREGSUBFIELD_RO("SMAP\0" "Supports Supervisor Mode Access Prevention", 20, 1, 0), 4457 DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "Supports CLFLUSHOPT (Cache Line Flush)", 23, 1, 0), 4458 DBGFREGSUBFIELD_RO("INTEL_PT\0" "Supports Intel Processor Trace", 25, 1, 0), 4459 DBGFREGSUBFIELD_RO("AVX512PF\0" "Supports AVX512PF", 26, 1, 0), 4460 DBGFREGSUBFIELD_RO("AVX512ER\0" "Supports AVX512ER", 27, 1, 0), 4461 DBGFREGSUBFIELD_RO("AVX512CD\0" "Supports AVX512CD", 28, 1, 0), 4462 DBGFREGSUBFIELD_RO("SHA\0" "Supports Secure Hash Algorithm extensions", 29, 1, 0), 4463 DBGFREGSUBFIELD_TERMINATOR() 4464 }; 4465 4466 /** CPUID(7,0).ECX field descriptions. */ 4467 static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] = 4468 { 4469 DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "Supports the PREFETCHWT1 instruction", 0, 1, 0), 4470 DBGFREGSUBFIELD_TERMINATOR() 4471 }; 4472 4473 4474 /** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */ 4475 static DBGFREGSUBFIELD const g_aXSaveStateBits[] = 4476 { 4477 DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0), 4478 DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0), 4479 DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0), 4480 DBGFREGSUBFIELD_RO("AVX\0" "256-bit AVX state", 3, 1, 0), 4481 DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 4, 1, 0), 4482 DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 5, 1, 0), 4483 DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 6, 1, 0), 4484 DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 7, 1, 0), 4485 DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 8, 1, 0), 4486 DBGFREGSUBFIELD_TERMINATOR() 4487 }; 4488 4489 /** CPUID(13,1).EAX field descriptions. */ 4490 static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] = 4491 { 4492 DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0), 4493 DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0), 4494 DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0), 4495 DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0), 4496 DBGFREGSUBFIELD_TERMINATOR() 4497 }; 4498 4499 4500 /** CPUID(0x80000001,0).EDX field descriptions. */ 4501 static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] = 4502 { 4503 DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0), 4504 DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0), 4505 DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0), 4506 DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0), 4507 DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0), 4508 DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0), 4509 DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0), 4510 DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0), 4511 DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0), 4512 DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0), 4513 DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0), 4514 DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0), 4515 DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0), 4516 DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0), 4517 DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move Instructions", 15, 1, 0), 4518 DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0), 4519 DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0), 4520 DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0), 4521 DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX Instructions", 22, 1, 0), 4522 DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0), 4523 DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0), 4524 DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR Instr.", 25, 1, 0), 4525 DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0), 4526 DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0), 4527 DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0), 4528 DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0), 4529 DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0), 4530 DBGFREGSUBFIELD_TERMINATOR() 4531 }; 4532 4533 /** CPUID(0x80000001,0).ECX field descriptions. */ 4534 static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] = 4535 { 4536 DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0), 4537 DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0), 4538 DBGFREGSUBFIELD_RO("SVM\0" "AMD VM extensions", 2, 1, 0), 4539 DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD extended APIC registers", 3, 1, 0), 4540 DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0), 4541 DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced bit manipulation", 5, 1, 0), 4542 DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instruction support", 6, 1, 0), 4543 DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0), 4544 DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instr.", 8, 1, 0), 4545 DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS visible workaround", 9, 1, 0), 4546 DBGFREGSUBFIELD_RO("IBS\0" "Instruct based sampling", 10, 1, 0), 4547 DBGFREGSUBFIELD_RO("SSE5\0" "SSE5 instruction support", 11, 1, 0), 4548 DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0), 4549 DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog timer support", 13, 1, 0), 4550 DBGFREGSUBFIELD_RO("LWP\0" "Lightweight profiling support", 15, 1, 0), 4551 DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0), 4552 DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0), 4553 DBGFREGSUBFIELD_RO("TBM\0" "Trailing bit manipulation instr.", 21, 1, 0), 4554 DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0), 4555 DBGFREGSUBFIELD_TERMINATOR() 4556 }; 4557 4558 4559 static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc, 4560 const char *pszLeadIn, uint32_t cchWidth) 4561 { 4562 if (pszLeadIn) 4563 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn); 4564 4565 for (uint32_t iBit = 0; iBit < 32; iBit++) 4566 if (RT_BIT_32(iBit) & uVal) 4567 { 4568 while ( pDesc->pszName != NULL 4569 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits) 4570 pDesc++; 4571 if ( pDesc->pszName != NULL 4572 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits) 4573 { 4574 if (pDesc->cBits == 1) 4575 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName); 4576 else 4577 { 4578 uint32_t uFieldValue = uVal >> pDesc->iFirstBit; 4579 if (pDesc->cBits < 32) 4580 uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1); 4581 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue); 4582 iBit = pDesc->iFirstBit + pDesc->cBits - 1; 4583 } 4584 } 4585 else 4586 pHlp->pfnPrintf(pHlp, " %u", iBit); 4587 } 4588 if (pszLeadIn) 4589 pHlp->pfnPrintf(pHlp, "\n"); 4590 } 4591 4592 4593 static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc, 4594 const char *pszLeadIn, uint32_t cchWidth) 4595 { 4596 if (pszLeadIn) 4597 pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn); 4598 4599 for (uint32_t iBit = 0; iBit < 64; iBit++) 4600 if (RT_BIT_64(iBit) & uVal) 4601 { 4602 while ( pDesc->pszName != NULL 4603 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits) 4604 pDesc++; 4605 if ( pDesc->pszName != NULL 4606 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits) 4607 { 4608 if (pDesc->cBits == 1) 4609 pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName); 4610 else 4611 { 4612 uint64_t uFieldValue = uVal >> pDesc->iFirstBit; 4613 if (pDesc->cBits < 64) 4614 uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1); 4615 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue); 4616 iBit = pDesc->iFirstBit + pDesc->cBits - 1; 4617 } 4618 } 4619 else 4620 pHlp->pfnPrintf(pHlp, " %u", iBit); 4621 } 4622 if (pszLeadIn) 4623 pHlp->pfnPrintf(pHlp, "\n"); 4624 } 4625 4626 4627 static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc, 4628 const char *pszLeadIn, uint32_t cchWidth) 4629 { 4630 if (!uVal) 4631 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal)); 4632 else 4633 { 4634 pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal)); 4635 cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0); 4636 pHlp->pfnPrintf(pHlp, " )\n"); 4637 } 4638 } 4639 4640 4641 static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc, 4642 uint32_t cchWidth) 4643 { 4644 uint32_t uCombined = uVal1 | uVal2; 4645 for (uint32_t iBit = 0; iBit < 32; iBit++) 4646 if ( (RT_BIT_32(iBit) & uCombined) 4647 || (iBit == pDesc->iFirstBit && pDesc->pszName) ) 4648 { 4649 while ( pDesc->pszName != NULL 4650 && iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits) 4651 pDesc++; 4652 4653 if ( pDesc->pszName != NULL 4654 && iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits) 4655 { 4656 size_t cchMnemonic = strlen(pDesc->pszName); 4657 const char *pszDesc = pDesc->pszName + cchMnemonic + 1; 4658 size_t cchDesc = strlen(pszDesc); 4659 uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit; 4660 uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit; 4661 if (pDesc->cBits < 32) 4662 { 4663 uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1); 4664 uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1); 4665 } 4666 4667 pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%*s= %u (%u)\n" : " %s - %s%*s= %#x (%#x)\n", 4668 pDesc->pszName, pszDesc, 4669 cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "", 4670 uFieldValue1, uFieldValue2); 4671 4672 iBit = pDesc->iFirstBit + pDesc->cBits - 1U; 4673 pDesc++; 4674 } 4675 else 4676 pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "", 4677 RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit))); 4678 } 4679 } 4680 4681 4682 /** 4683 * Produces a detailed summary of standard leaf 0x00000001. 4684 * 4685 * @param pHlp The info helper functions. 4686 * @param paLeaves The CPUID leaves array. 4687 * @param cLeaves The number of leaves in the array. 4688 * @param pCurLeaf The 0x00000001 leaf. 4689 * @param fVerbose Whether to be very verbose or not. 4690 * @param fIntel Set if intel CPU. 4691 */ 4692 static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, 4693 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel) 4694 { 4695 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1); 4696 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" }; 4697 uint32_t uEAX = pCurLeaf->uEax; 4698 uint32_t uEBX = pCurLeaf->uEbx; 4699 4700 pHlp->pfnPrintf(pHlp, 4701 "%36s %2d \tExtended: %d \tEffective: %d\n" 4702 "%36s %2d \tExtended: %d \tEffective: %d\n" 4703 "%36s %d\n" 4704 "%36s %d (%s)\n" 4705 "%36s %#04x\n" 4706 "%36s %d\n" 4707 "%36s %d\n" 4708 "%36s %#04x\n" 4709 , 4710 "Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX), 4711 "Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel), 4712 "Stepping:", ASMGetCpuStepping(uEAX), 4713 "Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3], 4714 "APIC ID:", (uEBX >> 24) & 0xff, 4715 "Logical CPUs:",(uEBX >> 16) & 0xff, 4716 "CLFLUSH Size:",(uEBX >> 8) & 0xff, 4717 "Brand ID:", (uEBX >> 0) & 0xff); 4718 if (fVerbose) 4719 { 4720 CPUMCPUID Host; 4721 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4722 pHlp->pfnPrintf(pHlp, "Features\n"); 4723 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n"); 4724 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56); 4725 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56); 4726 } 4727 else 4728 { 4729 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36); 4730 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36); 4731 } 4732 } 4733 4734 4735 /** 4736 * Produces a detailed summary of standard leaf 0x00000007. 4737 * 4738 * @param pHlp The info helper functions. 4739 * @param paLeaves The CPUID leaves array. 4740 * @param cLeaves The number of leaves in the array. 4741 * @param pCurLeaf The first 0x00000007 leaf. 4742 * @param fVerbose Whether to be very verbose or not. 4743 */ 4744 static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, 4745 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose) 4746 { 4747 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7); 4748 pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n"); 4749 for (;;) 4750 { 4751 CPUMCPUID Host; 4752 ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4753 4754 switch (pCurLeaf->uSubLeaf) 4755 { 4756 case 0: 4757 if (fVerbose) 4758 { 4759 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n"); 4760 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56); 4761 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56); 4762 if (pCurLeaf->uEdx || Host.uEdx) 4763 pHlp->pfnPrintf(pHlp, "%36 %#x (%#x)\n", "Ext Features EDX:", pCurLeaf->uEdx, Host.uEdx); 4764 } 4765 else 4766 { 4767 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36); 4768 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36); 4769 if (pCurLeaf->uEdx) 4770 pHlp->pfnPrintf(pHlp, "%36 %#x\n", "Ext Features EDX:", pCurLeaf->uEdx); 4771 } 4772 break; 4773 4774 default: 4775 if (pCurLeaf->uEdx || pCurLeaf->uEcx || pCurLeaf->uEbx) 4776 pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n", 4777 pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx); 4778 break; 4779 4780 } 4781 4782 /* advance. */ 4783 pCurLeaf++; 4784 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves 4785 || pCurLeaf->uLeaf != 0x7) 4786 break; 4787 } 4788 } 4789 4790 4791 /** 4792 * Produces a detailed summary of standard leaf 0x0000000d. 4793 * 4794 * @param pHlp The info helper functions. 4795 * @param paLeaves The CPUID leaves array. 4796 * @param cLeaves The number of leaves in the array. 4797 * @param pCurLeaf The first 0x00000007 leaf. 4798 * @param fVerbose Whether to be very verbose or not. 4799 */ 4800 static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, 4801 PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose) 4802 { 4803 Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13); 4804 pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n"); 4805 for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++) 4806 { 4807 CPUMCPUID Host; 4808 ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4809 4810 switch (uSubLeaf) 4811 { 4812 case 0: 4813 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf) 4814 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:", 4815 pCurLeaf->uEbx, pCurLeaf->uEcx); 4816 pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx); 4817 4818 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf) 4819 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits, 4820 "Valid XCR0 bits, guest:", 42); 4821 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits, 4822 "Valid XCR0 bits, host:", 42); 4823 break; 4824 4825 case 1: 4826 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf) 4827 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42); 4828 cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42); 4829 4830 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf) 4831 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, guest:", pCurLeaf->uEbx); 4832 pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0|XSS, host:", Host.uEbx); 4833 4834 if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf) 4835 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits, 4836 " Valid IA32_XSS bits, guest:", 42); 4837 cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits, 4838 " Valid IA32_XSS bits, host:", 42); 4839 break; 4840 4841 default: 4842 if ( pCurLeaf 4843 && pCurLeaf->uSubLeaf == uSubLeaf 4844 && (pCurLeaf->uEax || pCurLeaf->uEbx || pCurLeaf->uEcx || pCurLeaf->uEdx) ) 4845 { 4846 pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx, 4847 pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit"); 4848 if (pCurLeaf->uEcx & ~RT_BIT_32(0)) 4849 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0)); 4850 if (pCurLeaf->uEdx) 4851 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx); 4852 pHlp->pfnPrintf(pHlp, " --"); 4853 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0); 4854 pHlp->pfnPrintf(pHlp, "\n"); 4855 } 4856 if (Host.uEax || Host.uEbx || Host.uEcx || Host.uEdx) 4857 { 4858 pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx, 4859 Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit"); 4860 if (Host.uEcx & ~RT_BIT_32(0)) 4861 pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0)); 4862 if (Host.uEdx) 4863 pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx); 4864 pHlp->pfnPrintf(pHlp, " --"); 4865 cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0); 4866 pHlp->pfnPrintf(pHlp, "\n"); 4867 } 4868 break; 4869 4870 } 4871 4872 /* advance. */ 4873 if (pCurLeaf) 4874 { 4875 while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves 4876 && pCurLeaf->uSubLeaf <= uSubLeaf 4877 && pCurLeaf->uLeaf == UINT32_C(0x0000000d)) 4878 pCurLeaf++; 4879 if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves 4880 || pCurLeaf->uLeaf != UINT32_C(0x0000000d)) 4881 pCurLeaf = NULL; 4882 } 4883 } 4884 } 4885 4886 4365 4887 static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, 4366 4888 PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle) … … 4418 4940 PCCPUMCPUIDLEAF pCurLeaf; 4419 4941 PCCPUMCPUIDLEAF pNextLeaf; 4942 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx, 4943 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx, 4944 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx); 4420 4945 4421 4946 /* … … 4470 4995 } 4471 4996 } 4997 pNextLeaf = pCurLeaf; 4472 4998 4473 4999 /* … … 4476 5002 if (iVerbosity && paLeaves[0].uLeaf == 0) 4477 5003 pHlp->pfnPrintf(pHlp, 4478 "Name: %.04s%.04s%.04s\n" 4479 "Supports: 0-%x\n", 4480 &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx, paLeaves[0].uEax); 4481 4482 /* 4483 * Get Features. 4484 */ 4485 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx, 4486 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx, 4487 pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx); 4488 if (cGstMax >= 1 && iVerbosity) 4489 { 4490 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" }; 4491 4492 PCPUMCPUIDLEAF pFeatures = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, 1, 0); 4493 uint32_t uEAX = pFeatures ? pFeatures->uEax : 0; 4494 uint32_t uEBX = pFeatures ? pFeatures->uEbx : 0; 4495 4496 pHlp->pfnPrintf(pHlp, 4497 "Family: %d \tExtended: %d \tEffective: %d\n" 4498 "Model: %d \tExtended: %d \tEffective: %d\n" 4499 "Stepping: %d\n" 4500 "Type: %d (%s)\n" 4501 "APIC ID: %#04x\n" 4502 "Logical CPUs: %d\n" 4503 "CLFLUSH Size: %d\n" 4504 "Brand ID: %#04x\n", 4505 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX), 4506 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel), 4507 ASMGetCpuStepping(uEAX), 4508 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3], 4509 (uEBX >> 24) & 0xff, 4510 (uEBX >> 16) & 0xff, 4511 (uEBX >> 8) & 0xff, 4512 (uEBX >> 0) & 0xff); 4513 if (iVerbosity == 1) 4514 { 4515 uint32_t uEDX = pFeatures ? pFeatures->uEdx : 0; 4516 pHlp->pfnPrintf(pHlp, "Features EDX: "); 4517 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU"); 4518 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME"); 4519 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE"); 4520 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE"); 4521 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC"); 4522 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR"); 4523 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE"); 4524 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE"); 4525 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8"); 4526 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC"); 4527 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10"); 4528 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP"); 4529 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR"); 4530 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE"); 4531 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA"); 4532 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV"); 4533 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT"); 4534 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36"); 4535 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN"); 4536 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH"); 4537 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20"); 4538 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS"); 4539 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI"); 4540 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX"); 4541 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR"); 4542 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE"); 4543 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2"); 4544 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS"); 4545 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT"); 4546 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM"); 4547 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30"); 4548 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE"); 4549 pHlp->pfnPrintf(pHlp, "\n"); 4550 4551 uint32_t uECX = pFeatures ? pFeatures->uEcx : 0; 4552 pHlp->pfnPrintf(pHlp, "Features ECX: "); 4553 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3"); 4554 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL"); 4555 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64"); 4556 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR"); 4557 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL"); 4558 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX"); 4559 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX"); 4560 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST"); 4561 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2"); 4562 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3"); 4563 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID"); 4564 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11"); 4565 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA"); 4566 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16"); 4567 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE"); 4568 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM"); 4569 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16"); 4570 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID"); 4571 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA"); 4572 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1"); 4573 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2"); 4574 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC"); 4575 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE"); 4576 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT"); 4577 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL"); 4578 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES"); 4579 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE"); 4580 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE"); 4581 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX"); 4582 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " F16C"); 4583 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " RDRAND"); 4584 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP"); 4585 pHlp->pfnPrintf(pHlp, "\n"); 4586 } 4587 else 4588 { 4589 ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4590 4591 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.uEdx; 4592 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.uEcx; 4593 X86CPUIDFEATEDX EdxGuest; 4594 X86CPUIDFEATECX EcxGuest; 4595 if (pFeatures) 4596 { 4597 EdxGuest = *(PX86CPUIDFEATEDX)&pFeatures->uEdx; 4598 EcxGuest = *(PX86CPUIDFEATECX)&pFeatures->uEcx; 4599 } 4600 else 4601 { 4602 RT_ZERO(EdxGuest); 4603 RT_ZERO(EcxGuest); 4604 } 4605 4606 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); 4607 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU); 4608 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME); 4609 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE); 4610 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE); 4611 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC); 4612 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR); 4613 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE); 4614 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE); 4615 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8); 4616 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC); 4617 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1); 4618 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP); 4619 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR); 4620 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE); 4621 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA); 4622 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV); 4623 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT); 4624 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36); 4625 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN); 4626 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH); 4627 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2); 4628 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS); 4629 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI); 4630 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX); 4631 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR); 4632 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE); 4633 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2); 4634 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS); 4635 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT); 4636 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM); 4637 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3); 4638 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE); 4639 4640 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3); 4641 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ); 4642 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64); 4643 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor); 4644 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS); 4645 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX); 4646 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX); 4647 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST); 4648 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2); 4649 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3); 4650 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID); 4651 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1); 4652 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA); 4653 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16); 4654 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate); 4655 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM); 4656 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2); 4657 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID); 4658 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA); 4659 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1); 4660 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2); 4661 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC); 4662 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE); 4663 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT); 4664 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE); 4665 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES); 4666 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE); 4667 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE); 4668 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX); 4669 pHlp->pfnPrintf(pHlp, "16-bit floating point conversion instr = %d (%d)\n", EcxGuest.u1F16C, EcxHost.u1F16C); 4670 pHlp->pfnPrintf(pHlp, "RDRAND instruction = %d (%d)\n", EcxGuest.u1RDRAND, EcxHost.u1RDRAND); 4671 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP); 4672 } 4673 } 4674 if (cGstMax >= 2 && iVerbosity) 4675 { 4676 /** @todo */ 4677 } 5004 "%36s %.04s%.04s%.04s\n" 5005 "%36s 0x00000000-%#010x\n" 5006 , 5007 "Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx, 5008 "Supports:", paLeaves[0].uEax); 5009 5010 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL) 5011 cpumR3CpuIdInfoStdLeaf1Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1, fIntel); 5012 5013 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL) 5014 cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1); 5015 5016 if (iVerbosity && (pCurLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL) 5017 cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1); 5018 5019 pCurLeaf = pNextLeaf; 4678 5020 4679 5021 /* … … 4779 5121 if (iVerbosity == 1) 4780 5122 { 4781 uint32_t uEDX = pCurLeaf->uEdx; 4782 pHlp->pfnPrintf(pHlp, "Features EDX: "); 4783 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU"); 4784 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME"); 4785 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE"); 4786 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE"); 4787 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC"); 4788 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR"); 4789 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE"); 4790 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE"); 4791 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8"); 4792 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC"); 4793 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10"); 4794 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR"); 4795 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR"); 4796 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE"); 4797 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA"); 4798 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV"); 4799 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT"); 4800 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36"); 4801 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18"); 4802 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19"); 4803 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX"); 4804 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21"); 4805 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX"); 4806 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX"); 4807 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR"); 4808 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR"); 4809 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB"); 4810 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP"); 4811 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28"); 4812 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode"); 4813 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow"); 4814 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow"); 4815 pHlp->pfnPrintf(pHlp, "\n"); 4816 4817 uint32_t uECX = pCurLeaf->uEcx; 4818 pHlp->pfnPrintf(pHlp, "Features ECX: "); 4819 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF"); 4820 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL"); 4821 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM"); 4822 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC"); 4823 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L"); 4824 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM"); 4825 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A"); 4826 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE"); 4827 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF"); 4828 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW"); 4829 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS"); 4830 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5"); 4831 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT"); 4832 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT"); 4833 for (unsigned iBit = 5; iBit < 32; iBit++) 4834 if (uECX & RT_BIT(iBit)) 4835 pHlp->pfnPrintf(pHlp, " %d", iBit); 4836 pHlp->pfnPrintf(pHlp, "\n"); 5123 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34); 5124 cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34); 4837 5125 } 4838 5126 else 4839 5127 { 4840 5128 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx); 4841 4842 uint32_t uEdxGst = pCurLeaf->uEdx; 4843 uint32_t uEdxHst = Host.uEdx; 4844 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n"); 4845 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0))); 4846 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1))); 4847 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2))); 4848 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3))); 4849 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4))); 4850 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5))); 4851 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6))); 4852 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7))); 4853 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8))); 4854 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9))); 4855 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10))); 4856 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11))); 4857 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12))); 4858 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13))); 4859 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14))); 4860 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15))); 4861 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16))); 4862 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17))); 4863 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18))); 4864 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19))); 4865 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20))); 4866 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21))); 4867 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22))); 4868 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23))); 4869 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24))); 4870 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25))); 4871 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26))); 4872 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27))); 4873 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28))); 4874 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29))); 4875 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30))); 4876 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31))); 4877 4878 uint32_t uEcxGst = pCurLeaf->uEcx; 4879 uint32_t uEcxHst = Host.uEcx; 4880 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0))); 4881 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1))); 4882 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2))); 4883 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3))); 4884 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4))); 4885 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5))); 4886 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6))); 4887 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7))); 4888 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8))); 4889 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9))); 4890 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10))); 4891 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11))); 4892 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12))); 4893 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13))); 4894 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14); 5129 pHlp->pfnPrintf(pHlp, "Ext Features\n"); 5130 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n"); 5131 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56); 5132 cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56); 4895 5133 } 4896 5134 } … … 4920 5158 *pu32++ = pCurLeaf->uEdx; 4921 5159 } 4922 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);5160 pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString); 4923 5161 } 4924 5162
Note:
See TracChangeset
for help on using the changeset viewer.
