Changeset 54887 in vbox for trunk/src/VBox
- Timestamp:
- Mar 20, 2015 9:32:24 PM (10 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp ¶
r54879 r54887 2003 2003 /** @name Instruction Set Extension Options 2004 2004 * @{ */ 2005 /** Configuration option type . */2005 /** Configuration option type (extended boolean, really). */ 2006 2006 typedef uint8_t CPUMISAEXTCFG; 2007 /** Default choice of the VMM. */2008 #define CPUMISAEXTCFG_DEFAULT UINT8_C(0)2009 2007 /** Always disable the extension. */ 2010 #define CPUMISAEXTCFG_DISABLED UINT8_C(1)2008 #define CPUMISAEXTCFG_DISABLED false 2011 2009 /** Enable the extension if it's supported by the host CPU. */ 2012 #define CPUMISAEXTCFG_ENABLED_SUPPORTED UINT8_C(2)2010 #define CPUMISAEXTCFG_ENABLED_SUPPORTED true 2013 2011 /** Always enable the extension. */ 2014 #define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_ C(3)2012 #define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_MAX 2015 2013 /** @} */ 2016 2014 … … 2032 2030 bool fInvariantTsc; 2033 2031 CPUMISAEXTCFG enmAesNi; 2034 CPUMISAEXTCFG enmPClMulQDQ; 2032 CPUMISAEXTCFG enmPClMul; 2033 CPUMISAEXTCFG enmPopCnt; 2034 CPUMISAEXTCFG enmMovBe; 2035 CPUMISAEXTCFG enmRdRand; 2036 CPUMISAEXTCFG enmRdSeed; 2035 2037 uint32_t uMaxStdLeaf; 2036 2038 uint32_t uMaxExtLeaf; … … 2321 2323 pStdFeatureLeaf->uEcx &= 0 2322 2324 | X86_CPUID_FEATURE_ECX_SSE3 2323 //| X86_CPUID_FEATURE_ECX_PCLMUL - not implemented yet.2325 | (pConfig->enmPClMul ? X86_CPUID_FEATURE_ECX_PCLMUL : 0) 2324 2326 //| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet. 2325 2327 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */ … … 2342 2344 | (pConfig->fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0) 2343 2345 //| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled. 2344 //| X86_CPUID_FEATURE_ECX_MOVBE - not implemented yet.2345 //| X86_CPUID_FEATURE_ECX_POPCNT2346 | (pConfig->enmMovBe ? X86_CPUID_FEATURE_ECX_MOVBE : 0) 2347 | (pConfig->enmPopCnt ? X86_CPUID_FEATURE_ECX_POPCNT : 0) 2346 2348 //| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet. 2347 //| X86_CPUID_FEATURE_ECX_AES - not implemented yet.2349 | (pConfig->enmAesNi ? X86_CPUID_FEATURE_ECX_AES : 0) 2348 2350 //| X86_CPUID_FEATURE_ECX_XSAVE - not implemented yet. 2349 2351 //| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state 2350 2352 //| X86_CPUID_FEATURE_ECX_AVX - not implemented yet. 2351 2353 //| X86_CPUID_FEATURE_ECX_F16C - not implemented yet. 2352 //| X86_CPUID_FEATURE_ECX_RDRAND - not implemented yet.2354 | (pConfig->enmRdRand ? X86_CPUID_FEATURE_ECX_RDRAND : 0) 2353 2355 //| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later. 2354 2356 ; … … 2697 2699 //| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16) 2698 2700 //| RT_BIT(17) - reserved 2699 //| X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT(18)2701 | (pConfig->enmRdSeed ? X86_CPUID_STEXT_FEATURE_EBX_RDSEED : 0) 2700 2702 //| X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT(19) 2701 2703 //| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20) … … 3157 3159 3158 3160 3159 static int cpumR3CpuIdReadConfig(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec) 3161 static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName, 3162 CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault) 3163 { 3164 /* 3165 * Try integer encoding first. 3166 */ 3167 uint64_t uValue; 3168 int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue); 3169 if (RT_SUCCESS(rc)) 3170 switch (uValue) 3171 { 3172 case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break; 3173 case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break; 3174 case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break; 3175 default: 3176 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS, 3177 "Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', or 2/'forced')", 3178 pszValueName, uValue); 3179 } 3180 /* 3181 * If missing, use default. 3182 */ 3183 else if (rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT) 3184 *penmValue = enmDefault; 3185 else 3186 { 3187 if (rc == VERR_CFGM_NOT_INTEGER) 3188 { 3189 /* 3190 * Not an integer, try read it as a string. 3191 */ 3192 char szValue[32]; 3193 rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue)); 3194 if (RT_SUCCESS(rc)) 3195 { 3196 RTStrToLower(szValue); 3197 size_t cchValue = strlen(szValue); 3198 #define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1)) 3199 if ( EQ("disabled") || EQ("disable") || EQ("off") || EQ("no")) 3200 *penmValue = CPUMISAEXTCFG_DISABLED; 3201 else if (EQ("enabled") || EQ("enable") || EQ("on") || EQ("yes")) 3202 *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; 3203 else if (EQ("forced") || EQ("force") || EQ("always")) 3204 *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; 3205 else if (EQ("default") || EQ("def")) 3206 *penmValue = enmDefault; 3207 else 3208 return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS, 3209 "Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', or 2/'forced')", 3210 pszValueName, uValue); 3211 #undef EQ 3212 } 3213 } 3214 if (RT_FAILURE(rc)) 3215 return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc); 3216 } 3217 return VINF_SUCCESS; 3218 } 3219 3220 3221 static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec) 3160 3222 { 3161 3223 int rc; … … 3175 3237 * values should only be used when older CPUs are involved since it may 3176 3238 * harm performance and maybe also cause problems with specific guests. */ 3177 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &p Cpum->u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0);3239 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, pConfig->fSyntheticCpu ? 1 : 0); 3178 3240 AssertLogRelRCReturn(rc, rc); 3179 3241 … … 3240 3302 */ 3241 3303 PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts"); 3304 if (pIsaExts) 3305 { 3306 rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/", 3307 "CMPXCHG16B" 3308 "|MONITOR" 3309 "|MWaitExtensions" 3310 "|SSE4.1" 3311 "|SSE4.2" 3312 "|AESNI" 3313 "|PCLMUL" 3314 "|POPCNT" 3315 "|MOVBE" 3316 "|RDRAND" 3317 "|RDSEED", 3318 "" /*pszValidNodes*/, "CPUM" /*pszWho*/, 0 /*uInstance*/); 3319 if (RT_FAILURE(rc)) 3320 return rc; 3321 } 3242 3322 3243 3323 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false} … … 3272 3352 AssertLogRelRCReturn(rc, rc); 3273 3353 3274 #if 03275 3354 /** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends} 3276 3355 * Whether to expose the AES instructions to the guest. For the time being the … … 3278 3357 * unrestricted guest mode. 3279 3358 */ 3280 rc = cpumR3CpuIdReadIsaExtCfg(p IsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);3359 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec); 3281 3360 AssertLogRelRCReturn(rc, rc); 3282 #endif 3283 3361 3362 /** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends} 3363 * Whether to expose the PCLMULQDQ instructions to the guest. For the time 3364 * being the default is to only do this for VMs with nested paging and AMD-V or 3365 * unrestricted guest mode. 3366 */ 3367 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec); 3368 AssertLogRelRCReturn(rc, rc); 3369 3370 /** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, depends} 3371 * Whether to expose the POPCNT instructions to the guest. For the time 3372 * being the default is to only do this for VMs with nested paging and AMD-V or 3373 * unrestricted guest mode. 3374 */ 3375 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, fNestedPagingAndFullGuestExec); 3376 AssertLogRelRCReturn(rc, rc); 3377 3378 /** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends} 3379 * Whether to expose the MOVBE instructions to the guest. For the time 3380 * being the default is to only do this for VMs with nested paging and AMD-V or 3381 * unrestricted guest mode. 3382 */ 3383 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, fNestedPagingAndFullGuestExec); 3384 AssertLogRelRCReturn(rc, rc); 3385 3386 /** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends} 3387 * Whether to expose the RDRAND instructions to the guest. For the time being 3388 * the default is to only do this for VMs with nested paging and AMD-V or 3389 * unrestricted guest mode. 3390 */ 3391 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec); 3392 AssertLogRelRCReturn(rc, rc); 3393 3394 /** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends} 3395 * Whether to expose the RDSEED instructions to the guest. For the time being 3396 * the default is to only do this for VMs with nested paging and AMD-V or 3397 * unrestricted guest mode. 3398 */ 3399 rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec); 3400 AssertLogRelRCReturn(rc, rc); 3284 3401 3285 3402 return VINF_SUCCESS; … … 3304 3421 RT_ZERO(Config); 3305 3422 3306 int rc = cpumR3CpuIdReadConfig(p Cpum, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM));3423 int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, HMAreNestedPagingAndFullGuestExecEnabled(pVM)); 3307 3424 AssertRCReturn(rc, rc); 3308 3425 … … 4446 4563 DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0), 4447 4564 DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0), 4565 DBGFREGSUBFIELD_RO("SDBG\0" "Sillicon debug interface", 11, 1, 0), 4448 4566 DBGFREGSUBFIELD_RO("FMA\0" "FMA Support", 12, 1, 0), 4449 4567 DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B", 13, 1, 0),
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