Changeset 54892 in vbox

Timestamp:

Mar 21, 2015 6:01:12 PM (10 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

99107

Message:

typo

Location:

trunk

Files:

• include/iprt/x86.h (modified) (1 diff)
• include/iprt/x86.mac (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (2 diffs)

trunk/include/iprt/x86.h

@@ -2495 +2495 @@
  * @{ */
 /** Exception Flag: Invalid operation.  */
-#define X86_MSXCR_IE          RT_BIT(0)
+#define X86_MXSCR_IE          RT_BIT(0)
 /** Exception Flag: Denormalized operand.  */
-#define X86_MSXCR_DE          RT_BIT(1)
+#define X86_MXSCR_DE          RT_BIT(1)
 /** Exception Flag: Zero divide.  */
-#define X86_MSXCR_ZE          RT_BIT(2)
+#define X86_MXSCR_ZE          RT_BIT(2)
 /** Exception Flag: Overflow.  */
-#define X86_MSXCR_OE          RT_BIT(3)
+#define X86_MXSCR_OE          RT_BIT(3)
 /** Exception Flag: Underflow.  */
-#define X86_MSXCR_UE          RT_BIT(4)
+#define X86_MXSCR_UE          RT_BIT(4)
 /** Exception Flag: Precision.  */
-#define X86_MSXCR_PE          RT_BIT(5)
+#define X86_MXSCR_PE          RT_BIT(5)
 
 /** Denormals are zero. */
-#define X86_MSXCR_DAZ         RT_BIT(6)
+#define X86_MXSCR_DAZ         RT_BIT(6)
 
 /** Exception Mask: Invalid operation. */
-#define X86_MSXCR_IM          RT_BIT(7)
+#define X86_MXSCR_IM          RT_BIT(7)
 /** Exception Mask: Denormalized operand. */
-#define X86_MSXCR_DM          RT_BIT(8)
+#define X86_MXSCR_DM          RT_BIT(8)
 /** Exception Mask: Zero divide.  */
-#define X86_MSXCR_ZM          RT_BIT(9)
+#define X86_MXSCR_ZM          RT_BIT(9)
 /** Exception Mask: Overflow.  */
-#define X86_MSXCR_OM          RT_BIT(10)
+#define X86_MXSCR_OM          RT_BIT(10)
 /** Exception Mask: Underflow.  */
-#define X86_MSXCR_UM          RT_BIT(11)
+#define X86_MXSCR_UM          RT_BIT(11)
 /** Exception Mask: Precision.  */
-#define X86_MSXCR_PM          RT_BIT(12)
+#define X86_MXSCR_PM          RT_BIT(12)
 
 /** Rounding control mask. */
-#define X86_MSXCR_RC_MASK     UINT16_C(0x6000)
+#define X86_MXSCR_RC_MASK     UINT16_C(0x6000)
 /** Rounding control: To nearest. */
-#define X86_MSXCR_RC_NEAREST  UINT16_C(0x0000)
+#define X86_MXSCR_RC_NEAREST  UINT16_C(0x0000)
 /** Rounding control: Down. */
-#define X86_MSXCR_RC_DOWN     UINT16_C(0x2000)
+#define X86_MXSCR_RC_DOWN     UINT16_C(0x2000)
 /** Rounding control: Up. */
-#define X86_MSXCR_RC_UP       UINT16_C(0x4000)
+#define X86_MXSCR_RC_UP       UINT16_C(0x4000)
 /** Rounding control: Towards zero. */
-#define X86_MSXCR_RC_ZERO     UINT16_C(0x6000)
+#define X86_MXSCR_RC_ZERO     UINT16_C(0x6000)
 
 /** Flush-to-zero for masked underflow.  */
-#define X86_MSXCR_FZ          RT_BIT(15)
+#define X86_MXSCR_FZ          RT_BIT(15)
 
 /** Misaligned Exception Mask.  */
-#define X86_MSXCR_MM          RT_BIT(16)
+#define X86_MXSCR_MM          RT_BIT(16)
 /** @} */
 

trunk/include/iprt/x86.mac

@@ -628 +628 @@
 %define X86_FCW_RC_ZERO     0x0c00
 %define X86_FCW_ZERO_MASK   0xf080
-%define X86_MSXCR_IE          RT_BIT(0)
-%define X86_MSXCR_DE          RT_BIT(1)
-%define X86_MSXCR_ZE          RT_BIT(2)
-%define X86_MSXCR_OE          RT_BIT(3)
-%define X86_MSXCR_UE          RT_BIT(4)
-%define X86_MSXCR_PE          RT_BIT(5)
-%define X86_MSXCR_DAZ         RT_BIT(6)
-%define X86_MSXCR_IM          RT_BIT(7)
-%define X86_MSXCR_DM          RT_BIT(8)
-%define X86_MSXCR_ZM          RT_BIT(9)
-%define X86_MSXCR_OM          RT_BIT(10)
-%define X86_MSXCR_UM          RT_BIT(11)
-%define X86_MSXCR_PM          RT_BIT(12)
-%define X86_MSXCR_RC_MASK     0x6000
-%define X86_MSXCR_RC_NEAREST  0x0000
-%define X86_MSXCR_RC_DOWN     0x2000
-%define X86_MSXCR_RC_UP       0x4000
-%define X86_MSXCR_RC_ZERO     0x6000
-%define X86_MSXCR_FZ          RT_BIT(15)
-%define X86_MSXCR_MM          RT_BIT(16)
+%define X86_MXSCR_IE          RT_BIT(0)
+%define X86_MXSCR_DE          RT_BIT(1)
+%define X86_MXSCR_ZE          RT_BIT(2)
+%define X86_MXSCR_OE          RT_BIT(3)
+%define X86_MXSCR_UE          RT_BIT(4)
+%define X86_MXSCR_PE          RT_BIT(5)
+%define X86_MXSCR_DAZ         RT_BIT(6)
+%define X86_MXSCR_IM          RT_BIT(7)
+%define X86_MXSCR_DM          RT_BIT(8)
+%define X86_MXSCR_ZM          RT_BIT(9)
+%define X86_MXSCR_OM          RT_BIT(10)
+%define X86_MXSCR_UM          RT_BIT(11)
+%define X86_MXSCR_PM          RT_BIT(12)
+%define X86_MXSCR_RC_MASK     0x6000
+%define X86_MXSCR_RC_NEAREST  0x0000
+%define X86_MXSCR_RC_DOWN     0x2000
+%define X86_MXSCR_RC_UP       0x4000
+%define X86_MXSCR_RC_ZERO     0x6000
+%define X86_MXSCR_FZ          RT_BIT(15)
+%define X86_MXSCR_MM          RT_BIT(16)
 %ifndef VBOX_FOR_DTRACE_LIB
 %endif

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -7172 +7172 @@
     /* The lazy approach for now... */
     /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
-    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MSXCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
+    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -7372 +7372 @@
 {
     /* The lazy approach for now... */
-    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MSXCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
+    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
         return iemRaiseGeneralProtectionFault0(pIemCpu);