VirtualBox

Changeset 54896 in vbox


Ignore:
Timestamp:
Mar 22, 2015 6:54:38 PM (10 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
99111
Message:

x86.h,VMM: XSAVE structures.

Location:
trunk
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/iprt/x86.h

    r54894 r54896  
    22512251    uint8_t reg[10];
    22522252} X86FPUMMX;
     2253#ifndef VBOX_FOR_DTRACE_LIB
     2254AssertCompileSize(X86FPUMMX, 10);
     2255#endif
    22532256/** Pointer to a 80-bit MMX/FPU register type. */
    22542257typedef X86FPUMMX *PX86FPUMMX;
    22552258/** Pointer to a const 80-bit MMX/FPU register type. */
    22562259typedef const X86FPUMMX *PCX86FPUMMX;
     2260
     2261/** FPU (x87) register. */
     2262typedef union X86FPUREG
     2263{
     2264    /** MMX view. */
     2265    uint64_t    mmx;
     2266    /** FPU view - todo. */
     2267    X86FPUMMX   fpu;
     2268    /** Extended precision floating point view. */
     2269    RTFLOAT80U  r80;
     2270    /** Extended precision floating point view v2 */
     2271    RTFLOAT80U2 r80Ex;
     2272    /** 8-bit view. */
     2273    uint8_t     au8[16];
     2274    /** 16-bit view. */
     2275    uint16_t    au16[8];
     2276    /** 32-bit view. */
     2277    uint32_t    au32[4];
     2278    /** 64-bit view. */
     2279    uint64_t    au64[2];
     2280    /** 128-bit view. (yeah, very helpful) */
     2281    uint128_t   au128[1];
     2282} X86FPUREG;
     2283#ifndef VBOX_FOR_DTRACE_LIB
     2284AssertCompileSize(X86FPUREG, 16);
     2285#endif
     2286/** Pointer to a FPU register. */
     2287typedef X86FPUREG *PX86FPUREG;
     2288/** Pointer to a const FPU register. */
     2289typedef X86FPUREG const *PCX86FPUREG;
     2290
     2291/**
     2292 * XMM register union.
     2293 */
     2294typedef union X86XMMREG
     2295{
     2296    /** XMM Register view *. */
     2297    uint128_t   xmm;
     2298    /** 8-bit view. */
     2299    uint8_t     au8[16];
     2300    /** 16-bit view. */
     2301    uint16_t    au16[8];
     2302    /** 32-bit view. */
     2303    uint32_t    au32[4];
     2304    /** 64-bit view. */
     2305    uint64_t    au64[2];
     2306    /** 128-bit view. (yeah, very helpful) */
     2307    uint128_t   au128[1];
     2308} X86XMMREG;
     2309#ifndef VBOX_FOR_DTRACE_LIB
     2310AssertCompileSize(X86XMMREG, 16);
     2311#endif
     2312/** Pointer to an XMM register state. */
     2313typedef X86XMMREG *PX86XMMREG;
     2314/** Pointer to a const XMM register state. */
     2315typedef X86XMMREG const *PCX86XMMREG;
     2316
     2317/**
     2318 * YMM register union.
     2319 */
     2320typedef union X86YMMREG
     2321{
     2322    /** 8-bit view. */
     2323    uint8_t     au8[32];
     2324    /** 16-bit view. */
     2325    uint16_t    au16[16];
     2326    /** 32-bit view. */
     2327    uint32_t    au32[8];
     2328    /** 64-bit view. */
     2329    uint64_t    au64[4];
     2330    /** 128-bit view. (yeah, very helpful) */
     2331    uint128_t   au128[2];
     2332    /** XMM sub register view. */
     2333    X86XMMREG   aXmm[2];
     2334} X86YMMREG;
     2335#ifndef VBOX_FOR_DTRACE_LIB
     2336AssertCompileSize(X86YMMREG, 32);
     2337#endif
     2338/** Pointer to an YMM register state. */
     2339typedef X86YMMREG *PX86YMMREG;
     2340/** Pointer to a const YMM register state. */
     2341typedef X86YMMREG const *PCX86YMMREG;
     2342
     2343/**
     2344 * ZMM register union.
     2345 */
     2346typedef union X86ZMMREG
     2347{
     2348    /** 8-bit view. */
     2349    uint8_t     au8[64];
     2350    /** 16-bit view. */
     2351    uint16_t    au16[32];
     2352    /** 32-bit view. */
     2353    uint32_t    au32[16];
     2354    /** 64-bit view. */
     2355    uint64_t    au64[8];
     2356    /** 128-bit view. (yeah, very helpful) */
     2357    uint128_t   au128[4];
     2358    /** XMM sub register view. */
     2359    X86XMMREG   aXmm[4];
     2360    /** YMM sub register view. */
     2361    X86YMMREG   aYmm[2];
     2362} X86ZMMREG;
     2363#ifndef VBOX_FOR_DTRACE_LIB
     2364AssertCompileSize(X86ZMMREG, 64);
     2365#endif
     2366/** Pointer to an ZMM register state. */
     2367typedef X86ZMMREG *PX86ZMMREG;
     2368/** Pointer to a const ZMM register state. */
     2369typedef X86ZMMREG const *PCX86ZMMREG;
     2370
    22572371
    22582372/**
    … …  
    22862400    /** 0x18 - FOS. */
    22872401    uint32_t    FPUOS;
    2288     /** 0x1c */
    2289     union
    2290     {
    2291         /** MMX view. */
    2292         uint64_t    mmx;
    2293         /** FPU view - todo. */
    2294         X86FPUMMX   fpu;
    2295         /** Extended precision floating point view. */
    2296         RTFLOAT80U  r80;
    2297         /** Extended precision floating point view v2. */
    2298         RTFLOAT80U2 r80Ex;
    2299         /** 8-bit view. */
    2300         uint8_t     au8[16];
    2301         /** 16-bit view. */
    2302         uint16_t    au16[8];
    2303         /** 32-bit view. */
    2304         uint32_t    au32[4];
    2305         /** 64-bit view. */
    2306         uint64_t    au64[2];
    2307         /** 128-bit view. (yeah, very helpful) */
    2308         uint128_t   au128[1];
    2309     } regs[8];
     2402    /** 0x1c - FPU register. */
     2403    X86FPUREG   regs[8];
    23102404} X86FPUSTATE;
    23112405#pragma pack()
    … …  
    23442438    /** 0x1c */
    23452439    uint32_t    MXCSR_MASK;
    2346     /** 0x20 */
    2347     union
    2348     {
    2349         /** MMX view. */
    2350         uint64_t    mmx;
    2351         /** FPU view - todo. */
    2352         X86FPUMMX   fpu;
    2353         /** Extended precision floating point view. */
    2354         RTFLOAT80U  r80;
    2355         /** Extended precision floating point view v2 */
    2356         RTFLOAT80U2 r80Ex;
    2357         /** 8-bit view. */
    2358         uint8_t     au8[16];
    2359         /** 16-bit view. */
    2360         uint16_t    au16[8];
    2361         /** 32-bit view. */
    2362         uint32_t    au32[4];
    2363         /** 64-bit view. */
    2364         uint64_t    au64[2];
    2365         /** 128-bit view. (yeah, very helpful) */
    2366         uint128_t   au128[1];
    2367     } aRegs[8];
    2368     /* - offset 160 - */
    2369     union
    2370     {
    2371         /** XMM Register view *. */
    2372         uint128_t   xmm;
    2373         /** 8-bit view. */
    2374         uint8_t     au8[16];
    2375         /** 16-bit view. */
    2376         uint16_t    au16[8];
    2377         /** 32-bit view. */
    2378         uint32_t    au32[4];
    2379         /** 64-bit view. */
    2380         uint64_t    au64[2];
    2381         /** 128-bit view. (yeah, very helpful) */
    2382         uint128_t   au128[1];
    2383     } aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
     2440    /** 0x20 - FPU registers. */
     2441    X86FPUREG   aRegs[8];
     2442    /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
     2443    X86XMMREG   aXMM[16];
    23842444    /* - offset 416 - */
    23852445    uint32_t    au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
    … …  
    25402600#define X86_MXSCR_MM          RT_BIT(17)
    25412601/** @} */
     2602
     2603/**
     2604 * XSAVE header.
     2605 */
     2606typedef struct X86XSAVEHDR
     2607{
     2608    /** XTATE_BV - Bitmap indicating whether a component is in the state. */
     2609    uint64_t        bmXState;
     2610    /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
     2611    uint64_t        bmXComp;
     2612    /** Reserved for furture extensions, probably MBZ. */
     2613    uint64_t        au64Reserved[6];
     2614} X86XSAVEHDR;
     2615#ifndef VBOX_FOR_DTRACE_LIB
     2616AssertCompileSize(X86XSAVEHDR, 64);
     2617#endif
     2618/** Pointer to an XSAVE header. */
     2619typedef X86XSAVEHDR *PX86XSAVEHDR;
     2620/** Pointer to a const XSAVE header. */
     2621typedef X86XSAVEHDR const *PCX86XSAVEHDR;
     2622
     2623
     2624/**
     2625 * The high 128-bit YMM register state (XSAVE_C_YMM).
     2626 * (The lower 128-bits being in X86FXSTATE.)
     2627 */
     2628typedef struct X86XSAVEYMMHI
     2629{
     2630    /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
     2631    X86XMMREG       aYmmHi[16];
     2632} X86XSAVEYMMHI;
     2633#ifndef VBOX_FOR_DTRACE_LIB
     2634AssertCompileSize(X86XSAVEYMMHI, 256);
     2635#endif
     2636/** Pointer to a high 128-bit YMM register state. */
     2637typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
     2638/** Pointer to a const high 128-bit YMM register state. */
     2639typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
     2640
     2641/**
     2642 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
     2643 */
     2644typedef struct X86XSAVEBNDREGS
     2645{
     2646    /** Array of registers (BND0...BND3). */
     2647    struct
     2648    {
     2649        /** Lower bound. */
     2650        uint64_t    uLowerBound;
     2651        /** Upper bound. */
     2652        uint64_t    uUpperBound;
     2653    } aRegs[4];
     2654} X86XSAVEBNDREGS;
     2655#ifndef VBOX_FOR_DTRACE_LIB
     2656AssertCompileSize(X86XSAVEBNDREGS, 64);
     2657#endif
     2658/** Pointer to a MPX bound register state. */
     2659typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
     2660/** Pointer to a const MPX bound register state. */
     2661typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
     2662
     2663/**
     2664 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
     2665 */
     2666typedef struct X86XSAVEBNDCFG
     2667{
     2668    uint64_t        fConfig;
     2669    uint64_t        fStatus;
     2670} X86XSAVEBNDCFG;
     2671#ifndef VBOX_FOR_DTRACE_LIB
     2672AssertCompileSize(X86XSAVEBNDCFG, 16);
     2673#endif
     2674/** Pointer to a MPX bound config and status register state. */
     2675typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
     2676/** Pointer to a const MPX bound config and status register state. */
     2677typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
     2678
     2679/**
     2680 * AVX-512 opmask state (XSAVE_C_OPMASK).
     2681 */
     2682typedef struct X86XSAVEOPMASK
     2683{
     2684    /** The K0..K7 values. */
     2685    uint64_t    aKRegs[8];
     2686} X86XSAVEOPMASK;
     2687#ifndef VBOX_FOR_DTRACE_LIB
     2688AssertCompileSize(X86XSAVEOPMASK, 64);
     2689#endif
     2690/** Pointer to a AVX-512 opmask state. */
     2691typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
     2692/** Pointer to a const AVX-512 opmask state. */
     2693typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
     2694
     2695/**
     2696 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
     2697 */
     2698typedef struct X86XSAVEZMMHI256
     2699{
     2700    /** Upper 256-bits of ZMM0-15. */
     2701    X86YMMREG   aHi256Regs[16];
     2702} X86XSAVEZMMHI256;
     2703#ifndef VBOX_FOR_DTRACE_LIB
     2704AssertCompileSize(X86XSAVEZMMHI256, 512);
     2705#endif
     2706/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
     2707typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
     2708/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
     2709typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
     2710
     2711/**
     2712 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
     2713 */
     2714typedef struct X86XSAVEZMM16HI
     2715{
     2716    /** ZMM16 thru ZMM31. */
     2717    X86ZMMREG   aRegs[16];
     2718} X86XSAVEZMM16HI;
     2719#ifndef VBOX_FOR_DTRACE_LIB
     2720AssertCompileSize(X86XSAVEZMM16HI, 1024);
     2721#endif
     2722/** Pointer to a state comprising ZMM16-32. */
     2723typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
     2724/** Pointer to a const state comprising ZMM16-32. */
     2725typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
     2726
     2727/**
     2728 * AMD Light weight profiling state (XSAVE_C_LWP).
     2729 *
     2730 * We probably won't play with this as AMD seems to be dropping from their "zen"
     2731 * processor micro architecture.
     2732 */
     2733typedef struct X86XSAVELWP
     2734{
     2735    /** Details when needed. */
     2736    uint64_t        auLater[128/8];
     2737} X86XSAVELWP;
     2738#ifndef VBOX_FOR_DTRACE_LIB
     2739AssertCompileSize(X86XSAVELWP, 128);
     2740#endif
     2741
     2742
     2743
     2744typedef struct X86XSAVEAREA
     2745{
     2746    /** The x87 and SSE region (or legacy region if you like).  */
     2747    X86FXSTATE      x87;
     2748    /** The XSAVE header. */
     2749    X86XSAVEHDR     Hdr;
     2750    /** Beyond the header, there isn't really a fixed layout, but we can
     2751       generally assume the YMM (AVX) register extensions are present and
     2752       follows immediately. */
     2753    union
     2754    {
     2755        /** This is a typical layout on intel CPUs (good for debuggers). */
     2756        struct
     2757        {
     2758            X86XSAVEYMMHI       YmmHi;
     2759            X86XSAVEBNDREGS     BndRegs;
     2760            X86XSAVEBNDCFG      BndCfg;
     2761            uint8_t             abFudgeToMatchDocs[0xB0];
     2762            X86XSAVEOPMASK      Opmask;
     2763            X86XSAVEZMMHI256    ZmmHi256;
     2764            X86XSAVEZMM16HI     Zmm16Hi;
     2765        } Intel;
     2766
     2767        /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
     2768        struct
     2769        {
     2770            X86XSAVEYMMHI       YmmHi;
     2771            X86XSAVELWP         Lwp;
     2772        } AmdBd;
     2773
     2774        /** Reserved 8K here for current and future state info. */
     2775        uint8_t         ab[8192 - 512 - 64];
     2776    } u;
     2777} X86XSAVEAREA;
     2778#ifndef VBOX_FOR_DTRACE_LIB
     2779AssertCompileSize(X86XSAVEAREA, 8192);
     2780AssertCompileMemberOffset(X86XSAVEAREA, Hdr,                0x200);
     2781AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi,      0x240);
     2782AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs,    0x340);
     2783AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg,     0x380);
     2784AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask,     0x440 /* 1088 */);
     2785AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256,   0x480 /* 1152 */);
     2786AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi,    0x680 /* 1664 */);
     2787#endif
     2788
     2789
     2790/** @name XSAVE_C_XXX - XSAVE State Components Bits.
     2791 * @{ */
     2792/** Bit 0 - x87 - Legacy FPU state. */
     2793#define XSAVE_C_X87         RT_BIT_64(0)
     2794/** Bit 1 - SSE - 128-bit SSE state. */
     2795#define XSAVE_C_SSE         RT_BIT_64(1)
     2796/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
     2797#define XSAVE_C_YMM         RT_BIT_64(2)
     2798/** Bit 3 - BNDREGS - MPX bound register state. */
     2799#define XSAVE_C_BNDREGS     RT_BIT_64(3)
     2800/** Bit 4 - BNDCSR - MPX bound config and status state. */
     2801#define XSAVE_C_BNDCSR      RT_BIT_64(4)
     2802/** Bit 5 - Opmask - opmask state. */
     2803#define XSAVE_C_OPMASK      RT_BIT_64(5)
     2804/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
     2805#define XSAVE_C_ZMM_HI256   RT_BIT_64(6)
     2806/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
     2807#define XSAVE_C_ZMM_16HI    RT_BIT_64(7)
     2808/** Bit 62 - LWP - Lightweight Profiling (AMD). */
     2809#define XSAVE_C_LWP         RT_BIT_64(62)
     2810/** @} */
     2811
    25422812
    25432813

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r54894 r54896  
    48054805    DBGFREGSUBFIELD_RO("SSE\0"       "128-bit SSE state",                                1, 1, 0),
    48064806    DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)",                  2, 1, 0),
    4807     DBGFREGSUBFIELD_RO("AVX\0"       "256-bit AVX state",                                3, 1, 0),
    4808     DBGFREGSUBFIELD_RO("BNDREGS\0"   "MPX bound register state",                         4, 1, 0),
    4809     DBGFREGSUBFIELD_RO("BNDCSR\0"    "MPX bound config and status state",                5, 1, 0),
    4810     DBGFREGSUBFIELD_RO("Opmask\0"    "opmask state",                                     6, 1, 0),
    4811     DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)",              7, 1, 0),
    4812     DBGFREGSUBFIELD_RO("Hi16_ZMM\0"  "512-bits ZMM16-31 state (AVX-512)",                8, 1, 0),
     4807    DBGFREGSUBFIELD_RO("BNDREGS\0"   "MPX bound register state",                         3, 1, 0),
     4808    DBGFREGSUBFIELD_RO("BNDCSR\0"    "MPX bound config and status state",                4, 1, 0),
     4809    DBGFREGSUBFIELD_RO("Opmask\0"    "opmask state",                                     5, 1, 0),
     4810    DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)",              6, 1, 0),
     4811    DBGFREGSUBFIELD_RO("Hi16_ZMM\0"  "512-bits ZMM16-31 state (AVX-512)",                7, 1, 0),
     4812    DBGFREGSUBFIELD_RO("LWP\0"       "Lightweight Profiling (AMD)",                     62, 1, 0),
    48134813    DBGFREGSUBFIELD_TERMINATOR()
    48144814};
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette