Index: /trunk/include/VBox/vmm/cpum.mac
===================================================================
--- /trunk/include/VBox/vmm/cpum.mac	(revision 54897)
+++ /trunk/include/VBox/vmm/cpum.mac	(revision 54898)
@@ -133,6 +133,8 @@
 
 
+%define XSTATE_SIZE             8192
+
 struc CPUMCTX
-    .fpu                resb    512
+    .XState             resb    XSTATE_SIZE
     .eax                resq    1
     .ecx                resq    1
Index: /trunk/include/VBox/vmm/cpumctx.h
===================================================================
--- /trunk/include/VBox/vmm/cpumctx.h	(revision 54897)
+++ /trunk/include/VBox/vmm/cpumctx.h	(revision 54898)
@@ -250,5 +250,5 @@
      * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
      *       actual format or convert it (waste of time).  */
-    X86FXSTATE      fpu;
+    X86XSAVEAREA        XState;
 
     /** CPUMCTXCORE Part.
Index: /trunk/include/VBox/vmm/vm.h
===================================================================
--- /trunk/include/VBox/vmm/vm.h	(revision 54897)
+++ /trunk/include/VBox/vmm/vm.h	(revision 54898)
@@ -231,4 +231,13 @@
     uint8_t                 abAlignment2[3584];
 
+    /** PGM part. */
+    union
+    {
+#ifdef ___PGMInternal_h
+        struct PGMCPU       s;
+#endif
+        uint8_t             padding[4096];      /* multiple of 4096 */
+    } pgm;
+
     /** CPUM part. */
     union
@@ -237,15 +246,6 @@
         struct CPUMCPU      s;
 #endif
-        uint8_t             padding[4096];      /* multiple of 4096 */
+        uint8_t             padding[28672];      /* multiple of 4096 */
     } cpum;
-
-    /** PGM part. */
-    union
-    {
-#ifdef ___PGMInternal_h
-        struct PGMCPU       s;
-#endif
-        uint8_t             padding[4096];      /* multiple of 4096 */
-    } pgm;
 
 } VMCPU;
Index: /trunk/include/VBox/vmm/vm.mac
===================================================================
--- /trunk/include/VBox/vmm/vm.mac	(revision 54897)
+++ /trunk/include/VBox/vmm/vm.mac	(revision 54898)
@@ -146,6 +146,8 @@
 
     alignb 4096
-    .cpum                   resb 4096
     .pgm                    resb 4096
+    alignb 4096
+    .cpum                   resb 28672
+    alignb 4096
 endstruc
 
Index: /trunk/include/iprt/x86.h
===================================================================
--- /trunk/include/iprt/x86.h	(revision 54897)
+++ /trunk/include/iprt/x86.h	(revision 54898)
@@ -2772,5 +2772,9 @@
         } AmdBd;
 
-        /** Reserved 8K here for current and future state info. */
+        /** To enbling static deployments that have a reasonable chance of working for
+         * the next 3-6 CPU generations without running short on space, we allocate a
+         * lot of extra space here, making the structure a round 8KB in size.  This
+         * leaves us 7616 bytes for extended state.  The skylake xeons are likely to use
+         * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
         uint8_t         ab[8192 - 512 - 64];
     } u;
@@ -2778,4 +2782,5 @@
 #ifndef VBOX_FOR_DTRACE_LIB
 AssertCompileSize(X86XSAVEAREA, 8192);
+AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
 AssertCompileMemberOffset(X86XSAVEAREA, Hdr,                0x200);
 AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi,      0x240);
Index: /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 54898)
@@ -5229,24 +5229,24 @@
 DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PIEMCPU pIemCpu, PCPUMCTX pCtx)
 {
-    pCtx->fpu.FOP   = pIemCpu->abOpcode[pIemCpu->offFpuOpcode]
+    pCtx->XState.x87.FOP   = pIemCpu->abOpcode[pIemCpu->offFpuOpcode]
                     | ((uint16_t)(pIemCpu->abOpcode[pIemCpu->offFpuOpcode - 1] & 0x7) << 8);
-    /** @todo FPU.CS and FPUIP needs to be kept seperately. */
+    /** @todo XState.x87.CS and FPUIP needs to be kept seperately. */
     if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
     {
         /** @todo Testcase: making assumptions about how FPUIP and FPUDP are handled
          *        happens in real mode here based on the fnsave and fnstenv images. */
-        pCtx->fpu.CS    = 0;
-        pCtx->fpu.FPUIP = pCtx->eip | ((uint32_t)pCtx->cs.Sel << 4);
+        pCtx->XState.x87.CS    = 0;
+        pCtx->XState.x87.FPUIP = pCtx->eip | ((uint32_t)pCtx->cs.Sel << 4);
     }
     else
     {
-        pCtx->fpu.CS    = pCtx->cs.Sel;
-        pCtx->fpu.FPUIP = pCtx->rip;
-    }
-}
-
-
-/**
- * Updates the FPU.DS and FPUDP registers.
+        pCtx->XState.x87.CS    = pCtx->cs.Sel;
+        pCtx->XState.x87.FPUIP = pCtx->rip;
+    }
+}
+
+
+/**
+ * Updates the XState.x87.DS and FPUDP registers.
  *
  * @param   pIemCpu             The IEM per CPU data.
@@ -5270,14 +5270,14 @@
             sel = pCtx->ds.Sel;
     }
-    /** @todo FPU.DS and FPUDP needs to be kept seperately. */
+    /** @todo XState.x87.DS and FPUDP needs to be kept seperately. */
     if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
     {
-        pCtx->fpu.DS    = 0;
-        pCtx->fpu.FPUDP = (uint32_t)GCPtrEff | ((uint32_t)sel << 4);
+        pCtx->XState.x87.DS    = 0;
+        pCtx->XState.x87.FPUDP = (uint32_t)GCPtrEff | ((uint32_t)sel << 4);
     }
     else
     {
-        pCtx->fpu.DS    = sel;
-        pCtx->fpu.FPUDP = GCPtrEff;
+        pCtx->XState.x87.DS    = sel;
+        pCtx->XState.x87.FPUDP = GCPtrEff;
     }
 }
@@ -5293,13 +5293,13 @@
 DECLINLINE(void) iemFpuRotateStackPush(PCPUMCTX pCtx)
 {
-    RTFLOAT80U r80Tmp = pCtx->fpu.aRegs[7].r80;
-    pCtx->fpu.aRegs[7].r80 = pCtx->fpu.aRegs[6].r80;
-    pCtx->fpu.aRegs[6].r80 = pCtx->fpu.aRegs[5].r80;
-    pCtx->fpu.aRegs[5].r80 = pCtx->fpu.aRegs[4].r80;
-    pCtx->fpu.aRegs[4].r80 = pCtx->fpu.aRegs[3].r80;
-    pCtx->fpu.aRegs[3].r80 = pCtx->fpu.aRegs[2].r80;
-    pCtx->fpu.aRegs[2].r80 = pCtx->fpu.aRegs[1].r80;
-    pCtx->fpu.aRegs[1].r80 = pCtx->fpu.aRegs[0].r80;
-    pCtx->fpu.aRegs[0].r80 = r80Tmp;
+    RTFLOAT80U r80Tmp = pCtx->XState.x87.aRegs[7].r80;
+    pCtx->XState.x87.aRegs[7].r80 = pCtx->XState.x87.aRegs[6].r80;
+    pCtx->XState.x87.aRegs[6].r80 = pCtx->XState.x87.aRegs[5].r80;
+    pCtx->XState.x87.aRegs[5].r80 = pCtx->XState.x87.aRegs[4].r80;
+    pCtx->XState.x87.aRegs[4].r80 = pCtx->XState.x87.aRegs[3].r80;
+    pCtx->XState.x87.aRegs[3].r80 = pCtx->XState.x87.aRegs[2].r80;
+    pCtx->XState.x87.aRegs[2].r80 = pCtx->XState.x87.aRegs[1].r80;
+    pCtx->XState.x87.aRegs[1].r80 = pCtx->XState.x87.aRegs[0].r80;
+    pCtx->XState.x87.aRegs[0].r80 = r80Tmp;
 }
 
@@ -5314,13 +5314,13 @@
 DECLINLINE(void) iemFpuRotateStackPop(PCPUMCTX pCtx)
 {
-    RTFLOAT80U r80Tmp = pCtx->fpu.aRegs[0].r80;
-    pCtx->fpu.aRegs[0].r80 = pCtx->fpu.aRegs[1].r80;
-    pCtx->fpu.aRegs[1].r80 = pCtx->fpu.aRegs[2].r80;
-    pCtx->fpu.aRegs[2].r80 = pCtx->fpu.aRegs[3].r80;
-    pCtx->fpu.aRegs[3].r80 = pCtx->fpu.aRegs[4].r80;
-    pCtx->fpu.aRegs[4].r80 = pCtx->fpu.aRegs[5].r80;
-    pCtx->fpu.aRegs[5].r80 = pCtx->fpu.aRegs[6].r80;
-    pCtx->fpu.aRegs[6].r80 = pCtx->fpu.aRegs[7].r80;
-    pCtx->fpu.aRegs[7].r80 = r80Tmp;
+    RTFLOAT80U r80Tmp = pCtx->XState.x87.aRegs[0].r80;
+    pCtx->XState.x87.aRegs[0].r80 = pCtx->XState.x87.aRegs[1].r80;
+    pCtx->XState.x87.aRegs[1].r80 = pCtx->XState.x87.aRegs[2].r80;
+    pCtx->XState.x87.aRegs[2].r80 = pCtx->XState.x87.aRegs[3].r80;
+    pCtx->XState.x87.aRegs[3].r80 = pCtx->XState.x87.aRegs[4].r80;
+    pCtx->XState.x87.aRegs[4].r80 = pCtx->XState.x87.aRegs[5].r80;
+    pCtx->XState.x87.aRegs[5].r80 = pCtx->XState.x87.aRegs[6].r80;
+    pCtx->XState.x87.aRegs[6].r80 = pCtx->XState.x87.aRegs[7].r80;
+    pCtx->XState.x87.aRegs[7].r80 = r80Tmp;
 }
 
@@ -5337,31 +5337,31 @@
 {
     /* Update FSW and bail if there are pending exceptions afterwards. */
-    uint16_t fFsw = pCtx->fpu.FSW & ~X86_FSW_C_MASK;
+    uint16_t fFsw = pCtx->XState.x87.FSW & ~X86_FSW_C_MASK;
     fFsw |= pResult->FSW & ~X86_FSW_TOP_MASK;
-    if (   (fFsw          & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
-        & ~(pCtx->fpu.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
-    {
-        pCtx->fpu.FSW = fFsw;
+    if (   (fFsw                 & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
+        & ~(pCtx->XState.x87.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
+    {
+        pCtx->XState.x87.FSW = fFsw;
         return;
     }
 
     uint16_t iNewTop = (X86_FSW_TOP_GET(fFsw) + 7) & X86_FSW_TOP_SMASK;
-    if (!(pCtx->fpu.FTW & RT_BIT(iNewTop)))
+    if (!(pCtx->XState.x87.FTW & RT_BIT(iNewTop)))
     {
         /* All is fine, push the actual value. */
-        pCtx->fpu.FTW |= RT_BIT(iNewTop);
-        pCtx->fpu.aRegs[7].r80 = pResult->r80Result;
-    }
-    else if (pCtx->fpu.FCW & X86_FCW_IM)
+        pCtx->XState.x87.FTW |= RT_BIT(iNewTop);
+        pCtx->XState.x87.aRegs[7].r80 = pResult->r80Result;
+    }
+    else if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked stack overflow, push QNaN. */
         fFsw |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1;
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[7].r80);
     }
     else
     {
         /* Raise stack overflow, don't push anything. */
-        pCtx->fpu.FSW |= pResult->FSW & ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
+        pCtx->XState.x87.FSW |= pResult->FSW & ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
         return;
     }
@@ -5369,5 +5369,5 @@
     fFsw &= ~X86_FSW_TOP_MASK;
     fFsw |= iNewTop << X86_FSW_TOP_SHIFT;
-    pCtx->fpu.FSW = fFsw;
+    pCtx->XState.x87.FSW = fFsw;
 
     iemFpuRotateStackPush(pCtx);
@@ -5386,9 +5386,9 @@
 {
     Assert(iStReg < 8);
-    uint16_t  iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
-    pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-    pCtx->fpu.FSW |= pResult->FSW & ~X86_FSW_TOP_MASK;
-    pCtx->fpu.FTW |= RT_BIT(iReg);
-    pCtx->fpu.aRegs[iStReg].r80 = pResult->r80Result;
+    uint16_t  iReg = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+    pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+    pCtx->XState.x87.FSW |= pResult->FSW & ~X86_FSW_TOP_MASK;
+    pCtx->XState.x87.FTW |= RT_BIT(iReg);
+    pCtx->XState.x87.aRegs[iStReg].r80 = pResult->r80Result;
 }
 
@@ -5403,6 +5403,6 @@
 static void iemFpuUpdateFSWOnly(PCPUMCTX pCtx, uint16_t u16FSW)
 {
-    pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-    pCtx->fpu.FSW |= u16FSW & ~X86_FSW_TOP_MASK;
+    pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+    pCtx->XState.x87.FSW |= u16FSW & ~X86_FSW_TOP_MASK;
 }
 
@@ -5416,7 +5416,7 @@
 {
     /* Check pending exceptions. */
-    uint16_t uFSW = pCtx->fpu.FSW;
-    if (   (pCtx->fpu.FSW & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
-        & ~(pCtx->fpu.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
+    uint16_t uFSW = pCtx->XState.x87.FSW;
+    if (   (pCtx->XState.x87.FSW & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
+        & ~(pCtx->XState.x87.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
         return;
 
@@ -5425,9 +5425,9 @@
     uFSW &= ~X86_FSW_TOP_MASK;
     uFSW |= (iOldTop + (UINT16_C(9) << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
-    pCtx->fpu.FSW = uFSW;
+    pCtx->XState.x87.FSW = uFSW;
 
     /* Mark the previous ST0 as empty. */
     iOldTop >>= X86_FSW_TOP_SHIFT;
-    pCtx->fpu.FTW &= ~RT_BIT(iOldTop);
+    pCtx->XState.x87.FTW &= ~RT_BIT(iOldTop);
 
     /* Rotate the registers. */
@@ -5481,33 +5481,33 @@
 
     /* Update FSW and bail if there are pending exceptions afterwards. */
-    uint16_t fFsw = pCtx->fpu.FSW & ~X86_FSW_C_MASK;
+    uint16_t fFsw = pCtx->XState.x87.FSW & ~X86_FSW_C_MASK;
     fFsw |= pResult->FSW & ~X86_FSW_TOP_MASK;
     if (   (fFsw          & (X86_FSW_IE | X86_FSW_ZE | X86_FSW_DE))
-        & ~(pCtx->fpu.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
-    {
-        pCtx->fpu.FSW = fFsw;
+        & ~(pCtx->XState.x87.FCW & (X86_FCW_IM | X86_FCW_ZM | X86_FCW_DM)))
+    {
+        pCtx->XState.x87.FSW = fFsw;
         return;
     }
 
     uint16_t iNewTop = (X86_FSW_TOP_GET(fFsw) + 7) & X86_FSW_TOP_SMASK;
-    if (!(pCtx->fpu.FTW & RT_BIT(iNewTop)))
+    if (!(pCtx->XState.x87.FTW & RT_BIT(iNewTop)))
     {
         /* All is fine, push the actual value. */
-        pCtx->fpu.FTW |= RT_BIT(iNewTop);
-        pCtx->fpu.aRegs[0].r80 = pResult->r80Result1;
-        pCtx->fpu.aRegs[7].r80 = pResult->r80Result2;
-    }
-    else if (pCtx->fpu.FCW & X86_FCW_IM)
+        pCtx->XState.x87.FTW |= RT_BIT(iNewTop);
+        pCtx->XState.x87.aRegs[0].r80 = pResult->r80Result1;
+        pCtx->XState.x87.aRegs[7].r80 = pResult->r80Result2;
+    }
+    else if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked stack overflow, push QNaN. */
         fFsw |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1;
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[0].r80);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[7].r80);
     }
     else
     {
         /* Raise stack overflow, don't push anything. */
-        pCtx->fpu.FSW |= pResult->FSW & ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
+        pCtx->XState.x87.FSW |= pResult->FSW & ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_C1 | X86_FSW_B | X86_FSW_ES;
         return;
     }
@@ -5515,5 +5515,5 @@
     fFsw &= ~X86_FSW_TOP_MASK;
     fFsw |= iNewTop << X86_FSW_TOP_SHIFT;
-    pCtx->fpu.FSW = fFsw;
+    pCtx->XState.x87.FSW = fFsw;
 
     iemFpuRotateStackPush(pCtx);
@@ -5619,6 +5619,6 @@
     Assert(iStReg < 8);
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    uint8_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
-    pCtx->fpu.FTW &= ~RT_BIT(iReg);
+    uint8_t iReg = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+    pCtx->XState.x87.FTW &= ~RT_BIT(iReg);
 }
 
@@ -5632,10 +5632,10 @@
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t uFsw = pCtx->fpu.FSW;
+    uint16_t uFsw = pCtx->XState.x87.FSW;
     uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
     uTop  = (uTop + (1 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
     uFsw &= ~X86_FSW_TOP_MASK;
     uFsw |= uTop;
-    pCtx->fpu.FSW = uFsw;
+    pCtx->XState.x87.FSW = uFsw;
 }
 
@@ -5649,10 +5649,10 @@
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t uFsw = pCtx->fpu.FSW;
+    uint16_t uFsw = pCtx->XState.x87.FSW;
     uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
     uTop  = (uTop + (7 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
     uFsw &= ~X86_FSW_TOP_MASK;
     uFsw |= uTop;
-    pCtx->fpu.FSW = uFsw;
+    pCtx->XState.x87.FSW = uFsw;
 }
 
@@ -5748,20 +5748,20 @@
 {
     Assert(iStReg < 8 || iStReg == UINT8_MAX);
-    if (pCtx->fpu.FCW & X86_FCW_IM)
+    if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked underflow. */
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF;
-        uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF;
+        uint16_t iReg = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + iStReg) & X86_FSW_TOP_SMASK;
         if (iStReg != UINT8_MAX)
         {
-            pCtx->fpu.FTW |= RT_BIT(iReg);
-            iemFpuStoreQNan(&pCtx->fpu.aRegs[iStReg].r80);
+            pCtx->XState.x87.FTW |= RT_BIT(iReg);
+            iemFpuStoreQNan(&pCtx->XState.x87.aRegs[iStReg].r80);
         }
     }
     else
     {
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 }
@@ -5830,13 +5830,13 @@
     iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
 
-    if (pCtx->fpu.FCW & X86_FCW_IM)
+    if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked overflow - Push QNaN. */
-        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
-        pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF;
-        pCtx->fpu.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
-        pCtx->fpu.FTW |= RT_BIT(iNewTop);
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
+        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + 7) & X86_FSW_TOP_SMASK;
+        pCtx->XState.x87.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF;
+        pCtx->XState.x87.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
+        pCtx->XState.x87.FTW |= RT_BIT(iNewTop);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[7].r80);
         iemFpuRotateStackPush(pCtx);
     }
@@ -5844,6 +5844,6 @@
     {
         /* Exception pending - don't change TOP or the register stack. */
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 }
@@ -5856,14 +5856,14 @@
     iemFpuUpdateOpcodeAndIpWorker(pIemCpu, pCtx);
 
-    if (pCtx->fpu.FCW & X86_FCW_IM)
+    if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked overflow - Push QNaN. */
-        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
-        pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF;
-        pCtx->fpu.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
-        pCtx->fpu.FTW |= RT_BIT(iNewTop);
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
+        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + 7) & X86_FSW_TOP_SMASK;
+        pCtx->XState.x87.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF;
+        pCtx->XState.x87.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
+        pCtx->XState.x87.FTW |= RT_BIT(iNewTop);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[0].r80);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[7].r80);
         iemFpuRotateStackPush(pCtx);
     }
@@ -5871,6 +5871,6 @@
     {
         /* Exception pending - don't change TOP or the register stack. */
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 }
@@ -5885,13 +5885,13 @@
 static void iemFpuStackPushOverflowOnly(PIEMCPU pIemCpu, PCPUMCTX pCtx)
 {
-    if (pCtx->fpu.FCW & X86_FCW_IM)
+    if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked overflow. */
-        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + 7) & X86_FSW_TOP_SMASK;
-        pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
-        pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
-        pCtx->fpu.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
-        pCtx->fpu.FTW |= RT_BIT(iNewTop);
-        iemFpuStoreQNan(&pCtx->fpu.aRegs[7].r80);
+        uint16_t iNewTop = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + 7) & X86_FSW_TOP_SMASK;
+        pCtx->XState.x87.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_C_MASK);
+        pCtx->XState.x87.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
+        pCtx->XState.x87.FSW |= iNewTop << X86_FSW_TOP_SHIFT;
+        pCtx->XState.x87.FTW |= RT_BIT(iNewTop);
+        iemFpuStoreQNan(&pCtx->XState.x87.aRegs[7].r80);
         iemFpuRotateStackPush(pCtx);
     }
@@ -5899,6 +5899,6 @@
     {
         /* Exception pending - don't change TOP or the register stack. */
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 }
@@ -5938,6 +5938,6 @@
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
-    if (pCtx->fpu.FTW & RT_BIT(iReg))
+    uint16_t iReg = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+    if (pCtx->XState.x87.FTW & RT_BIT(iReg))
         return VINF_SUCCESS;
     return VERR_NOT_FOUND;
@@ -5948,8 +5948,8 @@
 {
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t iReg = (X86_FSW_TOP_GET(pCtx->fpu.FSW) + iStReg) & X86_FSW_TOP_SMASK;
-    if (pCtx->fpu.FTW & RT_BIT(iReg))
-    {
-        *ppRef = &pCtx->fpu.aRegs[iStReg].r80;
+    uint16_t iReg = (X86_FSW_TOP_GET(pCtx->XState.x87.FSW) + iStReg) & X86_FSW_TOP_SMASK;
+    if (pCtx->XState.x87.FTW & RT_BIT(iReg))
+    {
+        *ppRef = &pCtx->XState.x87.aRegs[iStReg].r80;
         return VINF_SUCCESS;
     }
@@ -5962,11 +5962,11 @@
 {
     PCPUMCTX pCtx  = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t iTop  = X86_FSW_TOP_GET(pCtx->fpu.FSW);
+    uint16_t iTop  = X86_FSW_TOP_GET(pCtx->XState.x87.FSW);
     uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
     uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
-    if ((pCtx->fpu.FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
-    {
-        *ppRef0 = &pCtx->fpu.aRegs[iStReg0].r80;
-        *ppRef1 = &pCtx->fpu.aRegs[iStReg1].r80;
+    if ((pCtx->XState.x87.FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
+    {
+        *ppRef0 = &pCtx->XState.x87.aRegs[iStReg0].r80;
+        *ppRef1 = &pCtx->XState.x87.aRegs[iStReg1].r80;
         return VINF_SUCCESS;
     }
@@ -5978,10 +5978,10 @@
 {
     PCPUMCTX pCtx  = pIemCpu->CTX_SUFF(pCtx);
-    uint16_t iTop  = X86_FSW_TOP_GET(pCtx->fpu.FSW);
+    uint16_t iTop  = X86_FSW_TOP_GET(pCtx->XState.x87.FSW);
     uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
     uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
-    if ((pCtx->fpu.FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
-    {
-        *ppRef0 = &pCtx->fpu.aRegs[iStReg0].r80;
+    if ((pCtx->XState.x87.FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
+    {
+        *ppRef0 = &pCtx->XState.x87.aRegs[iStReg0].r80;
         return VINF_SUCCESS;
     }
@@ -5997,10 +5997,10 @@
 static void iemFpuRecalcExceptionStatus(PCPUMCTX pCtx)
 {
-    uint16_t u16Fsw = pCtx->fpu.FSW;
-    if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pCtx->fpu.FCW & X86_FCW_XCPT_MASK))
+    uint16_t u16Fsw = pCtx->XState.x87.FSW;
+    if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pCtx->XState.x87.FCW & X86_FCW_XCPT_MASK))
         u16Fsw |= X86_FSW_ES | X86_FSW_B;
     else
         u16Fsw &= ~(X86_FSW_ES | X86_FSW_B);
-    pCtx->fpu.FSW = u16Fsw;
+    pCtx->XState.x87.FSW = u16Fsw;
 }
 
@@ -6014,7 +6014,7 @@
 static uint16_t iemFpuCalcFullFtw(PCCPUMCTX pCtx)
 {
-    uint8_t const   u8Ftw  = (uint8_t)pCtx->fpu.FTW;
+    uint8_t const   u8Ftw  = (uint8_t)pCtx->XState.x87.FTW;
     uint16_t        u16Ftw = 0;
-    unsigned const  iTop   = X86_FSW_TOP_GET(pCtx->fpu.FSW);
+    unsigned const  iTop   = X86_FSW_TOP_GET(pCtx->XState.x87.FSW);
     for (unsigned iSt = 0; iSt < 8; iSt++)
     {
@@ -6025,5 +6025,5 @@
         {
             uint16_t uTag;
-            PCRTFLOAT80U const pr80Reg = &pCtx->fpu.aRegs[iSt].r80;
+            PCRTFLOAT80U const pr80Reg = &pCtx->XState.x87.aRegs[iSt].r80;
             if (pr80Reg->s.uExponent == 0x7fff)
                 uTag = 2; /* Exponent is all 1's => Special. */
@@ -7172,5 +7172,5 @@
     /* The lazy approach for now... */
     /** @todo testcase: Ordering of \#SS(0) vs \#GP() vs \#PF on SSE stuff. */
-    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
+    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->XState.x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -7372,5 +7372,5 @@
 {
     /* The lazy approach for now... */
-    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->fpu.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
+    if ((GCPtrMem & 15) && !(pIemCpu->CTX_SUFF(pCtx)->XState.x87.MXCSR & X86_MXSCR_MM)) /** @todo should probably check this *after* applying seg.u64Base... Check real HW. */
         return iemRaiseGeneralProtectionFault0(pIemCpu);
 
@@ -8304,5 +8304,5 @@
 #define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
     do { \
-        if ((pIemCpu)->CTX_SUFF(pCtx)->fpu.FSW & X86_FSW_ES) \
+        if ((pIemCpu)->CTX_SUFF(pCtx)->XState.x87.FSW & X86_FSW_ES) \
             return iemRaiseMathFault(pIemCpu); \
     } while (0)
@@ -8387,6 +8387,6 @@
 #define IEM_MC_FETCH_EFLAGS(a_EFlags)                   (a_EFlags) = (pIemCpu)->CTX_SUFF(pCtx)->eflags.u
 #define IEM_MC_FETCH_EFLAGS_U8(a_EFlags)                (a_EFlags) = (uint8_t)(pIemCpu)->CTX_SUFF(pCtx)->eflags.u
-#define IEM_MC_FETCH_FSW(a_u16Fsw)                      (a_u16Fsw) = pIemCpu->CTX_SUFF(pCtx)->fpu.FSW
-#define IEM_MC_FETCH_FCW(a_u16Fcw)                      (a_u16Fcw) = pIemCpu->CTX_SUFF(pCtx)->fpu.FCW
+#define IEM_MC_FETCH_FSW(a_u16Fsw)                      (a_u16Fsw) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.FSW
+#define IEM_MC_FETCH_FCW(a_u16Fcw)                      (a_u16Fcw) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.FCW
 
 #define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value)        *iemGRegRefU8(pIemCpu, (a_iGReg)) = (a_u8Value)
@@ -8401,5 +8401,5 @@
 #define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst)    do { (a_pu32Dst)[1] = 0; } while (0)
 #define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
 
 #define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg)           (a_pu8Dst) = iemGRegRefU8(pIemCpu, (a_iGReg))
@@ -8492,44 +8492,44 @@
 #define IEM_MC_FLIP_EFL_BIT(a_fBit)                     do { (pIemCpu)->CTX_SUFF(pCtx)->eflags.u ^= (a_fBit); } while (0)
 
-#define IEM_MC_CLEAR_FSW_EX()   do { (pIemCpu)->CTX_SUFF(pCtx)->fpu.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
+#define IEM_MC_CLEAR_FSW_EX()   do { (pIemCpu)->CTX_SUFF(pCtx)->XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
 
 
 #define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
-    do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx; } while (0)
+    do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
 #define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
-    do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].au32[0]; } while (0)
+    do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
 #define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx = (a_u64Value); } while (0)
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); } while (0)
 #define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); } while (0)
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); } while (0)
 #define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg)         \
-        (a_pu64Dst) = (&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
+        (a_pu64Dst) = (&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx)
 #define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
-        (a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
+        (a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx)
 #define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
-        (a_pu32Dst) = ((uint32_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aRegs[(a_iMReg)].mmx)
+        (a_pu32Dst) = ((uint32_t const *)&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aRegs[(a_iMReg)].mmx)
 
 #define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
-    do { (a_u128Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm; } while (0)
+    do { (a_u128Value) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].xmm; } while (0)
 #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
-    do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0]; } while (0)
+    do { (a_u64Value) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
 #define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
-    do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au32[0]; } while (0)
+    do { (a_u32Value) = pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
 #define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm = (a_u128Value); } while (0)
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].xmm = (a_u128Value); } while (0)
 #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
-         pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[1] = 0; \
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
+         pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
     } while (0)
 #define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
-    do { pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
-         pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[1] = 0; \
+    do { pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
+         pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
     } while (0)
 #define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg)       \
-    (a_pu128Dst) = (&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm)
+    (a_pu128Dst) = (&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].xmm)
 #define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
-    (a_pu128Dst) = ((uint128_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].xmm)
+    (a_pu128Dst) = ((uint128_t const *)&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].xmm)
 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
-    (a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->fpu.aXMM[(a_iXReg)].au64[0])
+    (a_pu64Dst) = ((uint64_t const *)&pIemCpu->CTX_SUFF(pCtx)->XState.x87.aXMM[(a_iXReg)].au64[0])
 
 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
@@ -8739,5 +8739,5 @@
         if (   !(a_u16FSW & X86_FSW_ES) \
             || !(  (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
-                 & ~(pIemCpu->CTX_SUFF(pCtx)->fpu.FCW & X86_FCW_MASK_ALL) ) ) \
+                 & ~(pIemCpu->CTX_SUFF(pCtx)->XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
             IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pIemCpu, (a_pvMem), (a_fAccess))); \
     } while (0)
@@ -8875,5 +8875,5 @@
     do { \
         iemFpuPrepareUsage(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0)); \
     } while (0)
 
@@ -8888,5 +8888,5 @@
     do { \
         iemFpuPrepareUsage(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1)); \
     } while (0)
 
@@ -8902,5 +8902,5 @@
     do { \
         iemFpuPrepareUsage(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1), (a2)); \
     } while (0)
 
@@ -9019,5 +9019,5 @@
     do { \
         iemFpuPrepareUsage(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1)); \
     } while (0)
 
@@ -9033,5 +9033,5 @@
     do { \
         iemFpuPrepareUsage(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1), (a2)); \
     } while (0)
 
@@ -9047,5 +9047,5 @@
     do { \
         iemFpuPrepareUsageSse(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1)); \
     } while (0)
 
@@ -9061,5 +9061,5 @@
     do { \
         iemFpuPrepareUsageSse(pIemCpu); \
-        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->fpu, (a0), (a1), (a2)); \
+        a_pfnAImpl(&pIemCpu->CTX_SUFF(pCtx)->XState.x87, (a0), (a1), (a2)); \
     } while (0)
 
@@ -9131,5 +9131,5 @@
     if (iemFpu2StRegsNotEmptyRefFirst(pIemCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
 #define IEM_MC_IF_FCW_IM() \
-    if (pIemCpu->CTX_SUFF(pCtx)->fpu.FCW & X86_FCW_IM) {
+    if (pIemCpu->CTX_SUFF(pCtx)->XState.x87.FCW & X86_FCW_IM) {
 
 #define IEM_MC_ELSE()                                   } else {
@@ -10219,58 +10219,58 @@
         if (fRem)
         {
-            pOrgCtx->fpu.FOP        = pDebugCtx->fpu.FOP;
-            pOrgCtx->fpu.FPUIP      = pDebugCtx->fpu.FPUIP;
-            pOrgCtx->fpu.CS         = pDebugCtx->fpu.CS;
-            pOrgCtx->fpu.Rsrvd1     = pDebugCtx->fpu.Rsrvd1;
-            pOrgCtx->fpu.FPUDP      = pDebugCtx->fpu.FPUDP;
-            pOrgCtx->fpu.DS         = pDebugCtx->fpu.DS;
-            pOrgCtx->fpu.Rsrvd2     = pDebugCtx->fpu.Rsrvd2;
-            //pOrgCtx->fpu.MXCSR_MASK = pDebugCtx->fpu.MXCSR_MASK;
-            if ((pOrgCtx->fpu.FSW & X86_FSW_TOP_MASK) == (pDebugCtx->fpu.FSW & X86_FSW_TOP_MASK))
-                pOrgCtx->fpu.FSW = pDebugCtx->fpu.FSW;
+            pOrgCtx->XState.x87.FOP        = pDebugCtx->XState.x87.FOP;
+            pOrgCtx->XState.x87.FPUIP      = pDebugCtx->XState.x87.FPUIP;
+            pOrgCtx->XState.x87.CS         = pDebugCtx->XState.x87.CS;
+            pOrgCtx->XState.x87.Rsrvd1     = pDebugCtx->XState.x87.Rsrvd1;
+            pOrgCtx->XState.x87.FPUDP      = pDebugCtx->XState.x87.FPUDP;
+            pOrgCtx->XState.x87.DS         = pDebugCtx->XState.x87.DS;
+            pOrgCtx->XState.x87.Rsrvd2     = pDebugCtx->XState.x87.Rsrvd2;
+            //pOrgCtx->XState.x87.MXCSR_MASK = pDebugCtx->XState.x87.MXCSR_MASK;
+            if ((pOrgCtx->XState.x87.FSW & X86_FSW_TOP_MASK) == (pDebugCtx->XState.x87.FSW & X86_FSW_TOP_MASK))
+                pOrgCtx->XState.x87.FSW = pDebugCtx->XState.x87.FSW;
         }
 #endif
-        if (memcmp(&pOrgCtx->fpu, &pDebugCtx->fpu, sizeof(pDebugCtx->fpu)))
+        if (memcmp(&pOrgCtx->XState.x87, &pDebugCtx->XState.x87, sizeof(pDebugCtx->XState.x87)))
         {
             RTAssertMsg2Weak("  the FPU state differs\n");
             cDiffs++;
-            CHECK_FIELD(fpu.FCW);
-            CHECK_FIELD(fpu.FSW);
-            CHECK_FIELD(fpu.FTW);
-            CHECK_FIELD(fpu.FOP);
-            CHECK_FIELD(fpu.FPUIP);
-            CHECK_FIELD(fpu.CS);
-            CHECK_FIELD(fpu.Rsrvd1);
-            CHECK_FIELD(fpu.FPUDP);
-            CHECK_FIELD(fpu.DS);
-            CHECK_FIELD(fpu.Rsrvd2);
-            CHECK_FIELD(fpu.MXCSR);
-            CHECK_FIELD(fpu.MXCSR_MASK);
-            CHECK_FIELD(fpu.aRegs[0].au64[0]); CHECK_FIELD(fpu.aRegs[0].au64[1]);
-            CHECK_FIELD(fpu.aRegs[1].au64[0]); CHECK_FIELD(fpu.aRegs[1].au64[1]);
-            CHECK_FIELD(fpu.aRegs[2].au64[0]); CHECK_FIELD(fpu.aRegs[2].au64[1]);
-            CHECK_FIELD(fpu.aRegs[3].au64[0]); CHECK_FIELD(fpu.aRegs[3].au64[1]);
-            CHECK_FIELD(fpu.aRegs[4].au64[0]); CHECK_FIELD(fpu.aRegs[4].au64[1]);
-            CHECK_FIELD(fpu.aRegs[5].au64[0]); CHECK_FIELD(fpu.aRegs[5].au64[1]);
-            CHECK_FIELD(fpu.aRegs[6].au64[0]); CHECK_FIELD(fpu.aRegs[6].au64[1]);
-            CHECK_FIELD(fpu.aRegs[7].au64[0]); CHECK_FIELD(fpu.aRegs[7].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 0].au64[0]);  CHECK_FIELD(fpu.aXMM[ 0].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 1].au64[0]);  CHECK_FIELD(fpu.aXMM[ 1].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 2].au64[0]);  CHECK_FIELD(fpu.aXMM[ 2].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 3].au64[0]);  CHECK_FIELD(fpu.aXMM[ 3].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 4].au64[0]);  CHECK_FIELD(fpu.aXMM[ 4].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 5].au64[0]);  CHECK_FIELD(fpu.aXMM[ 5].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 6].au64[0]);  CHECK_FIELD(fpu.aXMM[ 6].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 7].au64[0]);  CHECK_FIELD(fpu.aXMM[ 7].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 8].au64[0]);  CHECK_FIELD(fpu.aXMM[ 8].au64[1]);
-            CHECK_FIELD(fpu.aXMM[ 9].au64[0]);  CHECK_FIELD(fpu.aXMM[ 9].au64[1]);
-            CHECK_FIELD(fpu.aXMM[10].au64[0]);  CHECK_FIELD(fpu.aXMM[10].au64[1]);
-            CHECK_FIELD(fpu.aXMM[11].au64[0]);  CHECK_FIELD(fpu.aXMM[11].au64[1]);
-            CHECK_FIELD(fpu.aXMM[12].au64[0]);  CHECK_FIELD(fpu.aXMM[12].au64[1]);
-            CHECK_FIELD(fpu.aXMM[13].au64[0]);  CHECK_FIELD(fpu.aXMM[13].au64[1]);
-            CHECK_FIELD(fpu.aXMM[14].au64[0]);  CHECK_FIELD(fpu.aXMM[14].au64[1]);
-            CHECK_FIELD(fpu.aXMM[15].au64[0]);  CHECK_FIELD(fpu.aXMM[15].au64[1]);
-            for (unsigned i = 0; i < RT_ELEMENTS(pOrgCtx->fpu.au32RsrvdRest); i++)
-                CHECK_FIELD(fpu.au32RsrvdRest[i]);
+            CHECK_FIELD(XState.x87.FCW);
+            CHECK_FIELD(XState.x87.FSW);
+            CHECK_FIELD(XState.x87.FTW);
+            CHECK_FIELD(XState.x87.FOP);
+            CHECK_FIELD(XState.x87.FPUIP);
+            CHECK_FIELD(XState.x87.CS);
+            CHECK_FIELD(XState.x87.Rsrvd1);
+            CHECK_FIELD(XState.x87.FPUDP);
+            CHECK_FIELD(XState.x87.DS);
+            CHECK_FIELD(XState.x87.Rsrvd2);
+            CHECK_FIELD(XState.x87.MXCSR);
+            CHECK_FIELD(XState.x87.MXCSR_MASK);
+            CHECK_FIELD(XState.x87.aRegs[0].au64[0]); CHECK_FIELD(XState.x87.aRegs[0].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[1].au64[0]); CHECK_FIELD(XState.x87.aRegs[1].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[2].au64[0]); CHECK_FIELD(XState.x87.aRegs[2].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[3].au64[0]); CHECK_FIELD(XState.x87.aRegs[3].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[4].au64[0]); CHECK_FIELD(XState.x87.aRegs[4].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[5].au64[0]); CHECK_FIELD(XState.x87.aRegs[5].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[6].au64[0]); CHECK_FIELD(XState.x87.aRegs[6].au64[1]);
+            CHECK_FIELD(XState.x87.aRegs[7].au64[0]); CHECK_FIELD(XState.x87.aRegs[7].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 0].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 0].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 1].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 1].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 2].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 2].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 3].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 3].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 4].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 4].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 5].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 5].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 6].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 6].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 7].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 7].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 8].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 8].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[ 9].au64[0]);  CHECK_FIELD(XState.x87.aXMM[ 9].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[10].au64[0]);  CHECK_FIELD(XState.x87.aXMM[10].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[11].au64[0]);  CHECK_FIELD(XState.x87.aXMM[11].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[12].au64[0]);  CHECK_FIELD(XState.x87.aXMM[12].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[13].au64[0]);  CHECK_FIELD(XState.x87.aXMM[13].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[14].au64[0]);  CHECK_FIELD(XState.x87.aXMM[14].au64[1]);
+            CHECK_FIELD(XState.x87.aXMM[15].au64[0]);  CHECK_FIELD(XState.x87.aXMM[15].au64[1]);
+            for (unsigned i = 0; i < RT_ELEMENTS(pOrgCtx->XState.x87.au32RsrvdRest); i++)
+                CHECK_FIELD(XState.x87.au32RsrvdRest[i]);
         }
         CHECK_FIELD(rip);
@@ -10529,5 +10529,5 @@
               pCtx->cs.Sel, pCtx->ss.Sel, pCtx->ds.Sel, pCtx->es.Sel,
               pCtx->fs.Sel, pCtx->gs.Sel, pCtx->eflags.u,
-              pCtx->fpu.FSW, pCtx->fpu.FCW, pCtx->fpu.FTW, pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK,
+              pCtx->XState.x87.FSW, pCtx->XState.x87.FCW, pCtx->XState.x87.FTW, pCtx->XState.x87.MXCSR, pCtx->XState.x87.MXCSR_MASK,
               szInstr));
 
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h	(revision 54898)
@@ -5436,4 +5436,5 @@
     else
     {
+#ifdef IN_RING3
         CPUMCTX CtxTmp = *pCtx;
         rcStrict = CPUMSetGuestMsr(IEMCPU_TO_VMCPU(pIemCpu), pCtx->ecx, uValue.u);
@@ -5441,4 +5442,7 @@
         *pCtx = *pCtx2;
         *pCtx2 = CtxTmp;
+#else
+        AssertReleaseFailedReturn(VERR_INTERNAL_ERROR_4);
+#endif
     }
     if (rcStrict == VINF_SUCCESS)
@@ -6041,18 +6045,18 @@
     if (iemFRegIsFxSaveFormat(pIemCpu))
     {
-        pCtx->fpu.FCW   = 0x37f;
-        pCtx->fpu.FSW   = 0;
-        pCtx->fpu.FTW   = 0x00;         /* 0 - empty. */
-        pCtx->fpu.FPUDP = 0;
-        pCtx->fpu.DS    = 0; //??
-        pCtx->fpu.Rsrvd2= 0;
-        pCtx->fpu.FPUIP = 0;
-        pCtx->fpu.CS    = 0; //??
-        pCtx->fpu.Rsrvd1= 0;
-        pCtx->fpu.FOP   = 0;
+        pCtx->XState.x87.FCW   = 0x37f;
+        pCtx->XState.x87.FSW   = 0;
+        pCtx->XState.x87.FTW   = 0x00;         /* 0 - empty. */
+        pCtx->XState.x87.FPUDP = 0;
+        pCtx->XState.x87.DS    = 0; //??
+        pCtx->XState.x87.Rsrvd2= 0;
+        pCtx->XState.x87.FPUIP = 0;
+        pCtx->XState.x87.CS    = 0; //??
+        pCtx->XState.x87.Rsrvd1= 0;
+        pCtx->XState.x87.FOP   = 0;
     }
     else
     {
-        PX86FPUSTATE pFpu = (PX86FPUSTATE)&pCtx->fpu;
+        PX86FPUSTATE pFpu = (PX86FPUSTATE)&pCtx->XState.x87;
         pFpu->FCW       = 0x37f;
         pFpu->FSW       = 0;
@@ -6117,30 +6121,30 @@
 
     /* common for all formats */
-    pDst->FCW           = pCtx->fpu.FCW;
-    pDst->FSW           = pCtx->fpu.FSW;
-    pDst->FTW           = pCtx->fpu.FTW & UINT16_C(0xff);
-    pDst->FOP           = pCtx->fpu.FOP;
-    pDst->MXCSR         = pCtx->fpu.MXCSR;
-    pDst->MXCSR_MASK    = pCtx->fpu.MXCSR_MASK;
+    pDst->FCW           = pCtx->XState.x87.FCW;
+    pDst->FSW           = pCtx->XState.x87.FSW;
+    pDst->FTW           = pCtx->XState.x87.FTW & UINT16_C(0xff);
+    pDst->FOP           = pCtx->XState.x87.FOP;
+    pDst->MXCSR         = pCtx->XState.x87.MXCSR;
+    pDst->MXCSR_MASK    = pCtx->XState.x87.MXCSR_MASK;
     for (uint32_t i = 0; i < RT_ELEMENTS(pDst->aRegs); i++)
     {
         /** @todo Testcase: What actually happens to the 6 reserved bytes? I'm clearing
          *        them for now... */
-        pDst->aRegs[i].au32[0] = pCtx->fpu.aRegs[i].au32[0];
-        pDst->aRegs[i].au32[1] = pCtx->fpu.aRegs[i].au32[1];
-        pDst->aRegs[i].au32[2] = pCtx->fpu.aRegs[i].au32[2] & UINT32_C(0xffff);
+        pDst->aRegs[i].au32[0] = pCtx->XState.x87.aRegs[i].au32[0];
+        pDst->aRegs[i].au32[1] = pCtx->XState.x87.aRegs[i].au32[1];
+        pDst->aRegs[i].au32[2] = pCtx->XState.x87.aRegs[i].au32[2] & UINT32_C(0xffff);
         pDst->aRegs[i].au32[3] = 0;
     }
 
     /* FPU IP, CS, DP and DS. */
-    pDst->FPUIP  = pCtx->fpu.FPUIP;
-    pDst->CS     = pCtx->fpu.CS;
-    pDst->FPUDP  = pCtx->fpu.FPUDP;
-    pDst->DS     = pCtx->fpu.DS;
+    pDst->FPUIP  = pCtx->XState.x87.FPUIP;
+    pDst->CS     = pCtx->XState.x87.CS;
+    pDst->FPUDP  = pCtx->XState.x87.FPUDP;
+    pDst->DS     = pCtx->XState.x87.DS;
     if (enmEffOpSize == IEMMODE_64BIT)
     {
         /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
-        pDst->Rsrvd1 = pCtx->fpu.Rsrvd1;
-        pDst->Rsrvd2 = pCtx->fpu.Rsrvd2;
+        pDst->Rsrvd1 = pCtx->XState.x87.Rsrvd1;
+        pDst->Rsrvd2 = pCtx->XState.x87.Rsrvd2;
         pDst->au32RsrvdForSoftware[0] = 0;
     }
@@ -6159,5 +6163,5 @@
         uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
         for (uint32_t i = 0; i < cXmmRegs; i++)
-            pDst->aXMM[i] = pCtx->fpu.aXMM[i];
+            pDst->aXMM[i] = pCtx->XState.x87.aXMM[i];
         /** @todo Testcase: What happens to the reserved XMM registers? Untouched,
          *        right? */
@@ -6218,5 +6222,5 @@
      */
     uint32_t const fMXCSR      = pSrc->MXCSR;
-    uint32_t const fMXCSR_MASK = pCtx->fpu.MXCSR_MASK ? pCtx->fpu.MXCSR_MASK : UINT32_C(0xffbf);
+    uint32_t const fMXCSR_MASK = pCtx->XState.x87.MXCSR_MASK ? pCtx->XState.x87.MXCSR_MASK : UINT32_C(0xffbf);
     if (fMXCSR & ~fMXCSR_MASK)
     {
@@ -6232,16 +6236,16 @@
 
     /* common for all formats */
-    pCtx->fpu.FCW       = pSrc->FCW;
-    pCtx->fpu.FSW       = pSrc->FSW;
-    pCtx->fpu.FTW       = pSrc->FTW & UINT16_C(0xff);
-    pCtx->fpu.FOP       = pSrc->FOP;
-    pCtx->fpu.MXCSR     = fMXCSR;
+    pCtx->XState.x87.FCW       = pSrc->FCW;
+    pCtx->XState.x87.FSW       = pSrc->FSW;
+    pCtx->XState.x87.FTW       = pSrc->FTW & UINT16_C(0xff);
+    pCtx->XState.x87.FOP       = pSrc->FOP;
+    pCtx->XState.x87.MXCSR     = fMXCSR;
     /* (MXCSR_MASK is read-only) */
     for (uint32_t i = 0; i < RT_ELEMENTS(pSrc->aRegs); i++)
     {
-        pCtx->fpu.aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
-        pCtx->fpu.aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
-        pCtx->fpu.aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
-        pCtx->fpu.aRegs[i].au32[3] = 0;
+        pCtx->XState.x87.aRegs[i].au32[0] = pSrc->aRegs[i].au32[0];
+        pCtx->XState.x87.aRegs[i].au32[1] = pSrc->aRegs[i].au32[1];
+        pCtx->XState.x87.aRegs[i].au32[2] = pSrc->aRegs[i].au32[2] & UINT32_C(0xffff);
+        pCtx->XState.x87.aRegs[i].au32[3] = 0;
     }
 
@@ -6249,19 +6253,19 @@
     if (pIemCpu->enmCpuMode == IEMMODE_64BIT)
     {
-        pCtx->fpu.FPUIP  = pSrc->FPUIP;
-        pCtx->fpu.CS     = pSrc->CS;
-        pCtx->fpu.Rsrvd1 = pSrc->Rsrvd1;
-        pCtx->fpu.FPUDP  = pSrc->FPUDP;
-        pCtx->fpu.DS     = pSrc->DS;
-        pCtx->fpu.Rsrvd2 = pSrc->Rsrvd2;
+        pCtx->XState.x87.FPUIP  = pSrc->FPUIP;
+        pCtx->XState.x87.CS     = pSrc->CS;
+        pCtx->XState.x87.Rsrvd1 = pSrc->Rsrvd1;
+        pCtx->XState.x87.FPUDP  = pSrc->FPUDP;
+        pCtx->XState.x87.DS     = pSrc->DS;
+        pCtx->XState.x87.Rsrvd2 = pSrc->Rsrvd2;
     }
     else
     {
-        pCtx->fpu.FPUIP  = pSrc->FPUIP;
-        pCtx->fpu.CS     = pSrc->CS;
-        pCtx->fpu.Rsrvd1 = 0;
-        pCtx->fpu.FPUDP  = pSrc->FPUDP;
-        pCtx->fpu.DS     = pSrc->DS;
-        pCtx->fpu.Rsrvd2 = 0;
+        pCtx->XState.x87.FPUIP  = pSrc->FPUIP;
+        pCtx->XState.x87.CS     = pSrc->CS;
+        pCtx->XState.x87.Rsrvd1 = 0;
+        pCtx->XState.x87.FPUDP  = pSrc->FPUDP;
+        pCtx->XState.x87.DS     = pSrc->DS;
+        pCtx->XState.x87.Rsrvd2 = 0;
     }
 
@@ -6273,5 +6277,5 @@
         uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
         for (uint32_t i = 0; i < cXmmRegs; i++)
-            pCtx->fpu.aXMM[i] = pSrc->aXMM[i];
+            pCtx->XState.x87.aXMM[i] = pSrc->aXMM[i];
     }
 
@@ -6299,6 +6303,6 @@
     if (enmEffOpSize == IEMMODE_16BIT)
     {
-        uPtr.pu16[0] = pCtx->fpu.FCW;
-        uPtr.pu16[1] = pCtx->fpu.FSW;
+        uPtr.pu16[0] = pCtx->XState.x87.FCW;
+        uPtr.pu16[1] = pCtx->XState.x87.FSW;
         uPtr.pu16[2] = iemFpuCalcFullFtw(pCtx);
         if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
@@ -6309,15 +6313,15 @@
              *        effective address ((CS << 4) + IP) in the offset register and not
              *        doing any address calculations here. */
-            uPtr.pu16[3] = (uint16_t)pCtx->fpu.FPUIP;
-            uPtr.pu16[4] = ((pCtx->fpu.FPUIP >> 4) & UINT16_C(0xf000)) | pCtx->fpu.FOP;
-            uPtr.pu16[5] = (uint16_t)pCtx->fpu.FPUDP;
-            uPtr.pu16[6] = (pCtx->fpu.FPUDP  >> 4) & UINT16_C(0xf000);
+            uPtr.pu16[3] = (uint16_t)pCtx->XState.x87.FPUIP;
+            uPtr.pu16[4] = ((pCtx->XState.x87.FPUIP >> 4) & UINT16_C(0xf000)) | pCtx->XState.x87.FOP;
+            uPtr.pu16[5] = (uint16_t)pCtx->XState.x87.FPUDP;
+            uPtr.pu16[6] = (pCtx->XState.x87.FPUDP  >> 4) & UINT16_C(0xf000);
         }
         else
         {
-            uPtr.pu16[3] = pCtx->fpu.FPUIP;
-            uPtr.pu16[4] = pCtx->fpu.CS;
-            uPtr.pu16[5] = pCtx->fpu.FPUDP;
-            uPtr.pu16[6] = pCtx->fpu.DS;
+            uPtr.pu16[3] = pCtx->XState.x87.FPUIP;
+            uPtr.pu16[4] = pCtx->XState.x87.CS;
+            uPtr.pu16[5] = pCtx->XState.x87.FPUDP;
+            uPtr.pu16[6] = pCtx->XState.x87.DS;
         }
     }
@@ -6325,21 +6329,21 @@
     {
         /** @todo Testcase: what is stored in the "gray" areas? (figure 8-9 and 8-10) */
-        uPtr.pu16[0*2] = pCtx->fpu.FCW;
-        uPtr.pu16[1*2] = pCtx->fpu.FSW;
+        uPtr.pu16[0*2] = pCtx->XState.x87.FCW;
+        uPtr.pu16[1*2] = pCtx->XState.x87.FSW;
         uPtr.pu16[2*2] = iemFpuCalcFullFtw(pCtx);
         if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
         {
-            uPtr.pu16[3*2]  = (uint16_t)pCtx->fpu.FPUIP;
-            uPtr.pu32[4]    = ((pCtx->fpu.FPUIP & UINT32_C(0xffff0000)) >> 4) | pCtx->fpu.FOP;
-            uPtr.pu16[5*2]  = (uint16_t)pCtx->fpu.FPUDP;
-            uPtr.pu32[6]    = (pCtx->fpu.FPUDP  & UINT32_C(0xffff0000)) >> 4;
+            uPtr.pu16[3*2]  = (uint16_t)pCtx->XState.x87.FPUIP;
+            uPtr.pu32[4]    = ((pCtx->XState.x87.FPUIP & UINT32_C(0xffff0000)) >> 4) | pCtx->XState.x87.FOP;
+            uPtr.pu16[5*2]  = (uint16_t)pCtx->XState.x87.FPUDP;
+            uPtr.pu32[6]    = (pCtx->XState.x87.FPUDP  & UINT32_C(0xffff0000)) >> 4;
         }
         else
         {
-            uPtr.pu32[3]    = pCtx->fpu.FPUIP;
-            uPtr.pu16[4*2]  = pCtx->fpu.CS;
-            uPtr.pu16[4*2+1]= pCtx->fpu.FOP;
-            uPtr.pu32[5]    = pCtx->fpu.FPUDP;
-            uPtr.pu16[6*2]  = pCtx->fpu.DS;
+            uPtr.pu32[3]    = pCtx->XState.x87.FPUIP;
+            uPtr.pu16[4*2]  = pCtx->XState.x87.CS;
+            uPtr.pu16[4*2+1]= pCtx->XState.x87.FOP;
+            uPtr.pu32[5]    = pCtx->XState.x87.FPUDP;
+            uPtr.pu16[6*2]  = pCtx->XState.x87.DS;
         }
     }
@@ -6357,25 +6361,25 @@
     if (enmEffOpSize == IEMMODE_16BIT)
     {
-        pCtx->fpu.FCW = uPtr.pu16[0];
-        pCtx->fpu.FSW = uPtr.pu16[1];
-        pCtx->fpu.FTW = uPtr.pu16[2];
+        pCtx->XState.x87.FCW = uPtr.pu16[0];
+        pCtx->XState.x87.FSW = uPtr.pu16[1];
+        pCtx->XState.x87.FTW = uPtr.pu16[2];
         if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
         {
-            pCtx->fpu.FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
-            pCtx->fpu.FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
-            pCtx->fpu.FOP   = uPtr.pu16[4] & UINT16_C(0x07ff);
-            pCtx->fpu.CS    = 0;
-            pCtx->fpu.Rsrvd1= 0;
-            pCtx->fpu.DS    = 0;
-            pCtx->fpu.Rsrvd2= 0;
+            pCtx->XState.x87.FPUIP = uPtr.pu16[3] | ((uint32_t)(uPtr.pu16[4] & UINT16_C(0xf000)) << 4);
+            pCtx->XState.x87.FPUDP = uPtr.pu16[5] | ((uint32_t)(uPtr.pu16[6] & UINT16_C(0xf000)) << 4);
+            pCtx->XState.x87.FOP   = uPtr.pu16[4] & UINT16_C(0x07ff);
+            pCtx->XState.x87.CS    = 0;
+            pCtx->XState.x87.Rsrvd1= 0;
+            pCtx->XState.x87.DS    = 0;
+            pCtx->XState.x87.Rsrvd2= 0;
         }
         else
         {
-            pCtx->fpu.FPUIP = uPtr.pu16[3];
-            pCtx->fpu.CS    = uPtr.pu16[4];
-            pCtx->fpu.Rsrvd1= 0;
-            pCtx->fpu.FPUDP = uPtr.pu16[5];
-            pCtx->fpu.DS    = uPtr.pu16[6];
-            pCtx->fpu.Rsrvd2= 0;
+            pCtx->XState.x87.FPUIP = uPtr.pu16[3];
+            pCtx->XState.x87.CS    = uPtr.pu16[4];
+            pCtx->XState.x87.Rsrvd1= 0;
+            pCtx->XState.x87.FPUDP = uPtr.pu16[5];
+            pCtx->XState.x87.DS    = uPtr.pu16[6];
+            pCtx->XState.x87.Rsrvd2= 0;
             /** @todo Testcase: Is FOP cleared when doing 16-bit protected mode fldenv? */
         }
@@ -6383,32 +6387,32 @@
     else
     {
-        pCtx->fpu.FCW = uPtr.pu16[0*2];
-        pCtx->fpu.FSW = uPtr.pu16[1*2];
-        pCtx->fpu.FTW = uPtr.pu16[2*2];
+        pCtx->XState.x87.FCW = uPtr.pu16[0*2];
+        pCtx->XState.x87.FSW = uPtr.pu16[1*2];
+        pCtx->XState.x87.FTW = uPtr.pu16[2*2];
         if (IEM_IS_REAL_OR_V86_MODE(pIemCpu))
         {
-            pCtx->fpu.FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
-            pCtx->fpu.FOP   = uPtr.pu32[4] & UINT16_C(0x07ff);
-            pCtx->fpu.FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
-            pCtx->fpu.CS    = 0;
-            pCtx->fpu.Rsrvd1= 0;
-            pCtx->fpu.DS    = 0;
-            pCtx->fpu.Rsrvd2= 0;
+            pCtx->XState.x87.FPUIP = uPtr.pu16[3*2] | ((uPtr.pu32[4] & UINT32_C(0x0ffff000)) << 4);
+            pCtx->XState.x87.FOP   = uPtr.pu32[4] & UINT16_C(0x07ff);
+            pCtx->XState.x87.FPUDP = uPtr.pu16[5*2] | ((uPtr.pu32[6] & UINT32_C(0x0ffff000)) << 4);
+            pCtx->XState.x87.CS    = 0;
+            pCtx->XState.x87.Rsrvd1= 0;
+            pCtx->XState.x87.DS    = 0;
+            pCtx->XState.x87.Rsrvd2= 0;
         }
         else
         {
-            pCtx->fpu.FPUIP = uPtr.pu32[3];
-            pCtx->fpu.CS    = uPtr.pu16[4*2];
-            pCtx->fpu.Rsrvd1= 0;
-            pCtx->fpu.FOP   = uPtr.pu16[4*2+1];
-            pCtx->fpu.FPUDP = uPtr.pu32[5];
-            pCtx->fpu.DS    = uPtr.pu16[6*2];
-            pCtx->fpu.Rsrvd2= 0;
+            pCtx->XState.x87.FPUIP = uPtr.pu32[3];
+            pCtx->XState.x87.CS    = uPtr.pu16[4*2];
+            pCtx->XState.x87.Rsrvd1= 0;
+            pCtx->XState.x87.FOP   = uPtr.pu16[4*2+1];
+            pCtx->XState.x87.FPUDP = uPtr.pu32[5];
+            pCtx->XState.x87.DS    = uPtr.pu16[6*2];
+            pCtx->XState.x87.Rsrvd2= 0;
         }
     }
 
     /* Make adjustments. */
-    pCtx->fpu.FTW = iemFpuCompressFtw(pCtx->fpu.FTW);
-    pCtx->fpu.FCW &= ~X86_FCW_ZERO_MASK;
+    pCtx->XState.x87.FTW = iemFpuCompressFtw(pCtx->XState.x87.FTW);
+    pCtx->XState.x87.FCW &= ~X86_FCW_ZERO_MASK;
     iemFpuRecalcExceptionStatus(pCtx);
     /** @todo Testcase: Check if ES and/or B are automatically cleared if no
@@ -6462,9 +6466,9 @@
     iemCImplCommonFpuStoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
     PRTFLOAT80U paRegs = (PRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
-    for (uint32_t i = 0; i < RT_ELEMENTS(pCtx->fpu.aRegs); i++)
-    {
-        paRegs[i].au32[0] = pCtx->fpu.aRegs[i].au32[0];
-        paRegs[i].au32[1] = pCtx->fpu.aRegs[i].au32[1];
-        paRegs[i].au16[4] = pCtx->fpu.aRegs[i].au16[4];
+    for (uint32_t i = 0; i < RT_ELEMENTS(pCtx->XState.x87.aRegs); i++)
+    {
+        paRegs[i].au32[0] = pCtx->XState.x87.aRegs[i].au32[0];
+        paRegs[i].au32[1] = pCtx->XState.x87.aRegs[i].au32[1];
+        paRegs[i].au16[4] = pCtx->XState.x87.aRegs[i].au16[4];
     }
 
@@ -6474,16 +6478,16 @@
 
     /*
-     * Re-initialize the FPU.
-     */
-    pCtx->fpu.FCW   = 0x37f;
-    pCtx->fpu.FSW   = 0;
-    pCtx->fpu.FTW   = 0x00;       /* 0 - empty */
-    pCtx->fpu.FPUDP = 0;
-    pCtx->fpu.DS    = 0;
-    pCtx->fpu.Rsrvd2= 0;
-    pCtx->fpu.FPUIP = 0;
-    pCtx->fpu.CS    = 0;
-    pCtx->fpu.Rsrvd1= 0;
-    pCtx->fpu.FOP   = 0;
+     * Re-initialize the XState.x87.
+     */
+    pCtx->XState.x87.FCW   = 0x37f;
+    pCtx->XState.x87.FSW   = 0;
+    pCtx->XState.x87.FTW   = 0x00;       /* 0 - empty */
+    pCtx->XState.x87.FPUDP = 0;
+    pCtx->XState.x87.DS    = 0;
+    pCtx->XState.x87.Rsrvd2= 0;
+    pCtx->XState.x87.FPUIP = 0;
+    pCtx->XState.x87.CS    = 0;
+    pCtx->XState.x87.Rsrvd1= 0;
+    pCtx->XState.x87.FOP   = 0;
 
     iemHlpUsedFpu(pIemCpu);
@@ -6539,10 +6543,10 @@
     iemCImplCommonFpuRestoreEnv(pIemCpu, enmEffOpSize, uPtr, pCtx);
     PCRTFLOAT80U paRegs = (PCRTFLOAT80U)(uPtr.pu8 + (enmEffOpSize == IEMMODE_16BIT ? 14 : 28));
-    for (uint32_t i = 0; i < RT_ELEMENTS(pCtx->fpu.aRegs); i++)
-    {
-        pCtx->fpu.aRegs[i].au32[0] = paRegs[i].au32[0];
-        pCtx->fpu.aRegs[i].au32[1] = paRegs[i].au32[1];
-        pCtx->fpu.aRegs[i].au32[2] = paRegs[i].au16[4];
-        pCtx->fpu.aRegs[i].au32[3] = 0;
+    for (uint32_t i = 0; i < RT_ELEMENTS(pCtx->XState.x87.aRegs); i++)
+    {
+        pCtx->XState.x87.aRegs[i].au32[0] = paRegs[i].au32[0];
+        pCtx->XState.x87.aRegs[i].au32[1] = paRegs[i].au32[1];
+        pCtx->XState.x87.aRegs[i].au32[2] = paRegs[i].au16[4];
+        pCtx->XState.x87.aRegs[i].au32[3] = 0;
     }
 
@@ -6571,5 +6575,5 @@
     /** @todo Testcase: Test that it raises and loweres the FPU exception bits
      *        according to FSW. (This is was is currently implemented.) */
-    pCtx->fpu.FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
+    pCtx->XState.x87.FCW = u16Fcw & ~X86_FCW_ZERO_MASK;
     iemFpuRecalcExceptionStatus(pCtx);
 
@@ -6591,34 +6595,34 @@
     PCPUMCTX pCtx = pIemCpu->CTX_SUFF(pCtx);
 
-    unsigned const iReg1 = X86_FSW_TOP_GET(pCtx->fpu.FSW);
+    unsigned const iReg1 = X86_FSW_TOP_GET(pCtx->XState.x87.FSW);
     unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
-    Assert(!(RT_BIT(iReg1) & pCtx->fpu.FTW) || !(RT_BIT(iReg2) & pCtx->fpu.FTW));
+    Assert(!(RT_BIT(iReg1) & pCtx->XState.x87.FTW) || !(RT_BIT(iReg2) & pCtx->XState.x87.FTW));
 
     /** @todo Testcase: fxch underflow. Making assumptions that underflowed
      *        registers are read as QNaN and then exchanged. This could be
      *        wrong... */
-    if (pCtx->fpu.FCW & X86_FCW_IM)
-    {
-        if (RT_BIT(iReg1) & pCtx->fpu.FTW)
-        {
-            if (RT_BIT(iReg2) & pCtx->fpu.FTW)
-                iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
+    if (pCtx->XState.x87.FCW & X86_FCW_IM)
+    {
+        if (RT_BIT(iReg1) & pCtx->XState.x87.FTW)
+        {
+            if (RT_BIT(iReg2) & pCtx->XState.x87.FTW)
+                iemFpuStoreQNan(&pCtx->XState.x87.aRegs[0].r80);
             else
-                pCtx->fpu.aRegs[0].r80 = pCtx->fpu.aRegs[iStReg].r80;
-            iemFpuStoreQNan(&pCtx->fpu.aRegs[iStReg].r80);
+                pCtx->XState.x87.aRegs[0].r80 = pCtx->XState.x87.aRegs[iStReg].r80;
+            iemFpuStoreQNan(&pCtx->XState.x87.aRegs[iStReg].r80);
         }
         else
         {
-            pCtx->fpu.aRegs[iStReg].r80 = pCtx->fpu.aRegs[0].r80;
-            iemFpuStoreQNan(&pCtx->fpu.aRegs[0].r80);
-        }
-        pCtx->fpu.FSW &= ~X86_FSW_C_MASK;
-        pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
+            pCtx->XState.x87.aRegs[iStReg].r80 = pCtx->XState.x87.aRegs[0].r80;
+            iemFpuStoreQNan(&pCtx->XState.x87.aRegs[0].r80);
+        }
+        pCtx->XState.x87.FSW &= ~X86_FSW_C_MASK;
+        pCtx->XState.x87.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF;
     }
     else
     {
         /* raise underflow exception, don't change anything. */
-        pCtx->fpu.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
-        pCtx->fpu.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~(X86_FSW_TOP_MASK | X86_FSW_XCPT_MASK);
+        pCtx->XState.x87.FSW |= X86_FSW_C1 | X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
     }
 
@@ -6645,5 +6649,5 @@
     if (pCtx->cr0 & (X86_CR0_EM | X86_CR0_TS))
         return iemRaiseDeviceNotAvailable(pIemCpu);
-    uint16_t u16Fsw = pCtx->fpu.FSW;
+    uint16_t u16Fsw = pCtx->XState.x87.FSW;
     if (u16Fsw & X86_FSW_ES)
         return iemRaiseMathFault(pIemCpu);
@@ -6654,13 +6658,14 @@
     unsigned const iReg1 = X86_FSW_TOP_GET(u16Fsw);
     unsigned const iReg2 = (iReg1 + iStReg) & X86_FSW_TOP_SMASK;
-    if ((pCtx->fpu.FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
-    {
-        uint32_t u32Eflags = pfnAImpl(&pCtx->fpu, &u16Fsw, &pCtx->fpu.aRegs[0].r80, &pCtx->fpu.aRegs[iStReg].r80);
+    if ((pCtx->XState.x87.FTW & (RT_BIT(iReg1) | RT_BIT(iReg2))) == (RT_BIT(iReg1) | RT_BIT(iReg2)))
+    {
+        uint32_t u32Eflags = pfnAImpl(&pCtx->XState.x87, &u16Fsw,
+                                      &pCtx->XState.x87.aRegs[0].r80, &pCtx->XState.x87.aRegs[iStReg].r80);
         NOREF(u32Eflags);
 
-        pCtx->fpu.FSW &= ~X86_FSW_C1;
-        pCtx->fpu.FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C1;
+        pCtx->XState.x87.FSW |= u16Fsw & ~X86_FSW_TOP_MASK;
         if (   !(u16Fsw & X86_FSW_IE)
-            || (pCtx->fpu.FCW & X86_FCW_IM) )
+            || (pCtx->XState.x87.FCW & X86_FCW_IM) )
         {
             pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
@@ -6668,9 +6673,9 @@
         }
     }
-    else if (pCtx->fpu.FCW & X86_FCW_IM)
+    else if (pCtx->XState.x87.FCW & X86_FCW_IM)
     {
         /* Masked underflow. */
-        pCtx->fpu.FSW &= ~X86_FSW_C1;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C1;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF;
         pCtx->eflags.u &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF);
         pCtx->eflags.u |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF;
@@ -6679,6 +6684,6 @@
     {
         /* Raise underflow - don't touch EFLAGS or TOP. */
-        pCtx->fpu.FSW &= ~X86_FSW_C1;
-        pCtx->fpu.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
+        pCtx->XState.x87.FSW &= ~X86_FSW_C1;
+        pCtx->XState.x87.FSW |= X86_FSW_IE | X86_FSW_SF | X86_FSW_ES | X86_FSW_B;
         fPop = false;
     }
@@ -6689,7 +6694,7 @@
     if (fPop)
     {
-        pCtx->fpu.FTW &= ~RT_BIT(iReg1);
-        pCtx->fpu.FSW &= X86_FSW_TOP_MASK;
-        pCtx->fpu.FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
+        pCtx->XState.x87.FTW &= ~RT_BIT(iReg1);
+        pCtx->XState.x87.FSW &= X86_FSW_TOP_MASK;
+        pCtx->XState.x87.FSW |= ((iReg1 + 7) & X86_FSW_TOP_SMASK) << X86_FSW_TOP_SHIFT;
     }
 
Index: /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp	(revision 54898)
@@ -488,5 +488,5 @@
          *        We could just all this in assembly. */
         uint128_t aGuestXmmRegs[16];
-        memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
+        memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.XState.x87.aXMM[0], sizeof(aGuestXmmRegs));
 #endif
 
@@ -511,5 +511,5 @@
 
 #ifdef VBOX_WITH_KERNEL_USING_XMM
-        memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
+        memcpy(&pVCpu->cpum.s.Guest.XState.x87.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
 #endif
     }
Index: /trunk/src/VBox/VMM/VMMR0/CPUMR0A.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/CPUMR0A.asm	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMR0/CPUMR0A.asm	(revision 54898)
@@ -90,5 +90,5 @@
     ffree   st7              ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs
                              ; for the upcoming push (load)
-    fild    dword [xDX + CPUMCPU.Guest.fpu] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
+    fild    dword [xDX + CPUMCPU.Guest.XState] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
 
 .nothing_to_clean:
@@ -101,22 +101,22 @@
 ; @remarks Requires CPUMCPU pointer in RDX
 %macro SAVE_32_OR_64_FPU 0
-    o64 fxsave  [rdx + CPUMCPU.Guest.fpu]
+    o64 fxsave  [rdx + CPUMCPU.Guest.XState]
 
     ; Shouldn't be necessary to check if the entire 64-bit FIP is 0 (i.e. guest hasn't used its FPU yet) because it should
     ; be taken care of by the calling code, i.e. hmR0[Vmx|Svm]LoadSharedCR0() and hmR0[Vmx|Svm]ExitXcptNm() which ensure
     ; we swap the guest FPU state when it starts using it (#NM). In any case it's only a performance optimization.
-    ; cmp         qword [rdx + CPUMCPU.Guest.fpu + IP_OFF_IN_X86FXSTATE], 0
+    ; cmp         qword [rdx + CPUMCPU.Guest.XState + IP_OFF_IN_X86FXSTATE], 0
     ; je          short %%save_done
 
-    cmp         dword [rdx + CPUMCPU.Guest.fpu + CS_OFF_IN_X86FXSTATE], 0
+    cmp         dword [rdx + CPUMCPU.Guest.XState + CS_OFF_IN_X86FXSTATE], 0
     jne         short %%save_done
     sub         rsp, 20h                         ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0)
     fnstenv     [rsp]
     movzx       eax, word [rsp + 10h]
-    mov         [rdx + CPUMCPU.Guest.fpu + CS_OFF_IN_X86FXSTATE], eax
+    mov         [rdx + CPUMCPU.Guest.XState + CS_OFF_IN_X86FXSTATE], eax
     movzx       eax, word [rsp + 18h]
-    mov         [rdx + CPUMCPU.Guest.fpu + DS_OFF_IN_X86FXSTATE], eax
+    mov         [rdx + CPUMCPU.Guest.XState + DS_OFF_IN_X86FXSTATE], eax
     add         rsp, 20h
-    mov         dword [rdx + CPUMCPU.Guest.fpu + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
+    mov         dword [rdx + CPUMCPU.Guest.XState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
 %%save_done:
 %endmacro
@@ -127,10 +127,10 @@
 ; @remarks Requires CPUMCPU pointer in RDX
 %macro RESTORE_32_OR_64_FPU 0
-    cmp         dword [rdx + CPUMCPU.Guest.fpu + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
+    cmp         dword [rdx + CPUMCPU.Guest.XState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
     jne         short %%restore_64bit_fpu
-    fxrstor     [rdx + CPUMCPU.Guest.fpu]
+    fxrstor     [rdx + CPUMCPU.Guest.XState]
     jmp         short %%restore_fpu_done
 %%restore_64bit_fpu:
-    o64 fxrstor [rdx + CPUMCPU.Guest.fpu]
+    o64 fxrstor [rdx + CPUMCPU.Guest.XState]
 %%restore_fpu_done:
 %endmacro
@@ -201,10 +201,10 @@
 %ifdef RT_ARCH_AMD64
     ; Use explicit REX prefix. See @bugref{6398}.
-    o64 fxsave  [rdx + CPUMCPU.Host.fpu]    ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
+    o64 fxsave  [rdx + CPUMCPU.Host.XState] ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
 
     ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
     test    dword [rdx + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
     jnz     short .fpu_load_32_or_64
-    fxrstor [rdx + CPUMCPU.Guest.fpu]
+    fxrstor [rdx + CPUMCPU.Guest.XState]
     jmp     short .fpu_load_done
 .fpu_load_32_or_64:
@@ -212,11 +212,11 @@
 .fpu_load_done:
 %else
-    fxsave  [edx + CPUMCPU.Host.fpu]        ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
-    fxrstor [edx + CPUMCPU.Guest.fpu]
+    fxsave  [edx + CPUMCPU.Host.XState]     ; ASSUMES that all VT-x/AMD-V boxes sports fxsave/fxrstor (safe assumption)
+    fxrstor [edx + CPUMCPU.Guest.XState]
 %endif
 
 %ifdef VBOX_WITH_KERNEL_USING_XMM
     ; Restore the non-volatile xmm registers. ASSUMING 64-bit windows
-    lea     r11, [xDX + CPUMCPU.Host.fpu + XMM_OFF_IN_X86FXSTATE]
+    lea     r11, [xDX + CPUMCPU.Host.XState + XMM_OFF_IN_X86FXSTATE]
     movdqa  xmm6,  [r11 + 060h]
     movdqa  xmm7,  [r11 + 070h]
@@ -243,10 +243,10 @@
 .sixtyfourbit_mode:
     and     edx, 0ffffffffh
-    o64 fxsave  [rdx + CPUMCPU.Host.fpu]
+    o64 fxsave  [rdx + CPUMCPU.Host.XState]
 
     ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
     test    dword [rdx + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
     jnz     short .fpu_load_32_or_64_darwin
-    fxrstor [rdx + CPUMCPU.Guest.fpu]
+    fxrstor [rdx + CPUMCPU.Guest.XState]
     jmp     short .fpu_load_done_darwin
 .fpu_load_32_or_64_darwin:
@@ -284,5 +284,5 @@
     ; Do NOT use xCX from this point!
 
-    fxsave  [xDX + CPUMCPU.Host.fpu]    ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
+    fxsave  [xDX + CPUMCPU.Host.XState] ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
 
     ; Restore CR0 from xCX if it was saved previously.
@@ -340,5 +340,5 @@
     test    dword [rdx + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
     jnz     short .fpu_save_32_or_64
-    fxsave  [rdx + CPUMCPU.Guest.fpu]
+    fxsave  [rdx + CPUMCPU.Guest.XState]
     jmp     short .fpu_save_done
 .fpu_save_32_or_64:
@@ -347,8 +347,8 @@
 
     ; Use explicit REX prefix. See @bugref{6398}.
-    o64 fxrstor [rdx + CPUMCPU.Host.fpu]
-%else
-    fxsave  [edx + CPUMCPU.Guest.fpu]       ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
-    fxrstor [edx + CPUMCPU.Host.fpu]
+    o64 fxrstor [rdx + CPUMCPU.Host.XState]
+%else
+    fxsave  [edx + CPUMCPU.Guest.XState]    ; ASSUMES that all VT-x/AMD-V boxes support fxsave/fxrstor (safe assumption)
+    fxrstor [edx + CPUMCPU.Host.XState]
 %endif
 
@@ -371,5 +371,5 @@
     test    dword [rdx + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
     jnz     short .fpu_save_32_or_64_darwin
-    fxsave  [rdx + CPUMCPU.Guest.fpu]
+    fxsave  [rdx + CPUMCPU.Guest.XState]
     jmp     short .fpu_save_done_darwin
 .fpu_save_32_or_64_darwin:
@@ -377,5 +377,5 @@
 .fpu_save_done_darwin:
 
-    o64 fxrstor [rdx + CPUMCPU.Host.fpu]
+    o64 fxrstor [rdx + CPUMCPU.Host.XState]
     jmp far [.fpret wrt rip]
 .fpret:                                 ; 16:32 Pointer to .the_end.
@@ -425,7 +425,7 @@
 
 %ifdef RT_ARCH_AMD64
-    o64 fxrstor [xDX + CPUMCPU.Host.fpu]
-%else
-    fxrstor [xDX + CPUMCPU.Host.fpu]
+    o64 fxrstor [xDX + CPUMCPU.Host.XState]
+%else
+    fxrstor [xDX + CPUMCPU.Host.XState]
 %endif
 
@@ -444,5 +444,5 @@
 .sixtyfourbit_mode:
     and     edx, 0ffffffffh
-    o64 fxrstor [rdx + CPUMCPU.Host.fpu]
+    o64 fxrstor [rdx + CPUMCPU.Host.XState]
     jmp far [.fpret wrt rip]
 .fpret:                                 ; 16:32 Pointer to .the_end.
Index: /trunk/src/VBox/VMM/VMMR0/HMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 54898)
@@ -1976,8 +1976,8 @@
         "FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
         ,
-        pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
-        pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
-        pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
-        pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
+        pCtx->XState.x87.FCW, pCtx->XState.x87.FSW, pCtx->XState.x87.FTW,
+        pCtx->XState.x87.FOP, pCtx->XState.x87.FPUIP, pCtx->XState.x87.CS, pCtx->XState.x87.Rsrvd1,
+        pCtx->XState.x87.FPUDP, pCtx->XState.x87.DS, pCtx->XState.x87.Rsrvd2,
+        pCtx->XState.x87.MXCSR, pCtx->XState.x87.MXCSR_MASK));
 
     Log(("MSR:\n"
Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 54898)
@@ -114,40 +114,40 @@
 static const SSMFIELD g_aCpumCtxFields[] =
 {
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FCW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FSW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FTW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FOP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FPUIP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.CS),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.Rsrvd1),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FPUDP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.DS),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.Rsrvd2),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.MXCSR),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.MXCSR_MASK),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[0]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[1]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[2]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[3]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[4]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[5]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[6]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[7]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[0]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[1]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[2]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[3]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[4]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[5]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[6]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[7]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[8]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[9]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[10]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[11]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[12]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[13]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[14]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[15]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FCW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FSW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FTW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FOP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FPUIP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.CS),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.Rsrvd1),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FPUDP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.DS),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.Rsrvd2),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.MXCSR),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.MXCSR_MASK),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[0]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[1]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[2]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[3]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[4]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[5]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[6]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[7]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[0]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[1]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[2]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[3]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[4]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[5]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[6]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[7]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[8]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[9]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[10]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[11]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[12]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[13]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[14]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[15]),
     SSMFIELD_ENTRY(         CPUMCTX, rdi),
     SSMFIELD_ENTRY(         CPUMCTX, rsi),
@@ -248,41 +248,41 @@
 static const SSMFIELD g_aCpumCtxFieldsMem[] =
 {
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FCW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FSW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FTW),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FOP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FPUIP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.CS),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.Rsrvd1),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.FPUDP),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.DS),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.Rsrvd2),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.MXCSR),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.MXCSR_MASK),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[0]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[1]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[2]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[3]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[4]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[5]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[6]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aRegs[7]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[0]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[1]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[2]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[3]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[4]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[5]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[6]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[7]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[8]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[9]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[10]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[11]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[12]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[13]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[14]),
-    SSMFIELD_ENTRY(         CPUMCTX, fpu.aXMM[15]),
-    SSMFIELD_ENTRY_IGNORE(  CPUMCTX, fpu.au32RsrvdRest),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FCW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FSW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FTW),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FOP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FPUIP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.CS),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.Rsrvd1),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.FPUDP),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.DS),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.Rsrvd2),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.MXCSR),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.MXCSR_MASK),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[0]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[1]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[2]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[3]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[4]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[5]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[6]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aRegs[7]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[0]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[1]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[2]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[3]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[4]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[5]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[6]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[7]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[8]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[9]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[10]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[11]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[12]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[13]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[14]),
+    SSMFIELD_ENTRY(         CPUMCTX, XState.x87.aXMM[15]),
+    SSMFIELD_ENTRY_IGNORE(  CPUMCTX, XState.x87.au32RsrvdRest),
     SSMFIELD_ENTRY(         CPUMCTX, rdi),
     SSMFIELD_ENTRY(         CPUMCTX, rsi),
@@ -378,41 +378,41 @@
 static const SSMFIELD g_aCpumCtxFieldsV16[] =
 {
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FCW),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FSW),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FTW),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FOP),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FPUIP),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.CS),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.Rsrvd1),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.FPUDP),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.DS),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.Rsrvd2),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.MXCSR),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.MXCSR_MASK),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[0]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[1]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[2]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[3]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[4]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[5]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[6]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aRegs[7]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[0]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[1]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[2]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[3]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[4]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[5]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[6]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[7]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[8]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[9]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[10]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[11]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[12]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[13]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[14]),
-    SSMFIELD_ENTRY(             CPUMCTX, fpu.aXMM[15]),
-    SSMFIELD_ENTRY_IGNORE(      CPUMCTX, fpu.au32RsrvdRest),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FCW),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FSW),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FTW),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FOP),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FPUIP),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.CS),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.Rsrvd1),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.FPUDP),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.DS),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.Rsrvd2),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.MXCSR),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.MXCSR_MASK),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[0]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[1]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[2]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[3]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[4]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[5]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[6]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aRegs[7]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[0]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[1]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[2]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[3]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[4]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[5]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[6]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[7]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[8]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[9]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[10]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[11]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[12]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[13]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[14]),
+    SSMFIELD_ENTRY(             CPUMCTX, XState.x87.aXMM[15]),
+    SSMFIELD_ENTRY_IGNORE(      CPUMCTX, XState.x87.au32RsrvdRest),
     SSMFIELD_ENTRY(             CPUMCTX, rdi),
     SSMFIELD_ENTRY(             CPUMCTX, rsi),
@@ -842,11 +842,11 @@
     pCtx->dr[7]                     = X86_DR7_INIT_VAL;
 
-    pCtx->fpu.FTW                   = 0x00;         /* All empty (abbridged tag reg edition). */
-    pCtx->fpu.FCW                   = 0x37f;
+    pCtx->XState.x87.FTW            = 0x00;         /* All empty (abbridged tag reg edition). */
+    pCtx->XState.x87.FCW            = 0x37f;
 
     /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
        IA-32 Processor States Following Power-up, Reset, or INIT */
-    pCtx->fpu.MXCSR                 = 0x1F80;
-    pCtx->fpu.MXCSR_MASK            = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
+    pCtx->XState.x87.MXCSR          = 0x1F80;
+    pCtx->XState.x87.MXCSR_MASK     = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
                                                         supports all bits, since a zero value here should be read as 0xffbf. */
 
@@ -1521,31 +1521,31 @@
                 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x  %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
                 ,
-                pszPrefix, pCtx->fpu.FCW,   pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
-                pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
-                pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS,  pszPrefix, pCtx->fpu.Rsrvd1,
-                pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS,  pszPrefix, pCtx->fpu.Rsrvd2
+                pszPrefix, pCtx->XState.x87.FCW,   pszPrefix, pCtx->XState.x87.FSW, pszPrefix, pCtx->XState.x87.FTW, pszPrefix, pCtx->XState.x87.FOP,
+                pszPrefix, pCtx->XState.x87.MXCSR, pszPrefix, pCtx->XState.x87.MXCSR_MASK,
+                pszPrefix, pCtx->XState.x87.FPUIP, pszPrefix, pCtx->XState.x87.CS,  pszPrefix, pCtx->XState.x87.Rsrvd1,
+                pszPrefix, pCtx->XState.x87.FPUDP, pszPrefix, pCtx->XState.x87.DS,  pszPrefix, pCtx->XState.x87.Rsrvd2
                 );
-            unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
-            for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
+            unsigned iShift = (pCtx->XState.x87.FSW >> 11) & 7;
+            for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->XState.x87.aRegs); iST++)
             {
-                unsigned iFPR        = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
-                unsigned uTag        = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
-                char     chSign      = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
-                unsigned iInteger    = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
-                uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
-                unsigned uExponent   = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
+                unsigned iFPR        = (iST + iShift) % RT_ELEMENTS(pCtx->XState.x87.aRegs);
+                unsigned uTag        = pCtx->XState.x87.FTW & (1 << iFPR) ? 1 : 0;
+                char     chSign      = pCtx->XState.x87.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
+                unsigned iInteger    = (unsigned)(pCtx->XState.x87.aRegs[0].au64[0] >> 63);
+                uint64_t u64Fraction = pCtx->XState.x87.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
+                unsigned uExponent   = pCtx->XState.x87.aRegs[0].au16[4] & 0x7fff;
                 /** @todo This isn't entirenly correct and needs more work! */
                 pHlp->pfnPrintf(pHlp,
                                 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
                                 pszPrefix, iST, pszPrefix, iFPR,
-                                pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
+                                pCtx->XState.x87.aRegs[0].au16[4], pCtx->XState.x87.aRegs[0].au32[1], pCtx->XState.x87.aRegs[0].au32[0],
                                 uTag, chSign, iInteger, u64Fraction, uExponent);
-                if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
+                if (pCtx->XState.x87.aRegs[0].au16[5] || pCtx->XState.x87.aRegs[0].au16[6] || pCtx->XState.x87.aRegs[0].au16[7])
                     pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
-                                    pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
+                                    pCtx->XState.x87.aRegs[0].au16[5], pCtx->XState.x87.aRegs[0].au16[6], pCtx->XState.x87.aRegs[0].au16[7]);
                 else
                     pHlp->pfnPrintf(pHlp, "\n");
             }
-            for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
+            for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->XState.x87.aXMM); iXMM++)
                 pHlp->pfnPrintf(pHlp,
                                 iXMM & 1
@@ -1553,12 +1553,12 @@
                                 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32  ",
                                 pszPrefix, iXMM, iXMM < 10 ? " " : "",
-                                pCtx->fpu.aXMM[iXMM].au32[3],
-                                pCtx->fpu.aXMM[iXMM].au32[2],
-                                pCtx->fpu.aXMM[iXMM].au32[1],
-                                pCtx->fpu.aXMM[iXMM].au32[0]);
-            for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
-                if (pCtx->fpu.au32RsrvdRest[i])
+                                pCtx->XState.x87.aXMM[iXMM].au32[3],
+                                pCtx->XState.x87.aXMM[iXMM].au32[2],
+                                pCtx->XState.x87.aXMM[iXMM].au32[1],
+                                pCtx->XState.x87.aXMM[iXMM].au32[0]);
+            for (unsigned i = 0; i < RT_ELEMENTS(pCtx->XState.x87.au32RsrvdRest); i++)
+                if (pCtx->XState.x87.au32RsrvdRest[i])
                     pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
-                                    pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
+                                    pszPrefix, i, pCtx->XState.x87.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
 
             pHlp->pfnPrintf(pHlp,
Index: /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp	(revision 54898)
@@ -513,12 +513,12 @@
     if (cpumR3RegIsFxSaveFormat(pVCpu))
     {
-        unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
+        unsigned iReg = (pVCpu->cpum.s.Guest.XState.x87.FSW >> 11) & 7;
         iReg += pDesc->offRegister;
         iReg &= 7;
-        pValue->r80Ex = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80Ex;
+        pValue->r80Ex = pVCpu->cpum.s.Guest.XState.x87.aRegs[iReg].r80Ex;
     }
     else
     {
-        PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
+        PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.XState.x87;
 
         unsigned iReg = (pOldFpu->FSW >> 11) & 7;
@@ -677,12 +677,12 @@
     if (cpumR3RegIsFxSaveFormat(pVCpu))
     {
-        unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
+        unsigned iReg = (pVCpu->cpum.s.Guest.XState.x87.FSW >> 11) & 7;
         iReg += pDesc->offRegister;
         iReg &= 7;
-        pValue->r80Ex = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80Ex;
+        pValue->r80Ex = pVCpu->cpum.s.Guest.XState.x87.aRegs[iReg].r80Ex;
     }
     else
     {
-        PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
+        PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.XState.x87;
 
         unsigned iReg = (pOldFpu->FSW >> 11) & 7;
@@ -1079,8 +1079,8 @@
 
 #define CPU_REG_MM(n) \
-    CPU_REG_RW_AS("mm" #n,          MM##n,          U64, fpu.aRegs[n].mmx,      cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_mmN)
+    CPU_REG_RW_AS("mm" #n,          MM##n,          U64, XState.x87.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_mmN)
 
 #define CPU_REG_XMM(n) \
-    CPU_REG_RW_AS("xmm" #n,         XMM##n,         U128, fpu.aXMM[n].xmm,      cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_xmmN)
+    CPU_REG_RW_AS("xmm" #n,         XMM##n,         U128, XState.x87.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL,                       g_aCpumRegFields_xmmN)
 /** @} */
 
@@ -1124,14 +1124,14 @@
     CPU_REG_REG(RIP, rip),
     CPU_REG_RW_AS("rflags",         RFLAGS,         U64, rflags,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_rflags,   g_aCpumRegFields_rflags ),
-    CPU_REG_RW_AS("fcw",            FCW,            U16, fpu.FCW,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fcw    ),
-    CPU_REG_RW_AS("fsw",            FSW,            U16, fpu.FSW,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fsw    ),
-    CPU_REG_RO_AS("ftw",            FTW,            U16, fpu,                   cpumR3RegGet_ftw,       cpumR3RegSet_ftw,       NULL,                       g_aCpumRegFields_ftw    ),
-    CPU_REG_RW_AS("fop",            FOP,            U16, fpu.FOP,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("fpuip",          FPUIP,          U32, fpu.FPUIP,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpuip,    NULL                    ),
-    CPU_REG_RW_AS("fpucs",          FPUCS,          U16, fpu.CS,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("fpudp",          FPUDP,          U32, fpu.FPUDP,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpudp,    NULL                    ),
-    CPU_REG_RW_AS("fpuds",          FPUDS,          U16, fpu.DS,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("mxcsr",          MXCSR,          U32, fpu.MXCSR,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
-    CPU_REG_RW_AS("mxcsr_mask",     MXCSR_MASK,     U32, fpu.MXCSR_MASK,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
+    CPU_REG_RW_AS("fcw",            FCW,            U16, XState.x87.FCW,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fcw    ),
+    CPU_REG_RW_AS("fsw",            FSW,            U16, XState.x87.FSW,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fsw    ),
+    CPU_REG_RO_AS("ftw",            FTW,            U16, XState.x87,            cpumR3RegGet_ftw,       cpumR3RegSet_ftw,       NULL,                       g_aCpumRegFields_ftw    ),
+    CPU_REG_RW_AS("fop",            FOP,            U16, XState.x87.FOP,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("fpuip",          FPUIP,          U32, XState.x87.FPUIP,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpuip,    NULL                    ),
+    CPU_REG_RW_AS("fpucs",          FPUCS,          U16, XState.x87.CS,         cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("fpudp",          FPUDP,          U32, XState.x87.FPUDP,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpudp,    NULL                    ),
+    CPU_REG_RW_AS("fpuds",          FPUDS,          U16, XState.x87.DS,         cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("mxcsr",          MXCSR,          U32, XState.x87.MXCSR,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
+    CPU_REG_RW_AS("mxcsr_mask",     MXCSR_MASK,     U32, XState.x87.MXCSR_MASK, cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
     CPU_REG_ST(0),
     CPU_REG_ST(1),
@@ -1252,14 +1252,14 @@
     CPU_REG_REG(RIP, rip),
     CPU_REG_RW_AS("rflags",         RFLAGS,         U64, rflags,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_rflags,   g_aCpumRegFields_rflags ),
-    CPU_REG_RW_AS("fcw",            FCW,            U16, fpu.FCW,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fcw    ),
-    CPU_REG_RW_AS("fsw",            FSW,            U16, fpu.FSW,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fsw    ),
-    CPU_REG_RO_AS("ftw",            FTW,            U16, fpu,                   cpumR3RegGet_ftw,       cpumR3RegSet_ftw,       NULL,                       g_aCpumRegFields_ftw    ),
-    CPU_REG_RW_AS("fop",            FOP,            U16, fpu.FOP,               cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("fpuip",          FPUIP,          U32, fpu.FPUIP,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpuip,    NULL                    ),
-    CPU_REG_RW_AS("fpucs",          FPUCS,          U16, fpu.CS,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("fpudp",          FPUDP,          U32, fpu.FPUDP,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpudp,    NULL                    ),
-    CPU_REG_RW_AS("fpuds",          FPUDS,          U16, fpu.DS,                cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
-    CPU_REG_RW_AS("mxcsr",          MXCSR,          U32, fpu.MXCSR,             cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
-    CPU_REG_RW_AS("mxcsr_mask",     MXCSR_MASK,     U32, fpu.MXCSR_MASK,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
+    CPU_REG_RW_AS("fcw",            FCW,            U16, XState.x87.FCW,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fcw    ),
+    CPU_REG_RW_AS("fsw",            FSW,            U16, XState.x87.FSW,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_fsw    ),
+    CPU_REG_RO_AS("ftw",            FTW,            U16, XState.x87,            cpumR3RegGet_ftw,       cpumR3RegSet_ftw,       NULL,                       g_aCpumRegFields_ftw    ),
+    CPU_REG_RW_AS("fop",            FOP,            U16, XState.x87.FOP,        cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("fpuip",          FPUIP,          U32, XState.x87.FPUIP,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpuip,    NULL                    ),
+    CPU_REG_RW_AS("fpucs",          FPUCS,          U16, XState.x87.CS,         cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("fpudp",          FPUDP,          U32, XState.x87.FPUDP,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   g_aCpumRegAliases_fpudp,    NULL                    ),
+    CPU_REG_RW_AS("fpuds",          FPUDS,          U16, XState.x87.DS,         cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       NULL                    ),
+    CPU_REG_RW_AS("mxcsr",          MXCSR,          U32, XState.x87.MXCSR,      cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
+    CPU_REG_RW_AS("mxcsr_mask",     MXCSR_MASK,     U32, XState.x87.MXCSR_MASK, cpumR3RegGet_Generic,   cpumR3RegSet_Generic,   NULL,                       g_aCpumRegFields_mxcsr  ),
     CPU_REG_ST(0),
     CPU_REG_ST(1),
Index: /trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm
===================================================================
--- /trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMRC/CPUMRCA.asm	(revision 54898)
@@ -65,5 +65,5 @@
     ffree   st7              ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs
                              ; for the upcoming push (load)
-    fild    dword [xDX + CPUMCPU.Guest.fpu] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
+    fild    dword [xDX + CPUMCPU.Guest.XState] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
 
 .nothing_to_clean:
@@ -197,10 +197,10 @@
 %ifdef RT_ARCH_AMD64
     ; Use explicit REX prefix. See @bugref{6398}.
-    o64 fxsave  [xDX + CPUMCPU.Host.fpu]
+    o64 fxsave  [xDX + CPUMCPU.Host.XState]
 %else
-    fxsave  [xDX + CPUMCPU.Host.fpu]
+    fxsave  [xDX + CPUMCPU.Host.XState]
 %endif
     or      dword [xDX + CPUMCPU.fUseFlags], (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)
-    fxrstor [xDX + CPUMCPU.Guest.fpu]           ; raw-mode guest is always 32-bit. See @bugref{7138}.
+    fxrstor [xDX + CPUMCPU.Guest.XState]        ; raw-mode guest is always 32-bit. See @bugref{7138}.
 
 hlfpua_finished_switch:
@@ -217,15 +217,15 @@
 ; legacy support.
 hlfpua_no_fxsave:
-    fnsave  [xDX + CPUMCPU.Host.fpu]
+    fnsave  [xDX + CPUMCPU.Host.XState]
     or      dword [xDX + CPUMCPU.fUseFlags], dword (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM) ; yasm / nasm
-    mov     eax, [xDX + CPUMCPU.Guest.fpu]      ; control word
+    mov     eax, [xDX + CPUMCPU.Guest.XState]   ; control word
     not     eax                                 ; 1 means exception ignored (6 LS bits)
     and     eax, byte 03Fh                      ; 6 LS bits only
-    test    eax, [xDX + CPUMCPU.Guest.fpu + 4]  ; status word
+    test    eax, [xDX + CPUMCPU.Guest.XState + 4] ; status word
     jz short hlfpua_no_exceptions_pending
     ; technically incorrect, but we certainly don't want any exceptions now!!
-    and     dword [xDX + CPUMCPU.Guest.fpu + 4], ~03Fh
+    and     dword [xDX + CPUMCPU.Guest.XState + 4], ~03Fh
 hlfpua_no_exceptions_pending:
-    frstor  [xDX + CPUMCPU.Guest.fpu]
+    frstor  [xDX + CPUMCPU.Guest.XState]
     jmp near hlfpua_finished_switch
 %endif ; !RT_ARCH_AMD64
Index: /trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac
===================================================================
--- /trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMSwitcher/AMD64andLegacy.mac	(revision 54898)
@@ -1144,6 +1144,6 @@
     mov     cr0, rcx
 
-    fxsave  [rdx + r8 + CPUMCPU.Guest.fpu]
-    o64 fxrstor [rdx + r8 + CPUMCPU.Host.fpu]       ; Restore 64-bit host FPU state. See @bugref{7138}
+    fxsave  [rdx + r8 + CPUMCPU.Guest.XState]
+    o64 fxrstor [rdx + r8 + CPUMCPU.Host.XState]    ; Restore 64-bit host FPU state. See @bugref{7138}
     jmp short gth_fpu_no
 
Index: /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac
===================================================================
--- /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMSwitcher/LegacyandAMD64.mac	(revision 54898)
@@ -665,5 +665,5 @@
     mov     cr0, rax
     ; Use explicit REX prefix. See @bugref{6398}.
-    o64 fxrstor [rdx + CPUMCPU.Guest.fpu]
+    o64 fxrstor [rdx + CPUMCPU.Guest.XState]
     mov     cr0, rcx                    ; and restore old CR0 again
 
@@ -725,5 +725,5 @@
     ; parameter for all helper functions (pCtx)
     DEBUG64_CHAR('9')
-    lea     rsi, [rdx + CPUMCPU.Guest.fpu]
+    lea     rsi, [rdx + CPUMCPU.Guest.XState]
     lea     rax, [htg_return wrt rip]
     push    rax                         ; return address
@@ -1259,5 +1259,5 @@
 
     ; Use explicit REX prefix. See @bugref{6398}.
-    o64 fxsave  [rsi + CPUMCTX.fpu]
+    o64 fxsave  [rsi + CPUMCTX.XState]
 
     mov     cr0, rcx                    ; and restore old CR0 again
Index: /trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac
===================================================================
--- /trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac	(revision 54897)
+++ /trunk/src/VBox/VMM/VMMSwitcher/PAEand32Bit.mac	(revision 54898)
@@ -991,21 +991,21 @@
 
     FIXUP FIX_NO_FXSAVE_JMP, 0, gth_no_fxsave - NAME(Start) ; this will insert a jmp gth_no_fxsave if fxsave isn't supported.
-    fxsave  [edx + CPUMCPU.Guest.fpu]
-    fxrstor [edx + CPUMCPU.Host.fpu]
+    fxsave  [edx + CPUMCPU.Guest.XState]
+    fxrstor [edx + CPUMCPU.Host.XState]
     jmp near gth_fpu_no
 
 gth_no_fxsave:
-    fnsave  [edx + CPUMCPU.Guest.fpu]
-    mov     eax, [edx + CPUMCPU.Host.fpu]     ; control word
+    fnsave  [edx + CPUMCPU.Guest.XState]
+    mov     eax, [edx + CPUMCPU.Host.XState] ; control word
     not     eax                            ; 1 means exception ignored (6 LS bits)
     and     eax, byte 03Fh                 ; 6 LS bits only
-    test    eax, [edx + CPUMCPU.Host.fpu + 4] ; status word
+    test    eax, [edx + CPUMCPU.Host.XState + 4] ; status word
     jz      gth_no_exceptions_pending
 
     ; technically incorrect, but we certainly don't want any exceptions now!!
-    and     dword [edx + CPUMCPU.Host.fpu + 4], ~03Fh
+    and     dword [edx + CPUMCPU.Host.XState + 4], ~03Fh
 
 gth_no_exceptions_pending:
-    frstor  [edx + CPUMCPU.Host.fpu]
+    frstor  [edx + CPUMCPU.Host.XState]
     jmp short gth_fpu_no
 
Index: /trunk/src/VBox/VMM/include/CPUMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/CPUMInternal.h	(revision 54897)
+++ /trunk/src/VBox/VMM/include/CPUMInternal.h	(revision 54898)
@@ -288,5 +288,5 @@
     /** FPU state. (16-byte alignment)
      * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
-    X86FXSTATE      fpu;
+    X86XSAVEAREA    XState;
 
     /** General purpose register, selectors, flags and more
Index: /trunk/src/VBox/VMM/include/CPUMInternal.mac
===================================================================
--- /trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 54897)
+++ /trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 54898)
@@ -17,4 +17,5 @@
 
 %include "VBox/asmdefs.mac"
+%include "VBox/vmm/cpum.mac"
 
 ;;
@@ -64,5 +65,4 @@
 %define VMMGCRET_USED_FPU               040000000h
 
-%define FPUSTATE_SIZE                   512
 
 ;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) in
@@ -127,5 +127,5 @@
     ;
     alignb 64
-    .Guest.fpu                resb    512
+    .Guest.XState             resb    XSTATE_SIZE
     .Guest.eax                resq    1
     .Guest.ecx                resq    1
@@ -256,5 +256,5 @@
     ;
     alignb 64
-    .Host.fpu            resb    FPUSTATE_SIZE
+    .Host.XState         resb    XSTATE_SIZE
 
 %if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBRID_32BIT_KERNEL
@@ -368,5 +368,5 @@
     ;
     alignb 64
-    .Hyper.fpu                resb    512
+    .Hyper.XState             resb    XSTATE_SIZE
     .Hyper.eax                resq    1
     .Hyper.ecx                resq    1
Index: /trunk/src/VBox/VMM/testcase/tstVMStruct.h
===================================================================
--- /trunk/src/VBox/VMM/testcase/tstVMStruct.h	(revision 54897)
+++ /trunk/src/VBox/VMM/testcase/tstVMStruct.h	(revision 54898)
@@ -63,5 +63,5 @@
 
     GEN_CHECK_SIZE(CPUMHOSTCTX);
-    GEN_CHECK_OFF(CPUMHOSTCTX, fpu);
+    GEN_CHECK_OFF(CPUMHOSTCTX, XState);
 #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
     GEN_CHECK_OFF(CPUMHOSTCTX, rbx);
@@ -132,5 +132,5 @@
 
     GEN_CHECK_SIZE(CPUMCTX);
-    GEN_CHECK_OFF(CPUMCTX, fpu);
+    GEN_CHECK_OFF(CPUMCTX, XState);
     GEN_CHECK_OFF(CPUMCTX, rdi);
     GEN_CHECK_OFF(CPUMCTX, rsi);
Index: /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
===================================================================
--- /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 54897)
+++ /trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp	(revision 54898)
@@ -298,5 +298,5 @@
 
     /* cpumctx */
-    CHECK_MEMBER_ALIGNMENT(CPUMCTX, fpu, 32);
+    CHECK_MEMBER_ALIGNMENT(CPUMCTX, XState, 64);
     CHECK_MEMBER_ALIGNMENT(CPUMCTX, rax, 32);
     CHECK_MEMBER_ALIGNMENT(CPUMCTX, idtr.pIdt, 8);
Index: /trunk/src/recompiler/VBoxRecompiler.c
===================================================================
--- /trunk/src/recompiler/VBoxRecompiler.c	(revision 54897)
+++ /trunk/src/recompiler/VBoxRecompiler.c	(revision 54898)
@@ -2352,5 +2352,5 @@
         /* Sync FPU state after CR4, CPUID and EFER (!). */
         if (fFlags & CPUM_CHANGED_FPU_REM)
-            save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu); /* 'save' is an excellent name. */
+            save_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->XState.x87); /* 'save' is an excellent name. */
     }
 
@@ -2545,5 +2545,5 @@
 
     /** @todo check if FPU/XMM was actually used in the recompiler */
-    restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
+    restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->XState.x87);
 ////    dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
 
@@ -2816,9 +2816,9 @@
     /** @todo DS */
     /** @todo Fix MXCSR support in QEMU so we don't overwrite MXCSR with 0 when we shouldn't! */
-    pCtx->fpu.MXCSR         = 0;
-    pCtx->fpu.MXCSR_MASK    = 0;
+    pCtx->XState.x87.MXCSR       = 0;
+    pCtx->XState.x87.MXCSR_MASK  = 0;
 
     /** @todo check if FPU/XMM was actually used in the recompiler */
-    restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->fpu);
+    restore_raw_fp_state(&pVM->rem.s.Env, (uint8_t *)&pCtx->XState.x87);
 ////    dprintf2(("FPU state CW=%04X TT=%04X SW=%04X (%04X)\n", env->fpuc, env->fpstt, env->fpus, pVMCtx->fpu.FSW));
 
