Changeset 55316 in vbox

Timestamp:

Apr 16, 2015 5:34:30 PM (10 years ago)

Author:

vboxsync

Message:

CPUM,IEM,HM: Enabled XSAVE and AVX for AMD-V too.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAll.cpp (modified) (1 diff)
• VMMR0/HMSVMR0.cpp (modified) (7 diffs)
• VMMR0/HMVMXR0.cpp (modified) (6 diffs)
• VMMR3/CPUMR3CpuId.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -9222 +9222 @@
     do \
     { \
-        if (RT_LIKELY((pIemCpu->fPrefixes & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
+        if (RT_LIKELY(!(pIemCpu->fPrefixes & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPNZ | IEM_OP_PRF_REPZ)))) \
         { /* likely */ } \
         else \

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -23 +23 @@
 #include <iprt/thread.h>
 
+#include <VBox/vmm/pdmapi.h>
+#include <VBox/vmm/dbgf.h>
+#include <VBox/vmm/iem.h>
+#include <VBox/vmm/iom.h>
+#include <VBox/vmm/tm.h>
+#include <VBox/vmm/gim.h>
 #include "HMInternal.h"
 #include <VBox/vmm/vm.h>
 #include "HMSVMR0.h"
-#include <VBox/vmm/pdmapi.h>
-#include <VBox/vmm/dbgf.h>
-#include <VBox/vmm/iom.h>
-#include <VBox/vmm/tm.h>
-#include <VBox/vmm/gim.h>
 #include "dtrace/VBoxVMM.h"
 
@@ -288 +289 @@
 static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
 static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
+static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
 static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
 static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
@@ -724 +726 @@
                                         | SVM_CTRL2_INTERCEPT_WBINVD        /* WBINVD causes a #VMEXIT. */
                                         | SVM_CTRL2_INTERCEPT_MONITOR       /* MONITOR causes a #VMEXIT. */
-                                        | SVM_CTRL2_INTERCEPT_MWAIT;        /* MWAIT causes a #VMEXIT. */
+                                        | SVM_CTRL2_INTERCEPT_MWAIT         /* MWAIT causes a #VMEXIT. */
+                                        | SVM_CTRL2_INTERCEPT_XSETBV;       /* XSETBV causes a #VMEXIT. */
 
         /* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
@@ -1249 +1252 @@
     /*
      * Guest CR4.
+     * ASSUMES this is done everytime we get in from ring-3! (XCR0)
      */
     if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
@@ -1289 +1293 @@
         pVmcb->guest.u64CR4 = u64GuestCR4;
         pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
+
+        /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
+        pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
+
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
     }
@@ -3582 +3590 @@
                 case SVM_EXIT_WRITE_DR14:   case SVM_EXIT_WRITE_DR15:
                     return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
+
+                case SVM_EXIT_XSETBV:
+                    return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
 
                 case SVM_EXIT_TASK_SWITCH:
@@ -4711 +4722 @@
 
 /**
+ * #VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional #VMEXIT.
+ */
+HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
+{
+    HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
+
+    /** @todo decode assists... */
+    VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
+    if (rcStrict == VINF_IEM_RAISED_XCPT)
+        HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
+
+    pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
+
+    HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
+    return VBOXSTRICTRC_TODO(rcStrict);
+}
+
+
+/**
  * #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
  */

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -24 +24 @@
 #include <iprt/thread.h>
 
-#include "HMInternal.h"
-#include <VBox/vmm/vm.h>
-#include "HMVMXR0.h"
 #include <VBox/vmm/pdmapi.h>
 #include <VBox/vmm/dbgf.h>
@@ -37 +34 @@
 # include <VBox/vmm/rem.h>
 #endif
-# include "dtrace/VBoxVMM.h"
+#include "HMInternal.h"
+#include <VBox/vmm/vm.h>
+#include "HMVMXR0.h"
+#include "dtrace/VBoxVMM.h"
 
 #ifdef DEBUG_ramshankar
@@ -4018 +4018 @@
     /*
      * Guest CR4.
+     * ASSUMES this is done everytime we get in from ring-3! (XCR0)
      */
     if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
@@ -4100 +4101 @@
 
         /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM-exit. */
-        uint32_t u32CR4Mask = 0;
-        u32CR4Mask =  X86_CR4_VME
-                    | X86_CR4_PAE
-                    | X86_CR4_PGE
-                    | X86_CR4_PSE
-                    | X86_CR4_VMXE;
+        uint32_t u32CR4Mask = X86_CR4_VME
+                            | X86_CR4_PAE
+                            | X86_CR4_PGE
+                            | X86_CR4_PSE
+                            | X86_CR4_VMXE;
+        if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
+            u32CR4Mask |= X86_CR4_OSXSAVE;
         pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
         rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
         AssertRCReturn(rc, rc);
+
+        /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
+        pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
 
         HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
@@ -10649 +10654 @@
     pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
 
-    return VBOXSTRICTRC_VAL(rcStrict);
+    return VBOXSTRICTRC_TODO(rcStrict);
 }
 
@@ -11049 +11054 @@
                     break;
                 case 4: /* CR4 */
-                    pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
                     HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
                     Log4(("CRX CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n",

trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

@@ -3643 +3643 @@
     AssertLogRelRCReturn(rc, rc);
 
-#if 1 /* Incomplete, so not yet enabled.  */
     bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
                             && pVM->cpum.s.HostFeatures.fXSaveRstor
-                            && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
-                            && pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL /** @todo test and enable on AMD! */;
-#else
-    bool const fMayHaveXSave = false;
-#endif
+                            && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
     /** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
      * Expose XSAVE/XRSTOR to the guest if available.  For the time being the