Changeset 55693 in vbox

Timestamp:

May 6, 2015 2:00:15 PM (10 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

100096

Message:

DevVGA-SVGA.cpp: Fixed for cubebench hang. The FIFO must take the lock when working over the IRQ state, just like the EMT (implicitly) does.

File:

• trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp (modified) (3 diffs)

trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp ¶

@@ -1240 +1240 @@
 
         /* Irq pending after the above change? */
-        if (pThis->svga.u32IrqMask & pThis->svga.u32IrqStatus)
+        if (pThis->svga.u32IrqStatus & u32)
         {
             Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
@@ -1498 +1498 @@
         /* Clear the irq in case all events have been cleared. */
         if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
+        {
+            Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
             PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
+        }
         break;
     }
@@ -3194 +3197 @@
             STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
 
-            /* FIFO progress might trigger an interrupt. */
-            if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
+            /*
+             * Raise IRQ if required.  Must enter the critical section here
+             * before making final decisions here, otherwise cubebench and
+             * others may end up waiting forever.
+             */
+            if (   u32IrqStatus
+                || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
             {
-                Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
-                u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
-            }
-
-            /* Irq pending? */
-            if (pThis->svga.u32IrqMask & u32IrqStatus)
-            {
-                Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
-                ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
-                PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
+                PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
+
+                /* FIFO progress might trigger an interrupt. */
+                if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
+                {
+                    Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
+                    u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
+                }
+
+                /* Unmasked IRQ pending? */
+                if (pThis->svga.u32IrqMask & u32IrqStatus)
+                {
+                    Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
+                    ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
+                    PDMDevHlpPCISetIrq(pDevIns, 0, 1);
+                }
+
+                PDMCritSectLeave(&pThis->CritSect);
             }
         }