VirtualBox

Changeset 56405 in vbox for trunk/src/VBox/Devices/Storage


Ignore:
Timestamp:
Jun 13, 2015 7:11:20 PM (10 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
101006
Message:

DevATA: Split out the data port from the IOPortBase1 I/O port registrations.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Storage/DevATA.cpp

    r56404 r56405  
    496496    /** Status LUN: Media Notify. */
    497497    R3PTRTYPE(PPDMIMEDIANOTIFY)     pMediaNotify;
    498     /** Flag whether GC is enabled. */
    499     bool                fGCEnabled;
     498    /** Flag whether RC is enabled. */
     499    bool                fRCEnabled;
    500500    /** Flag whether R0 is enabled. */
    501501    bool                fR0Enabled;
    … …  
    525525 ******************************************************************************/
    526526RT_C_DECLS_BEGIN
    527 PDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    528 PDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
    529 PDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
    530 PDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
     527
     528PDMBOTHCBDECL(int) ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
     529PDMBOTHCBDECL(int) ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
     530PDMBOTHCBDECL(int) ataIOPortWriteStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
     531PDMBOTHCBDECL(int) ataIOPortReadStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
     532PDMBOTHCBDECL(int) ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
     533PDMBOTHCBDECL(int) ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
    531534PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
    532535PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
    … …  
    58745877            rc = rc2;
    58755878
    5876         if (pThis->fGCEnabled)
     5879        if (pThis->fRCEnabled)
    58775880        {
    58785881            rc2 = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
    … …  
    59855988 * @see FNIOMIOPORTOUT for details.
    59865989 */
    5987 PDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     5990PDMBOTHCBDECL(int) ataIOPortWrite1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
    59885991{
    59895992    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    … …  
    59925995
    59935996    Assert(i < 2);
     5997    Assert(Port == pCtl->IOPortBase1);
    59945998
    59955999    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
    59966000    if (rc == VINF_SUCCESS)
    59976001    {
    5998         if (Port == pCtl->IOPortBase1)
    5999         {
    6000             /* Writes to the data port may be 16-bit or 32-bit. */
    6001             Assert(cb == 2 || cb == 4);
    6002             rc = ataDataWrite(pCtl, Port, cb, (const uint8_t *)&u32);
    6003         }
    6004         else
    6005         {
    6006             /* Writes to the other command block ports should be 8-bit only. If they
    6007              * are not, the high bits are simply discarded. Undocumented, but observed
    6008              * on a real PIIX4 system.
    6009              */
    6010             if (cb > 1)
    6011                 Log(("ataIOPortWrite1: suspect write to port %x val=%x size=%d\n", Port, u32, cb));
    6012 
    6013             rc = ataIOPortWriteU8(pCtl, Port, u32);
    6014         }
     6002        /* Writes to the data port may be 16-bit or 32-bit. */
     6003        Assert(cb == 2 || cb == 4);
     6004        rc = ataDataWrite(pCtl, Port, cb, (const uint8_t *)&u32);
     6005
    60156006        PDMCritSectLeave(&pCtl->lock);
    60166007    }
    … …  
    60236014 * @see FNIOMIOPORTIN for details.
    60246015 */
    6025 PDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     6016PDMBOTHCBDECL(int) ataIOPortRead1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
    60266017{
    60276018    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    … …  
    60306021
    60316022    Assert(i < 2);
     6023    Assert(Port == pCtl->IOPortBase1);
    60326024
    60336025    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
    60346026    if (rc == VINF_SUCCESS)
    60356027    {
    6036         if (Port == pCtl->IOPortBase1)
    6037         {
    6038             /* Reads from the data register may be 16-bit or 32-bit. */
    6039             Assert(cb == 1 || cb == 2 || cb == 4);
    6040             rc = ataDataRead(pCtl, Port, cb == 1 ? 2 : cb, (uint8_t *)pu32);
    6041             if (cb <= 2)
    6042                 *pu32 &= 0xffff >> (16 - cb * 8);
    6043         }
    6044         else
    6045         {
    6046             /* Reads from the other command block registers should be 8-bit only.
    6047              * If they are not, the low byte is propagated to the high bits.
    6048              * Undocumented, but observed on a real PIIX4 system.
    6049              */
    6050             rc = ataIOPortReadU8(pCtl, Port, pu32);
    6051             if (cb > 1)
    6052             {
    6053                 uint32_t    pad;
    6054 
    6055                 /* Replicate the 8-bit result into the upper three bytes. */
    6056                 pad = *pu32 & 0xff;
    6057                 pad = pad | (pad << 8);
    6058                 pad = pad | (pad << 16);
    6059                 *pu32 = pad;
    6060                 Log(("ataIOPortRead1: suspect read from port %x size=%d\n", Port, cb));
    6061             }
    6062         }
     6028        /* Reads from the data register may be 16-bit or 32-bit. */
     6029        Assert(cb == 1 || cb == 2 || cb == 4);
     6030        rc = ataDataRead(pCtl, Port, cb == 1 ? 2 : cb, (uint8_t *)pu32);
     6031        if (cb <= 2)
     6032            *pu32 &= 0xffff >> (16 - cb * 8);
     6033
    60636034        PDMCritSectLeave(&pCtl->lock);
    60646035    }
    … …  
    60736044 * @see FNIOMIOPORTINSTRING for details.
    60746045 */
    6075 PDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)
     6046PDMBOTHCBDECL(int) ataIOPortReadStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst,
     6047                                         PRTGCUINTREG pcTransfer, unsigned cb)
    60766048{
    60776049    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    … …  
    60816053
    60826054    Assert(i < 2);
     6055    Assert(Port == pCtl->IOPortBase1);
    60836056
    60846057    rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
    6085     if (rc != VINF_SUCCESS)
    6086         return rc;
    6087     if (Port == pCtl->IOPortBase1)
    6088     {
    6089         uint32_t cTransAvailable, cTransfer = *pcTransfer, cbTransfer;
    6090         RTGCPTR GCDst = *pGCPtrDst;
     6058    if (rc == VINF_SUCCESS)
     6059    {
    60916060        ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
     6061        uint32_t    cTransAvailable;
     6062        uint32_t    cTransfer = *pcTransfer;
     6063        uint32_t    cbTransfer;
     6064        RTGCPTR     GCDst = *pGCPtrDst;
    60926065        Assert(cb == 2 || cb == 4);
    60936066
    … …  
    61316104            ataHCPIOTransferFinish(pCtl, s);
    61326105# endif /* IN_RING3 */
    6133     }
    6134     PDMCritSectLeave(&pCtl->lock);
     6106        PDMCritSectLeave(&pCtl->lock);
     6107    }
    61356108    return rc;
    61366109}
    … …  
    61416114 * @see FNIOMIOPORTOUTSTRING for details.
    61426115 */
    6143 PDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)
     6116PDMBOTHCBDECL(int) ataIOPortWriteStr1Data(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc,
     6117                                          PRTGCUINTREG pcTransfer, unsigned cb)
    61446118{
    61456119    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
    … …  
    61496123
    61506124    Assert(i < 2);
     6125    Assert(Port == pCtl->IOPortBase1);
    61516126
    61526127    rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
    6153     if (rc != VINF_SUCCESS)
    6154         return rc;
    6155     if (Port == pCtl->IOPortBase1)
    6156     {
     6128    if (rc == VINF_SUCCESS)
     6129    {
     6130        ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
    61576131        uint32_t cTransfer = *pcTransfer;
    61586132        uint32_t cbTransfer;
    61596133        RTGCPTR GCSrc = *pGCPtrSrc;
    6160         ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
    61616134        Assert(cb == 2 || cb == 4);
    61626135
    … …  
    62006173            ataHCPIOTransferFinish(pCtl, s);
    62016174# endif /* IN_RING3 */
    6202     }
    6203     PDMCritSectLeave(&pCtl->lock);
     6175        PDMCritSectLeave(&pCtl->lock);
     6176    }
    62046177    return rc;
    62056178}
    62066179
    62076180#endif /* !IN_RING0 */
     6181
     6182/**
     6183 * Port I/O Handler for primary port range OUT operations.
     6184 * @see FNIOMIOPORTOUT for details.
     6185 */
     6186PDMBOTHCBDECL(int) ataIOPortWrite1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
     6187{
     6188    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
     6189    PCIATAState   *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
     6190    PATACONTROLLER pCtl = &pThis->aCts[i];
     6191
     6192    Assert(i < 2);
     6193    Assert(Port != pCtl->IOPortBase1);
     6194
     6195    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_WRITE);
     6196    if (rc == VINF_SUCCESS)
     6197    {
     6198        /* Writes to the other command block ports should be 8-bit only. If they
     6199         * are not, the high bits are simply discarded. Undocumented, but observed
     6200         * on a real PIIX4 system.
     6201         */
     6202        if (cb > 1)
     6203            Log(("ataIOPortWrite1: suspect write to port %x val=%x size=%d\n", Port, u32, cb));
     6204
     6205        rc = ataIOPortWriteU8(pCtl, Port, u32);
     6206
     6207        PDMCritSectLeave(&pCtl->lock);
     6208    }
     6209    return rc;
     6210}
     6211
     6212
     6213/**
     6214 * Port I/O Handler for primary port range IN operations.
     6215 * @see FNIOMIOPORTIN for details.
     6216 */
     6217PDMBOTHCBDECL(int) ataIOPortRead1Other(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
     6218{
     6219    uint32_t       i = (uint32_t)(uintptr_t)pvUser;
     6220    PCIATAState   *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
     6221    PATACONTROLLER pCtl = &pThis->aCts[i];
     6222
     6223    Assert(i < 2);
     6224    Assert(Port != pCtl->IOPortBase1);
     6225
     6226    int rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_R3_IOPORT_READ);
     6227    if (rc == VINF_SUCCESS)
     6228    {
     6229        /* Reads from the other command block registers should be 8-bit only.
     6230         * If they are not, the low byte is propagated to the high bits.
     6231         * Undocumented, but observed on a real PIIX4 system.
     6232         */
     6233        rc = ataIOPortReadU8(pCtl, Port, pu32);
     6234        if (cb > 1)
     6235        {
     6236            uint32_t    pad;
     6237
     6238            /* Replicate the 8-bit result into the upper three bytes. */
     6239            pad = *pu32 & 0xff;
     6240            pad = pad | (pad << 8);
     6241            pad = pad | (pad << 16);
     6242            *pu32 = pad;
     6243            Log(("ataIOPortRead1: suspect read from port %x size=%d\n", Port, cb));
     6244        }
     6245        PDMCritSectLeave(&pCtl->lock);
     6246    }
     6247    return rc;
     6248}
     6249
    62086250
    62096251/**
    … …  
    72547296    PPDMIBASE       pBase;
    72557297    int             rc;
    7256     bool            fGCEnabled;
     7298    bool            fRCEnabled;
    72577299    bool            fR0Enabled;
    72587300    uint32_t        DelayIRQMillies;
    … …  
    72837325                                N_("PIIX3 configuration error: unknown option specified"));
    72847326
    7285     rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
     7327    rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
    72867328    if (RT_FAILURE(rc))
    72877329        return PDMDEV_SET_ERROR(pDevIns, rc,
    72887330                                N_("PIIX3 configuration error: failed to read GCEnabled as boolean"));
    7289     Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
     7331    Log(("%s: fRCEnabled=%d\n", __FUNCTION__, fRCEnabled));
    72907332
    72917333    rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
    … …  
    73647406
    73657407    pThis->pDevIns          = pDevIns;
    7366     pThis->fGCEnabled       = fGCEnabled;
     7408    pThis->fRCEnabled       = fRCEnabled;
    73677409    pThis->fR0Enabled       = fR0Enabled;
    73687410    for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
    … …  
    74267468    for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
    74277469    {
    7428         rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTHCPTR)(uintptr_t)i,
    7429                                      ataIOPortWrite1, ataIOPortRead1,
    7430                                      ataIOPortWriteStr1, ataIOPortReadStr1,
    7431                                      "ATA I/O Base 1");
    7432         if (RT_FAILURE(rc))
    7433             return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers"));
    7434 
    7435         if (fGCEnabled)
    7436         {
    7437             rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i,
    7438                                            "ataIOPortWrite1", "ataIOPortRead1",
    7439                                            "ataIOPortWriteStr1", "ataIOPortReadStr1",
    7440                                            "ATA I/O Base 1");
    7441             if (RT_FAILURE(rc))
    7442                 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers (GC)"));
     7470        rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTHCPTR)(uintptr_t)i,
     7471                                     ataIOPortWrite1Data, ataIOPortRead1Data,
     7472                                     ataIOPortWriteStr1Data, ataIOPortReadStr1Data, "ATA I/O Base 1 - Data");
     7473        AssertLogRelRCReturn(rc, rc);
     7474        rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTHCPTR)(uintptr_t)i,
     7475                                     ataIOPortWrite1Other, ataIOPortRead1Other, NULL, NULL, "ATA I/O Base 1 - Other");
     7476
     7477        AssertLogRelRCReturn(rc, rc);
     7478        if (fRCEnabled)
     7479        {
     7480            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTGCPTR)i,
     7481                                           "ataIOPortWrite1Data", "ataIOPortRead1Data",
     7482                                           "ataIOPortWriteStr1Data", "ataIOPortReadStr1Data", "ATA I/O Base 1 - Data");
     7483            AssertLogRelRCReturn(rc, rc);
     7484            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTGCPTR)i,
     7485                                           "ataIOPortWrite1Other", "ataIOPortRead1Other", NULL, NULL, "ATA I/O Base 1 - Other");
     7486            AssertLogRelRCReturn(rc, rc);
    74437487        }
    74447488
    … …  
    74467490        {
    74477491#if 1
    7448             rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
    7449                                            "ataIOPortWrite1", "ataIOPortRead1", NULL, NULL, "ATA I/O Base 1");
     7492            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTR0PTR)i,
     7493                                           "ataIOPortWrite1Data", "ataIOPortRead1Data", NULL, NULL, "ATA I/O Base 1 - Data");
    74507494#else
    7451             rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
    7452                                            "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1");
     7495            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 1, (RTR0PTR)i,
     7496                                           "ataIOPortWrite1Data", "ataIOPortRead1Data",
     7497                                           "ataIOPortWriteStr1Data", "ataIOPortReadStr1Data", "ATA I/O Base 1 - Data");
    74537498#endif
    7454             if (RT_FAILURE(rc))
    7455                 return PDMDEV_SET_ERROR(pDevIns, rc, "PIIX3 cannot register I/O handlers (R0).");
     7499            AssertLogRelRCReturn(rc, rc);
     7500            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1 + 1, 7, (RTR0PTR)i,
     7501                                           "ataIOPortWrite1Other", "ataIOPortRead1Other", NULL, NULL, "ATA I/O Base 1 - Other");
     7502            AssertLogRelRCReturn(rc, rc);
    74567503        }
    74577504
    … …  
    74617508            return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers"));
    74627509
    7463         if (fGCEnabled)
     7510        if (fRCEnabled)
    74647511        {
    74657512            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,
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