Changeset 57237 in vbox for trunk/src/VBox/VMM/VMMR0
- Timestamp:
- Aug 7, 2015 10:24:50 AM (9 years ago)
- Location:
- trunk/src/VBox/VMM/VMMR0
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r57062 r57237 2014 2014 * Guest TR. 2015 2015 * Fixup TR attributes so it's compatible with Intel. Important when saved-states are used 2016 * between Intel and AMD. See @bugref{6208 } comment #39.2016 * between Intel and AMD. See @bugref{6208#c39}. 2017 2017 * ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode. 2018 2018 */ -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r57211 r57237 3826 3826 else 3827 3827 { 3828 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626 } comment #11. */3828 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */ 3829 3829 pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK; 3830 3830 } … … 4842 4842 AssertRCReturn(rc, rc); 4843 4843 4844 /* We need to intercept reads too, see @bugref{7386 } comment #16. */4844 /* We need to intercept reads too, see @bugref{7386#c16}. */ 4845 4845 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS) 4846 4846 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE); -
trunk/src/VBox/VMM/VMMR0/VMMR0.cpp
r57229 r57237 547 547 * preemption after doing the callout (one or two functions up the 548 548 * call chain). */ 549 /** @todo r=ramshankar: See @bugref{5313 } comment #30. */549 /** @todo r=ramshankar: See @bugref{5313#c30}. */ 550 550 RTTHREADPREEMPTSTATE ParanoidPreemptState = RTTHREADPREEMPTSTATE_INITIALIZER; 551 551 RTThreadPreemptDisable(&ParanoidPreemptState); … … 648 648 /* 649 649 * Clear the VCPU <-> host CPU mapping as we've left HM context. 650 * @bugref{7726 } comment #19explains the need for this trick:650 * @bugref{7726#c19} explains the need for this trick: 651 651 * 652 652 * hmR0VmxCallRing3Callback/hmR0SvmCallRing3Callback &
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