Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Contributions.txt
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Contributions.txt	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Contributions.txt	(revision 58464)
@@ -0,0 +1,202 @@
+
+======================
+= Code Contributions =
+======================
+
+To make a contribution to a TianoCore project, follow these steps.
+1. Create a change description in the format specified below to
+   use in the source control commit log.
+2. Your commit message must include your "Signed-off-by" signature,
+   and "Contributed-under" message.
+3. Your "Contributed-under" message explicitly states that the
+   contribution is made under the terms of the specified
+   contribution agreement.  Your "Contributed-under" message
+   must include the name of contribution agreement and version.
+   For example: Contributed-under: TianoCore Contribution Agreement 1.0
+   The "TianoCore Contribution Agreement" is included below in
+   this document.
+4. Submit your code to the TianoCore project using the process
+   that the project documents on its web page.  If the process is
+   not documented, then submit the code on development email list
+   for the project.
+5. It is preferred that contributions are submitted using the same
+   copyright license as the base project. When that is not possible,
+   then contributions using the following licenses can be accepted:
+   * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
+   * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
+   * MIT: http://opensource.org/licenses/MIT
+   * Python-2.0: http://opensource.org/licenses/Python-2.0
+   * Zlib: http://opensource.org/licenses/Zlib
+
+   Contributions of code put into the public domain can also be
+   accepted.
+
+   Contributions using other licenses might be accepted, but further
+   review will be required.
+
+=======================================
+= Change Description / Commit Message =
+=======================================
+
+Your change description should use the standard format for a
+commit message, and must include your "Signed-off-by" signature
+and the "Contributed-under" message.
+
+== Sample Change Description / Commit Message =
+
+=== Definitions for sample change description ===
+
+* "CodeModule" is a short idenfier for the affected code.  For
+  example MdePkg, or MdeModulePkg UsbBusDxe.
+* "Brief-single-line-summary" is a short summary of the change.
+* The entire first line should be less than ~70 characters.
+* "Full-commit-message" a verbose multiple line comment describing
+  the change.  Each line should be less than ~70 characters.
+* "Contributed-under" explicitely states that the contribution is
+  made under the terms of the contribtion agreement.  This
+  agreement is included below in this document.
+* "Signed-off-by" is the contributor's signature identifying them
+  by their real/legal name and their email address.
+
+=== Start of sample change description / commit message ===
+CodeModule: Brief-single-line-summary
+
+Full-commit-message
+
+Contributed-under: TianoCore Contribution Agreement 1.0
+Signed-off-by: Contributor Name <contributor@email.server>
+=== End of sample change description / commit message ===
+
+========================================
+= TianoCore Contribution Agreement 1.0 =
+========================================
+
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
+USE THE CONTENT.
+
+Unless otherwise indicated, all Content made available on the TianoCore
+site is provided to you under the terms and conditions of the BSD
+License ("BSD"). A copy of the BSD License is available at
+http://opensource.org/licenses/bsd-license.php
+or when applicable, in the associated License.txt file.
+
+Certain other content may be made available under other licenses as
+indicated in or with such Content. (For example, in a License.txt file.)
+
+You accept and agree to the following terms and conditions for Your
+present and future Contributions submitted to TianoCore site. Except
+for the license granted to Intel hereunder, You reserve all right,
+title, and interest in and to Your Contributions.
+
+== SECTION 1: Definitions ==
+* "You" or "Contributor" shall mean the copyright owner or legal
+  entity authorized by the copyright owner that is making a
+  Contribution hereunder. All other entities that control, are
+  controlled by, or are under common control with that entity are
+  considered to be a single Contributor. For the purposes of this
+  definition, "control" means (i) the power, direct or indirect, to
+  cause the direction or management of such entity, whether by
+  contract or otherwise, or (ii) ownership of fifty percent (50%)
+  or more of the outstanding shares, or (iii) beneficial ownership
+  of such entity.
+* "Contribution" shall mean any original work of authorship,
+  including any modifications or additions to an existing work,
+  that is intentionally submitted by You to the TinaoCore site for
+  inclusion in, or documentation of, any of the Content. For the
+  purposes of this definition, "submitted" means any form of
+  electronic, verbal, or written communication sent to the
+  TianoCore site or its representatives, including but not limited
+  to communication on electronic mailing lists, source code
+  control systems, and issue tracking systems that are managed by,
+  or on behalf of, the TianoCore site for the purpose of
+  discussing and improving the Content, but excluding
+  communication that is conspicuously marked or otherwise
+  designated in writing by You as "Not a Contribution."
+
+== SECTION 2: License for Contributions ==
+* Contributor hereby agrees that redistribution and use of the
+  Contribution in source and binary forms, with or without
+  modification, are permitted provided that the following
+  conditions are met:
+** Redistributions of source code must retain the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer.
+** Redistributions in binary form must reproduce the Contributor's
+   copyright notice, this list of conditions and the following
+   disclaimer in the documentation and/or other materials provided
+   with the distribution.
+* Disclaimer. None of the names of Contributor, Intel, or the names
+  of their respective contributors may be used to endorse or
+  promote products derived from this software without specific
+  prior written permission.
+* Contributor grants a license (with the right to sublicense) under
+  claims of Contributor's patents that Contributor can license that
+  are infringed by the Contribution (as delivered by Contributor) to
+  make, use, distribute, sell, offer for sale, and import the
+  Contribution and derivative works thereof solely to the minimum
+  extent necessary for licensee to exercise the granted copyright
+  license; this patent license applies solely to those portions of
+  the Contribution that are unmodified. No hardware per se is
+  licensed.
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
+  CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
+  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+  PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+  CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
+  CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+  DAMAGE.
+
+== SECTION 3: Representations ==
+* You represent that You are legally entitled to grant the above
+  license. If your employer(s) has rights to intellectual property
+  that You create that includes Your Contributions, You represent
+  that You have received permission to make Contributions on behalf
+  of that employer, that Your employer has waived such rights for
+  Your Contributions.
+* You represent that each of Your Contributions is Your original
+  creation (see Section 4 for submissions on behalf of others).
+  You represent that Your Contribution submissions include complete
+  details of any third-party license or other restriction
+  (including, but not limited to, related patents and trademarks)
+  of which You are personally aware and which are associated with
+  any part of Your Contributions.
+
+== SECTION 4: Third Party Contributions ==
+* Should You wish to submit work that is not Your original creation,
+  You may submit it to TianoCore site separately from any
+  Contribution, identifying the complete details of its source
+  and of any license or other restriction (including, but not
+  limited to, related patents, trademarks, and license agreements)
+  of which You are personally aware, and conspicuously marking the
+  work as "Submitted on behalf of a third-party: [named here]".
+
+== SECTION 5: Miscellaneous ==
+* Applicable Laws. Any claims arising under or relating to this
+  Agreement shall be governed by the internal substantive laws of
+  the State of Delaware or federal courts located in Delaware,
+  without regard to principles of conflict of laws.
+* Language. This Agreement is in the English language only, which
+  language shall be controlling in all respects, and all versions
+  of this Agreement in any other language shall be for accommodation
+  only and shall not be binding. All communications and notices made
+  or given pursuant to this Agreement, and all documentation and
+  support to be provided, unless otherwise noted, shall be in the
+  English language.
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxe.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxe.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxe.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// Simple CPU driver installs CPU Architecture Protocol.
+//
+// Simple CPU driver installs CPU Architecture Protocol.
+//
+// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Installs CPU Architecture Protocol"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Simple CPU driver installs CPU Architecture Protocol."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxeExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxeExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/CpuDxeExtra.uni	(revision 58464)
@@ -0,0 +1,20 @@
+﻿// /** @file
+// CpuDxe Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME 
+#language en-US 
+"CPU Architectural DXE Driver"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Produces the CPU I/O 2 Protocol by using the services of the I/O Library"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Produces the CPU I/O 2 Protocol by using the services of the I/O Library."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2DxeExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2DxeExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2DxeExtra.uni	(revision 58464)
@@ -0,0 +1,20 @@
+﻿// /** @file
+// CpuIo2Dxe Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME 
+#language en-US 
+"CPU I/O v2 DXE Driver"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.uni	(revision 58464)
@@ -0,0 +1,21 @@
+﻿// /** @file
+// Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.
+//
+// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2SmmExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2SmmExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2SmmExtra.uni	(revision 58464)
@@ -0,0 +1,19 @@
+﻿// /** @file
+// CpuIo2Smm Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME 
+#language en-US
+"CPU I/O v2 SMM Driver"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// Produces the CPU I/O PPI by using the services of the I/O Library.
+//
+// Produces the CPU I/O PPI by using the services of the I/O Library.
+//
+// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Produces the CPU I/O PPI by using the services of the I/O Library"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Produces the CPU I/O PPI by using the services of the I/O Library."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPeiExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPeiExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPeiExtra.uni	(revision 58464)
@@ -0,0 +1,20 @@
+﻿// /** @file
+// CpuIoPei Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME 
+#language en-US 
+"CPU I/O PEI Module"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// This library defines some routines that are generic for IA32 family CPU.
+//
+// The library routines are UEFI specification compliant.
+//
+// Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Defines generic routines for IA32 family CPUs."
+
+#string STR_MODULE_DESCRIPTION          #language en-US "The library routines comply with the UEFI Specification."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.uni	(revision 58464)
@@ -0,0 +1,23 @@
+﻿// /** @file
+// The Local Apic library supports xAPIC mode only.
+//
+// Note: Local APIC library assumes local APIC is enabled. It does not handle cases
+// where local APIC is disabled.
+//
+// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Supports xAPIC mode only"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Note: Local APIC library assumes local APIC is enabled. It does not handle cases where local APIC is disabled."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni	(revision 58464)
@@ -0,0 +1,23 @@
+﻿// /** @file
+// The Local Apic library supports x2APIC capable processors which have xAPIC and x2APIC modes.
+//
+// Note: Local APIC library assumes local APIC is enabled. It does not handle cases
+// where local APIC is disabled.
+//
+// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Supports x2APIC capable processors that have xAPIC and x2APIC modes"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Note: Local APIC library assumes local APIC is enabled. It does not handle cases where local APIC is disabled."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c	(revision 58464)
@@ -0,0 +1,173 @@
+/** @file
+  CPU Exception Handler Library common functions.
+
+  Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuExceptionCommon.h"
+
+//
+// Error code flag indicating whether or not an error code will be
+// pushed on the stack if an exception occurs.
+//
+// 1 means an error code will be pushed, otherwise 0
+//
+CONST UINT32 mErrorCodeFlag             = 0x00027d00;
+RESERVED_VECTORS_DATA *mReservedVectors = NULL;
+
+//
+// Define the maximum message length 
+//
+#define MAX_DEBUG_MESSAGE_LENGTH  0x100
+
+/**
+  Prints a message to the serial port.
+
+  @param  Format      Format string for the message to print.
+  @param  ...         Variable argument list whose contents are accessed 
+                      based on the format string specified by Format.
+
+**/
+VOID
+EFIAPI
+InternalPrintMessage (
+  IN  CONST CHAR8  *Format,
+  ...
+  )
+{
+  CHAR8    Buffer[MAX_DEBUG_MESSAGE_LENGTH];
+  VA_LIST  Marker;
+
+  //
+  // Convert the message to an ASCII String
+  //
+  VA_START (Marker, Format);
+  AsciiVSPrint (Buffer, sizeof (Buffer), Format, Marker);
+  VA_END (Marker);
+
+  //
+  // Send the print string to a Serial Port 
+  //
+  SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
+}
+
+/**
+  Find and display image base address and return image base and its entry point.
+  
+  @param CurrentEip      Current instruction pointer.
+  @param EntryPoint      Return module entry point if module header is found.
+  
+  @return !0     Image base address.
+  @return 0      Image header cannot be found.
+**/
+UINTN 
+FindModuleImageBase (
+  IN  UINTN              CurrentEip,
+  OUT UINTN              *EntryPoint
+  )
+{
+  UINTN                                Pe32Data;
+  EFI_IMAGE_DOS_HEADER                 *DosHdr;
+  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION  Hdr;
+  VOID                                 *PdbPointer;
+
+  //
+  // Find Image Base
+  //
+  Pe32Data = CurrentEip & ~(mImageAlignSize - 1);
+  while (Pe32Data != 0) {
+    DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
+    if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+      //
+      // DOS image header is present, so read the PE header after the DOS image header.
+      //
+      Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
+      //
+      // Make sure PE header address does not overflow and is less than the initial address.
+      //
+      if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CurrentEip)) {
+        if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
+          //
+          // It's PE image.
+          //
+          InternalPrintMessage ("!!!! Find PE image ");
+          *EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff);
+          break;
+        }
+      }
+    } else {
+      //
+      // DOS image header is not present, TE header is at the image base.
+      //
+      Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
+      if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
+          ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine == IMAGE_FILE_MACHINE_X64)) {
+        //
+        // It's TE image, it TE header and Machine type match
+        //
+        InternalPrintMessage ("!!!! Find TE image ");
+        *EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;
+        break;
+      }
+    }
+
+    //
+    // Not found the image base, check the previous aligned address
+    // 
+    Pe32Data -= mImageAlignSize;
+  }
+
+  if (Pe32Data != 0) {
+    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
+    if (PdbPointer != NULL) {
+      InternalPrintMessage ("%a", PdbPointer);
+    } else {
+      InternalPrintMessage ("(No PDB) " );
+    }
+  } else {
+    InternalPrintMessage ("!!!! Can't find image information. !!!!\n");
+  }
+
+  return Pe32Data;
+}
+
+/**
+  Read and save reserved vector information
+  
+  @param[in]  VectorInfo        Pointer to reserved vector list.
+  @param[out] ReservedVector    Pointer to reserved vector data buffer.
+  @param[in]  VectorCount       Vector number to be updated.
+  
+  @return EFI_SUCCESS           Read and save vector info successfully.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+
+**/
+EFI_STATUS
+ReadAndVerifyVectorInfo (
+  IN  EFI_VECTOR_HANDOFF_INFO       *VectorInfo,
+  OUT RESERVED_VECTORS_DATA         *ReservedVector,
+  IN  UINTN                         VectorCount
+  )
+{
+  while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
+    if (VectorInfo->Attribute > EFI_VECTOR_HANDOFF_HOOK_AFTER) {
+      //
+      // If vector attrubute is invalid
+      //
+      return EFI_INVALID_PARAMETER;
+    }
+    if (VectorInfo->VectorNumber < VectorCount) {
+      ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
+    }
+    VectorInfo ++;
+  }
+  return EFI_SUCCESS;
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h	(revision 58464)
@@ -0,0 +1,241 @@
+/** @file
+  Common header file for CPU Exception Handler Library.
+
+  Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_EXCEPTION_COMMON_H_
+#define _CPU_EXCEPTION_COMMON_H_
+
+#include <Ppi/VectorHandoffInfo.h>
+#include <Protocol/Cpu.h>
+#include <Library/BaseLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/PrintLib.h>
+#include <Library/LocalApicLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SynchronizationLib.h>
+
+#define  CPU_EXCEPTION_NUM          32
+#define  CPU_INTERRUPT_NUM         256
+#define  HOOKAFTER_STUB_SIZE        16
+
+#include "ArchInterruptDefs.h"
+
+//
+// Record exception handler information
+//
+typedef struct {
+  UINTN ExceptionStart;
+  UINTN ExceptionStubHeaderSize;
+  UINTN HookAfterStubHeaderStart;
+} EXCEPTION_HANDLER_TEMPLATE_MAP;
+
+extern CONST UINT32                mErrorCodeFlag;
+extern CONST UINTN                 mImageAlignSize;
+extern CONST UINTN                 mDoFarReturnFlag;
+extern RESERVED_VECTORS_DATA       *mReservedVectors;
+
+/**
+  Return address map of exception handler template so that C code can generate
+  exception tables.
+
+  @param AddressMap  Pointer to a buffer where the address map is returned.
+**/
+VOID
+EFIAPI
+AsmGetTemplateAddressMap (
+  OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+  );
+
+/**
+  Return address map of exception handler template so that C code can generate
+  exception tables.
+
+  @param IdtEntry          Pointer to IDT entry to be updated.
+  @param InterruptHandler  IDT handler value.
+
+**/
+VOID
+ArchUpdateIdtEntry (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry,
+  IN UINTN                           InterruptHandler
+  );
+
+/**
+  Read IDT handler value from IDT entry.
+
+  @param IdtEntry          Pointer to IDT entry to be read.
+
+**/
+UINTN
+ArchGetIdtHandler (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry
+  );
+
+/**
+  Prints a message to the serial port.
+
+  @param  Format      Format string for the message to print.
+  @param  ...         Variable argument list whose contents are accessed 
+                      based on the format string specified by Format.
+
+**/
+VOID
+EFIAPI
+InternalPrintMessage (
+  IN  CONST CHAR8  *Format,
+  ...
+  );
+
+/**
+  Find and display image base address and return image base and its entry point.
+  
+  @param CurrentEip      Current instruction pointer.
+  @param EntryPoint      Return module entry point if module header is found.
+  
+  @return !0     Image base address.
+  @return 0      Image header cannot be found.
+**/
+UINTN 
+FindModuleImageBase (
+  IN  UINTN              CurrentEip,
+  OUT UINTN              *EntryPoint
+  );
+
+/**
+  Display CPU information.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpCpuContent (
+  IN EFI_EXCEPTION_TYPE   ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  );
+
+/**
+  Internal worker function to initialize exception handler.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+InitializeCpuExceptionHandlersWorker (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  );
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+RegisterCpuInterruptHandlerWorker (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  );
+
+/**
+  Internal worker function to update IDT entries accordling to vector attributes.
+
+  @param[in] IdtTable       Pointer to IDT table.
+  @param[in] TemplateMap    Pointer to a buffer where the address map is returned.
+  @param[in] IdtEntryCount  IDT entries number to be updated.
+
+**/
+VOID
+UpdateIdtTable (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtTable,
+  IN EXCEPTION_HANDLER_TEMPLATE_MAP  *TemplateMap,
+  IN UINTN                           IdtEntryCount
+  );
+
+/**
+  Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param[in] ExceptionType  Exception type.
+  @param[in] SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+
+**/
+VOID
+ArchSaveExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  );
+
+/**
+  Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param[in] ExceptionType  Exception type.
+  @param[in] SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+
+**/
+VOID
+ArchRestoreExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  );
+
+/**
+  Fix up the vector number and function address in the vector code.
+ 
+  @param[in] NewVectorAddr   New vector handler address.
+  @param[in] VectorNum       Index of vector.
+  @param[in] OldVectorAddr   Old vector handler address.
+
+**/
+VOID
+EFIAPI
+AsmVectorNumFixup (
+  IN VOID    *NewVectorAddr,
+  IN UINT8   VectorNum,
+  IN VOID    *OldVectorAddr
+  );
+
+/**
+  Read and save reserved vector information
+  
+  @param[in]  VectorInfo        Pointer to reserved vector list.
+  @param[out] ReservedVector    Pointer to reserved vector data buffer.
+  @param[in]  VectorCount       Vector number to be updated.
+  
+  @return EFI_SUCCESS           Read and save vector info successfully.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+
+**/
+EFI_STATUS
+ReadAndVerifyVectorInfo (
+  IN  EFI_VECTOR_HANDOFF_INFO       *VectorInfo,
+  OUT RESERVED_VECTORS_DATA         *ReservedVector,
+  IN  UINTN                         VectorCount
+  );
+
+#endif
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf	(revision 58464)
@@ -0,0 +1,64 @@
+## @file
+#  CPU Exception Handler library instance for DXE modules.
+#
+#  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = DxeCpuExceptionHandlerLib
+  MODULE_UNI_FILE                = DxeCpuExceptionHandlerLib.uni
+  FILE_GUID                      = B6E9835A-EDCF-4748-98A8-27D3C722E02D
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpuExceptionHandlerLib|DXE_CORE DXE_DRIVER UEFI_APPLICATION
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Sources.Ia32]
+  Ia32/ExceptionHandlerAsm.asm
+  Ia32/ExceptionHandlerAsm.S   |GCC
+  Ia32/ArchExceptionHandler.c
+  Ia32/ArchInterruptDefs.h
+
+[Sources.X64]
+  X64/ExceptionHandlerAsm.asm
+  X64/ExceptionHandlerAsm.S     |GCC
+  X64/ArchExceptionHandler.c
+  X64/ArchInterruptDefs.h
+
+[Sources.common]
+  CpuExceptionCommon.h
+  CpuExceptionCommon.c
+  DxeSmmCpuException.c
+  DxeException.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  SerialPortLib
+  PrintLib
+  SynchronizationLib
+  LocalApicLib
+  PeCoffGetEntryPointLib 
+  MemoryAllocationLib
+  DebugLib
+
+[Ppis]
+  gEfiVectorHandoffInfoPpiGuid
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// CPU Exception Handler library instance for DXE modules.
+//
+// CPU Exception Handler library instance for DXE modules.
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "CPU Exception Handler library instance for DXE modules."
+
+#string STR_MODULE_DESCRIPTION          #language en-US "CPU Exception Handler library instance for DXE modules."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c	(revision 58464)
@@ -0,0 +1,170 @@
+/** @file
+  CPU exception handler library implemenation for DXE modules.
+
+  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include "CpuExceptionCommon.h"
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+CONST UINTN    mDoFarReturnFlag  = 0;
+
+extern SPIN_LOCK                   mDisplayMessageSpinLock;
+extern EFI_CPU_INTERRUPT_HANDLER   *mExternalInterruptHandler;
+
+/**
+  Initializes all CPU exceptions entries and provides the default exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return InitializeCpuExceptionHandlersWorker (VectorInfo);
+}
+
+/**
+  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
+                                with default interrupt/exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  EFI_STATUS                         Status;
+  IA32_IDT_GATE_DESCRIPTOR           *IdtTable;
+  IA32_DESCRIPTOR                    IdtDescriptor;
+  UINTN                              IdtEntryCount;
+  EXCEPTION_HANDLER_TEMPLATE_MAP     TemplateMap;
+  UINTN                              Index;
+  UINTN                              InterruptEntry;
+  UINT8                              *InterruptEntryCode;
+
+  mReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM);
+  ASSERT (mReservedVectors != NULL);
+  SetMem ((VOID *) mReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
+  if (VectorInfo != NULL) {
+    Status = ReadAndVerifyVectorInfo (VectorInfo, mReservedVectors, CPU_INTERRUPT_NUM);
+    if (EFI_ERROR (Status)) {
+      FreePool (mReservedVectors);
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+  InitializeSpinLock (&mDisplayMessageSpinLock);
+  mExternalInterruptHandler = AllocateZeroPool (sizeof (EFI_CPU_INTERRUPT_HANDLER) * CPU_INTERRUPT_NUM);
+  ASSERT (mExternalInterruptHandler != NULL);
+
+  //
+  // Read IDT descriptor and calculate IDT size
+  //
+  AsmReadIdtr (&IdtDescriptor);
+  IdtEntryCount = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
+  if (IdtEntryCount > CPU_INTERRUPT_NUM) {
+    IdtEntryCount = CPU_INTERRUPT_NUM;
+  }
+  //
+  // Create Interrupt Descriptor Table and Copy the old IDT table in
+  //
+  IdtTable = AllocateZeroPool (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM);
+  ASSERT (IdtTable != NULL);
+  CopyMem (IdtTable, (VOID *)IdtDescriptor.Base, sizeof (IA32_IDT_GATE_DESCRIPTOR) * IdtEntryCount);
+
+  AsmGetTemplateAddressMap (&TemplateMap);
+  ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
+  InterruptEntryCode = AllocatePool (TemplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NUM);
+  ASSERT (InterruptEntryCode != NULL);
+  
+  InterruptEntry = (UINTN) InterruptEntryCode;
+  for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) {
+    CopyMem (
+      (VOID *) InterruptEntry,
+      (VOID *) TemplateMap.ExceptionStart,
+      TemplateMap.ExceptionStubHeaderSize
+      );
+    AsmVectorNumFixup ((VOID *) InterruptEntry,  (UINT8) Index, (VOID *) TemplateMap.ExceptionStart);
+    InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
+  }
+
+  TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode;
+  UpdateIdtTable (IdtTable, &TemplateMap, CPU_INTERRUPT_NUM);
+
+  //
+  // Load Interrupt Descriptor Table
+  //
+  IdtDescriptor.Base  = (UINTN) IdtTable;
+  IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
+  AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  This function registers and enables the handler specified by InterruptHandler for a processor 
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  The installed handler is called once for each processor interrupt or exception.
+  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+  InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  )
+{
+  return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler);
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeSmmCpuException.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeSmmCpuException.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeSmmCpuException.c	(revision 58464)
@@ -0,0 +1,292 @@
+/** @file
+  CPU Exception Library provides DXE/SMM CPU common exception handler.
+
+Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuExceptionCommon.h"
+#include <Library/DebugLib.h>
+
+//
+// Spinlock for CPU information display
+//
+SPIN_LOCK        mDisplayMessageSpinLock;
+
+//
+// Image align size for DXE/SMM
+//
+CONST UINTN      mImageAlignSize = SIZE_4KB;
+
+RESERVED_VECTORS_DATA       mReservedVectorsData[CPU_EXCEPTION_NUM];
+EFI_CPU_INTERRUPT_HANDLER   mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
+EFI_CPU_INTERRUPT_HANDLER   *mExternalInterruptHandler = NULL;
+UINTN                       mEnabledInterruptNum = 0;
+
+/**
+  Common exception handler.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+EFIAPI
+CommonExceptionHandler (
+  IN EFI_EXCEPTION_TYPE          ExceptionType, 
+  IN EFI_SYSTEM_CONTEXT          SystemContext
+  )
+{
+  EXCEPTION_HANDLER_CONTEXT      *ExceptionHandlerContext;
+
+  ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32);
+
+  switch (mReservedVectors[ExceptionType].Attribute) {
+  case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
+    //
+    // Need to jmp to old IDT handler after this exception handler
+    //
+    ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
+    ExceptionHandlerContext->OldIdtHandler     = mReservedVectors[ExceptionType].ExceptonHandler;
+    break;
+  case EFI_VECTOR_HANDOFF_HOOK_AFTER:
+    while (TRUE) {
+      //
+      // If if anyone has gotten SPIN_LOCK for owner running hook after
+      //
+      if (AcquireSpinLockOrFail (&mReservedVectors[ExceptionType].SpinLock)) {
+        //
+        // Need to execute old IDT handler before running this exception handler
+        //
+        mReservedVectors[ExceptionType].ApicId = GetApicId ();
+        ArchSaveExceptionContext (ExceptionType, SystemContext);
+        ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
+        ExceptionHandlerContext->OldIdtHandler     = mReservedVectors[ExceptionType].ExceptonHandler;
+        return;
+      }
+      //
+      // If failed to acquire SPIN_LOCK, check if it was locked by processor itself
+      //
+      if (mReservedVectors[ExceptionType].ApicId == GetApicId ()) {
+        //
+        // Old IDT handler has been executed, then retore CPU exception content to
+        // run new exception handler.
+        //
+        ArchRestoreExceptionContext (ExceptionType, SystemContext);
+        //
+        // Rlease spin lock for ApicId
+        //
+        ReleaseSpinLock (&mReservedVectors[ExceptionType].SpinLock);
+        break;
+      }
+      CpuPause ();
+    }
+    break;
+  case 0xffffffff:
+    break;
+  default:
+    //
+    // It should never reach here
+    //
+    CpuDeadLoop ();
+    break;
+  }
+  
+  if (mExternalInterruptHandler[ExceptionType] != NULL) {
+    (mExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
+  } else if (ExceptionType < CPU_EXCEPTION_NUM) {
+    //
+    // Get Spinlock to display CPU information
+    //
+    while (!AcquireSpinLockOrFail (&mDisplayMessageSpinLock)) {
+      CpuPause ();
+    }
+    //
+    // Display ExceptionType, CPU information and Image information
+    //  
+    DumpCpuContent (ExceptionType, SystemContext);
+    //
+    // Release Spinlock of output message
+    //
+    ReleaseSpinLock (&mDisplayMessageSpinLock);
+    //
+    // Enter a dead loop if needn't to execute old IDT handler further
+    //
+    if (mReservedVectors[ExceptionType].Attribute != EFI_VECTOR_HANDOFF_HOOK_BEFORE) {
+      CpuDeadLoop ();
+    }
+  }
+}
+
+/**
+  Internal worker function to update IDT entries accordling to vector attributes.
+
+  @param[in] IdtTable       Pointer to IDT table.
+  @param[in] TemplateMap    Pointer to a buffer where the address map is returned.
+  @param[in] IdtEntryCount  IDT entries number to be updated.
+
+**/
+VOID
+UpdateIdtTable (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtTable,
+  IN EXCEPTION_HANDLER_TEMPLATE_MAP  *TemplateMap,
+  IN UINTN                           IdtEntryCount
+  )
+{
+  UINT16                             CodeSegment;
+  UINTN                              Index;
+  UINTN                              InterruptHandler;
+
+  //
+  // Use current CS as the segment selector of interrupt gate in IDT
+  //
+  CodeSegment = AsmReadCs ();
+
+  for (Index = 0; Index < IdtEntryCount; Index ++) {
+    IdtTable[Index].Bits.Selector = CodeSegment;
+    //
+    // Check reserved vectors attributes
+    //
+    switch (mReservedVectors[Index].Attribute) {
+    case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:
+      //
+      // Keep original IDT entry
+      //
+      continue;
+    case EFI_VECTOR_HANDOFF_HOOK_AFTER:
+      InitializeSpinLock (&mReservedVectors[Index].SpinLock);
+      CopyMem (
+        (VOID *) mReservedVectors[Index].HookAfterStubHeaderCode,
+        (VOID *) TemplateMap->HookAfterStubHeaderStart,
+        TemplateMap->ExceptionStubHeaderSize
+        );
+      AsmVectorNumFixup (
+        (VOID *) mReservedVectors[Index].HookAfterStubHeaderCode,
+        (UINT8) Index,
+        (VOID *) TemplateMap->HookAfterStubHeaderStart
+        );
+      //
+      // Go on the following code
+      //
+    case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
+      //
+      // Save original IDT handler address
+      //
+      mReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);
+      //
+      // Go on the following code
+      //
+    default:
+      //
+      // Update new IDT entry
+      //
+      InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;
+      ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
+      break;
+    }
+  }
+ 
+  //
+  // Save Interrupt number to global variable used for RegisterCpuInterruptHandler ()
+  //
+  mEnabledInterruptNum = IdtEntryCount;
+}
+
+/**
+  Internal worker function to initialize exception handler.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+InitializeCpuExceptionHandlersWorker (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  EFI_STATUS                       Status;
+  IA32_DESCRIPTOR                  IdtDescriptor;
+  UINTN                            IdtEntryCount;
+  EXCEPTION_HANDLER_TEMPLATE_MAP   TemplateMap;
+  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;
+
+  mReservedVectors = mReservedVectorsData;
+  SetMem ((VOID *) mReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
+  if (VectorInfo != NULL) {
+    Status = ReadAndVerifyVectorInfo (VectorInfo, mReservedVectors, CPU_EXCEPTION_NUM);
+    if (EFI_ERROR (Status)) {
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+  InitializeSpinLock (&mDisplayMessageSpinLock);
+
+  mExternalInterruptHandler = mExternalInterruptHandlerTable;
+  //
+  // Read IDT descriptor and calculate IDT size
+  //
+  AsmReadIdtr (&IdtDescriptor);
+  IdtEntryCount = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
+  if (IdtEntryCount > CPU_EXCEPTION_NUM) {
+    //
+    // CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
+    //
+    IdtEntryCount = CPU_EXCEPTION_NUM;
+  }
+
+  IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
+  AsmGetTemplateAddressMap (&TemplateMap);
+  ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
+  UpdateIdtTable (IdtTable, &TemplateMap, IdtEntryCount);
+  mEnabledInterruptNum = IdtEntryCount;
+  return EFI_SUCCESS;
+}
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+RegisterCpuInterruptHandlerWorker (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  )
+{
+  if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)mEnabledInterruptNum ||
+      mReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {
+    return EFI_UNSUPPORTED;
+  }
+
+  if (InterruptHandler == NULL && mExternalInterruptHandler[InterruptType] == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (InterruptHandler != NULL && mExternalInterruptHandler[InterruptType] != NULL) {
+    return EFI_ALREADY_STARTED;
+  }
+
+  mExternalInterruptHandler[InterruptType] = InterruptHandler;
+  return EFI_SUCCESS;
+}
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c	(revision 58464)
@@ -0,0 +1,202 @@
+/** @file
+  IA32 CPU Exception Handler functons.
+
+  Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuExceptionCommon.h"
+
+/**
+  Return address map of exception handler template so that C code can generate
+  exception tables.
+
+  @param IdtEntry          Pointer to IDT entry to be updated.
+  @param InterruptHandler  IDT handler value.
+
+**/
+VOID
+ArchUpdateIdtEntry (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry,
+  IN UINTN                           InterruptHandler
+  )
+{
+  IdtEntry->Bits.OffsetLow   = (UINT16)(UINTN)InterruptHandler;
+  IdtEntry->Bits.OffsetHigh  = (UINT16)((UINTN)InterruptHandler >> 16);
+  IdtEntry->Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+}
+
+/**
+  Read IDT handler value from IDT entry.
+
+  @param IdtEntry          Pointer to IDT entry to be read.
+
+**/
+UINTN
+ArchGetIdtHandler (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry
+  )
+{
+  return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16);
+}
+
+/**
+  Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+
+**/
+VOID
+ArchSaveExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  )
+{
+  IA32_EFLAGS32           Eflags;
+  //
+  // Save Exception context in global variable
+  //
+  mReservedVectors[ExceptionType].OldFlags      = SystemContext.SystemContextIa32->Eflags;
+  mReservedVectors[ExceptionType].OldCs         = SystemContext.SystemContextIa32->Cs;
+  mReservedVectors[ExceptionType].OldIp         = SystemContext.SystemContextIa32->Eip;
+  mReservedVectors[ExceptionType].ExceptionData = SystemContext.SystemContextIa32->ExceptionData;
+  //
+  // Clear IF flag to avoid old IDT handler enable interrupt by IRET
+  //
+  Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
+  Eflags.Bits.IF = 0; 
+  SystemContext.SystemContextIa32->Eflags = Eflags.UintN;
+  //
+  // Modify the EIP in stack, then old IDT handler will return to the stub code
+  //
+  SystemContext.SystemContextIa32->Eip    = (UINTN) mReservedVectors[ExceptionType].HookAfterStubHeaderCode;
+}
+
+/**
+  Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+ArchRestoreExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  )
+{
+  SystemContext.SystemContextIa32->Eflags        = mReservedVectors[ExceptionType].OldFlags;
+  SystemContext.SystemContextIa32->Cs            = mReservedVectors[ExceptionType].OldCs;
+  SystemContext.SystemContextIa32->Eip           = mReservedVectors[ExceptionType].OldIp;
+  SystemContext.SystemContextIa32->ExceptionData = mReservedVectors[ExceptionType].ExceptionData;
+}
+
+/**
+  Display CPU information.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpCpuContent (
+  IN EFI_EXCEPTION_TYPE   ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  UINTN                   ImageBase;
+  UINTN                   EntryPoint;
+
+  InternalPrintMessage (
+    "!!!! IA32 Exception Type - %08x    CPU Apic ID - %08x !!!!\n",
+    ExceptionType,
+    GetApicId ()
+    );
+  InternalPrintMessage (
+    "EIP  - %08x, CS  - %08x, EFLAGS - %08x\n",
+    SystemContext.SystemContextIa32->Eip,
+    SystemContext.SystemContextIa32->Cs,
+    SystemContext.SystemContextIa32->Eflags
+    );
+  if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
+    InternalPrintMessage (
+      "ExceptionData - %08x\n",
+      SystemContext.SystemContextIa32->ExceptionData
+      );
+  }
+  InternalPrintMessage (
+    "EAX  - %08x, ECX - %08x, EDX - %08x, EBX - %08x\n",
+    SystemContext.SystemContextIa32->Eax,
+    SystemContext.SystemContextIa32->Ecx,
+    SystemContext.SystemContextIa32->Edx,
+    SystemContext.SystemContextIa32->Ebx
+    );
+  InternalPrintMessage (
+    "ESP  - %08x, EBP - %08x, ESI - %08x, EDI - %08x\n",
+    SystemContext.SystemContextIa32->Esp,
+    SystemContext.SystemContextIa32->Ebp,
+    SystemContext.SystemContextIa32->Esi,
+    SystemContext.SystemContextIa32->Edi
+    );
+  InternalPrintMessage (
+    "DS   - %08x, ES  - %08x, FS  - %08x, GS  - %08x, SS - %08x\n",
+    SystemContext.SystemContextIa32->Ds,
+    SystemContext.SystemContextIa32->Es,
+    SystemContext.SystemContextIa32->Fs,
+    SystemContext.SystemContextIa32->Gs,
+    SystemContext.SystemContextIa32->Ss
+    );
+  InternalPrintMessage (
+    "CR0  - %08x, CR2 - %08x, CR3 - %08x, CR4 - %08x\n",
+    SystemContext.SystemContextIa32->Cr0,
+    SystemContext.SystemContextIa32->Cr2,
+    SystemContext.SystemContextIa32->Cr3,
+    SystemContext.SystemContextIa32->Cr4
+    );
+  InternalPrintMessage (
+    "DR0  - %08x, DR1 - %08x, DR2 - %08x, DR3 - %08x\n",
+    SystemContext.SystemContextIa32->Dr0,
+    SystemContext.SystemContextIa32->Dr1,
+    SystemContext.SystemContextIa32->Dr2,
+    SystemContext.SystemContextIa32->Dr3
+    );
+  InternalPrintMessage (
+    "DR6  - %08x, DR7 - %08x\n",
+    SystemContext.SystemContextIa32->Dr6,
+    SystemContext.SystemContextIa32->Dr7
+    );
+  InternalPrintMessage (
+    "GDTR - %08x %08x, IDTR - %08x %08x\n",
+    SystemContext.SystemContextIa32->Gdtr[0],
+    SystemContext.SystemContextIa32->Gdtr[1],
+    SystemContext.SystemContextIa32->Idtr[0],
+    SystemContext.SystemContextIa32->Idtr[1]
+    );
+  InternalPrintMessage (
+    "LDTR - %08x, TR - %08x\n",
+    SystemContext.SystemContextIa32->Ldtr,
+    SystemContext.SystemContextIa32->Tr
+    );
+  InternalPrintMessage (
+    "FXSAVE_STATE - %08x\n",
+    &SystemContext.SystemContextIa32->FxSaveState
+    );
+
+  //
+  // Find module image base and module entry point by RIP
+  //
+  ImageBase = FindModuleImageBase (SystemContext.SystemContextIa32->Eip, &EntryPoint);
+  if (ImageBase != 0) {
+    InternalPrintMessage (
+      " (ImageBase=%08x, EntryPoint=%08x) !!!!\n",
+      ImageBase,
+      EntryPoint
+      );
+  }
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h	(revision 58464)
@@ -0,0 +1,44 @@
+/** @file
+  Ia32 arch definition for CPU Exception Handler Library.
+
+  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ARCH_CPU_INTERRUPT_DEFS_H_
+#define _ARCH_CPU_INTERRUPT_DEFS_H_
+
+typedef struct {
+  EFI_SYSTEM_CONTEXT_IA32 SystemContext;
+  BOOLEAN                 ExceptionDataFlag;
+  UINTN                   OldIdtHandler;
+} EXCEPTION_HANDLER_CONTEXT;
+
+//
+// Register Structure Definitions
+//
+typedef struct {
+  EFI_STATUS_CODE_DATA      Header;
+  EFI_SYSTEM_CONTEXT_IA32   SystemContext;
+} CPU_STATUS_CODE_TEMPLATE;
+
+typedef struct {
+  SPIN_LOCK   SpinLock;
+  UINT32      ApicId;
+  UINT32      Attribute;
+  UINTN       ExceptonHandler;
+  UINTN       OldFlags;
+  UINTN       OldCs;
+  UINTN       OldIp;
+  UINTN       ExceptionData;
+  UINT8       HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
+} RESERVED_VECTORS_DATA;
+
+#endif
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S	(revision 58464)
@@ -0,0 +1,642 @@
+#------------------------------------------------------------------------------
+#*
+#*   Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+#*   This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*    ExceptionHandlerAsm.S
+#*
+#*   Abstract:
+#*
+#*     IA32 CPU Exception Handler
+#
+#------------------------------------------------------------------------------
+
+
+#.MMX
+#.XMM
+
+ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
+ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
+ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
+
+#EXTRN ASM_PFX(mErrorCodeFlag):DWORD           # Error code flags for exceptions
+#EXTRN ASM_PFX(mDoFarReturnFlag):DWORD         # Do far return flag
+
+.text
+
+#
+# exception handler stub table
+#
+Exception0Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   0
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception1Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   1
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception2Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   2
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception3Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   3
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception4Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   4
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception5Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   5
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception6Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   6
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception7Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   7
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception8Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   8
+    pushl   %eax
+     .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception9Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   9
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception10Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   10
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception11Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   11
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception12Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   12
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception13Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   13
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception14Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   14
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception15Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   15
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception16Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   16
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception17Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   17
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception18Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   18
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception19Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   19
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception20Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   20
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception21Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   21
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception22Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   22
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception23Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   23
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception24Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   24
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception25Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   25
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception26Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   26
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception27Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   27
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception28Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   28
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception29Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   29
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception30Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   30
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+Exception31Handle:
+    .byte   0x6a    #  push #VectorNum
+    .byte   31
+    pushl   %eax
+    .byte   0xB8
+    .long   ASM_PFX(CommonInterruptEntry)
+    jmp     *%eax
+
+HookAfterStubBegin:
+    .byte   0x6a       # push
+VectorNum:
+    .byte   0          # 0 will be fixed
+    pushl   %eax
+    .byte   0xB8       # movl    ASM_PFX(HookAfterStubHeaderEnd), %eax
+    .long   ASM_PFX(HookAfterStubHeaderEnd)
+    jmp     *%eax
+ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
+ASM_PFX(HookAfterStubHeaderEnd):
+    popl    %eax
+    subl    $8, %esp        # reserve room for filling exception data later
+    pushl   8(%esp)
+    xchgl   (%esp), %ecx    # get vector number
+    bt      %ecx, ASM_PFX(mErrorCodeFlag)
+    jnc     NoErrorData
+    pushl    (%esp)         # addition push if exception data needed
+NoErrorData:
+    xchg    (%esp), %ecx    # restore ecx
+    pushl   %eax
+
+#---------------------------------------;
+# CommonInterruptEntry                  ;
+#---------------------------------------;
+# The follow algorithm is used for the common interrupt routine.
+
+ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
+ASM_PFX(CommonInterruptEntry):
+    cli
+    popl    %eax
+    #
+    # All interrupt handlers are invoked through interrupt gates, so
+    # IF flag automatically cleared at the entry point
+    #
+
+    #
+    # Get vector number from top of stack
+    #
+    xchgl   (%esp), %ecx
+    andl    $0x0FF, %ecx      # Vector number should be less than 256
+    cmpl    $32, %ecx         # Intel reserved vector for exceptions?
+    jae     NoErrorCode
+    bt      %ecx, ASM_PFX(mErrorCodeFlag)
+    jc      HasErrorCode
+
+NoErrorCode:
+
+    #
+    # Stack:
+    # +---------------------+
+    # +    EFlags           +
+    # +---------------------+
+    # +    CS               +
+    # +---------------------+
+    # +    EIP              +
+    # +---------------------+
+    # +    ECX              +
+    # +---------------------+ <-- ESP
+    #
+    # Registers:
+    #   ECX - Vector Number
+    #
+
+    #
+    # Put Vector Number on stack
+    #
+    pushl   %ecx
+
+    #
+    # Put 0 (dummy) error code on stack, and restore ECX
+    #
+    xorl    %ecx, %ecx  # ECX = 0
+    xchgl   4(%esp), %ecx
+
+    jmp     ErrorCodeAndVectorOnStack
+
+HasErrorCode:
+
+    #
+    # Stack:
+    # +---------------------+
+    # +    EFlags           +
+    # +---------------------+
+    # +    CS               +
+    # +---------------------+
+    # +    EIP              +
+    # +---------------------+
+    # +    Error Code       +
+    # +---------------------+
+    # +    ECX              +
+    # +---------------------+ <-- ESP
+    #
+    # Registers:
+    #   ECX - Vector Number
+    #
+
+    #
+    # Put Vector Number on stack and restore ECX
+    #
+    xchgl   (%esp), %ecx 
+
+ErrorCodeAndVectorOnStack:
+    pushl   %ebp
+    movl    %esp, %ebp
+
+    #
+    # Stack:
+    # +---------------------+
+    # +    EFlags           +
+    # +---------------------+
+    # +    CS               +
+    # +---------------------+
+    # +    EIP              +
+    # +---------------------+
+    # +    Error Code       +
+    # +---------------------+
+    # +    Vector Number    +
+    # +---------------------+
+    # +    EBP              +
+    # +---------------------+ <-- EBP
+    #
+
+    #
+    # Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+    # is 16-byte aligned
+    #
+    andl    $0x0fffffff0, %esp 
+    subl    $12, %esp
+
+    subl    $8, %esp
+    pushl   $0         # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    pushl   $0         # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+       
+#; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+    pushl   %eax
+    pushl   %ecx
+    pushl   %edx
+    pushl   %ebx
+    leal    24(%ebp), %ecx
+    pushl   %ecx                          # ESP
+    pushl   (%ebp)              # EBP
+    pushl   %esi
+    pushl   %edi
+
+#; UINT32  Gs, Fs, Es, Ds, Cs, Ss;
+    movl    %ss, %eax
+    pushl   %eax
+    movzwl  16(%ebp), %eax 
+    pushl   %eax
+    movl    %ds, %eax
+    pushl   %eax
+    movl    %es, %eax
+    pushl   %eax
+    movl    %fs, %eax
+    pushl   %eax
+    movl    %gs, %eax
+    pushl   %eax
+
+#; UINT32  Eip;
+    movl    12(%ebp), %eax
+    pushl   %eax
+
+#; UINT32  Gdtr[2], Idtr[2];
+    subl    $8, %esp
+    sidt    (%esp)
+    movl    2(%esp), %eax
+    xchgl   (%esp), %eax
+    andl    $0x0FFFF, %eax 
+    movl    %eax, 4(%esp)
+
+    subl    $8, %esp
+    sgdt    (%esp)
+    movl    2(%esp), %eax
+    xchgl   (%esp), %eax
+    andl    $0x0FFFF, %eax 
+    movl    %eax, 4(%esp)
+
+#; UINT32  Ldtr, Tr;
+    xorl    %eax, %eax
+    str     %ax
+    pushl   %eax
+    sldt    %ax
+    pushl   %eax
+
+#; UINT32  EFlags;
+    movl    20(%ebp), %eax
+    pushl   %eax
+
+#; UINT32  Cr0, Cr1, Cr2, Cr3, Cr4;
+    movl    %cr4, %eax
+    orl     $0x208, %eax
+    movl    %eax, %cr4
+    pushl   %eax
+    movl    %cr3, %eax
+    pushl   %eax
+    movl    %cr2, %eax
+    pushl   %eax
+    xorl    %eax, %eax
+    pushl   %eax
+    movl    %cr0, %eax
+    pushl   %eax
+
+#; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+    movl    %dr7, %eax
+    pushl   %eax
+    movl    %dr6, %eax
+    pushl   %eax
+    movl    %dr3, %eax
+    pushl   %eax
+    movl    %dr2, %eax
+    pushl   %eax
+    movl    %dr1, %eax
+    pushl   %eax
+    movl    %dr0, %eax
+    pushl   %eax
+
+#; FX_SAVE_STATE_IA32 FxSaveState;
+    subl    $512, %esp
+    movl    %esp, %edi
+    .byte      0x0f, 0x0ae, 0x07 #fxsave [edi]
+
+#; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+    cld
+
+#; UINT32  ExceptionData;
+    pushl   8(%ebp)
+
+#; Prepare parameter and call
+    movl    %esp, %edx
+    pushl   %edx
+    movl    4(%ebp), %edx
+    pushl   %edx
+
+    #
+    # Call External Exception Handler
+    #
+    call    ASM_PFX(CommonExceptionHandler)
+    addl    $8, %esp
+
+    cli
+#; UINT32  ExceptionData;
+    addl    $4, %esp
+
+#; FX_SAVE_STATE_IA32 FxSaveState;
+    movl    %esp, %esi
+    .byte      0x0f, 0x0ae, 0x0e # fxrstor [esi]
+    addl    $512, %esp
+
+#; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+#; Skip restoration of DRx registers to support in-circuit emualators
+#; or debuggers set breakpoint in interrupt/exception context
+    addl    $24, %esp
+
+#; UINT32  Cr0, Cr1, Cr2, Cr3, Cr4;
+    popl    %eax
+    movl    %eax, %cr0
+    addl    $4, %esp    # not for Cr1
+    popl    %eax
+    movl    %eax, %cr2
+    popl    %eax
+    movl    %eax, %cr3
+    popl    %eax
+    movl    %eax, %cr4
+
+#; UINT32  EFlags;
+    popl    20(%ebp)
+
+#; UINT32  Ldtr, Tr;
+#; UINT32  Gdtr[2], Idtr[2];
+#; Best not let anyone mess with these particular registers...
+    addl    $24, %esp
+
+#; UINT32  Eip;
+    popl    12(%ebp)
+
+#; UINT32  Gs, Fs, Es, Ds, Cs, Ss;
+#; NOTE - modified segment registers could hang the debugger...  We
+#;        could attempt to insulate ourselves against this possibility,
+#;        but that poses risks as well.
+#;
+    popl    %gs
+    popl    %fs
+    popl    %es
+    popl    %ds
+    popl    16(%ebp)
+    popl    %ss
+
+#; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+    popl    %edi
+    popl    %esi
+    addl    $4, %esp   # not for ebp
+    addl    $4, %esp   # not for esp
+    popl    %ebx
+    popl    %edx
+    popl    %ecx
+    popl    %eax
+
+    popl    -8(%ebp)
+    popl    -4(%ebp)
+    movl    %ebp, %esp
+    popl    %ebp
+    addl    $8, %esp
+    cmpl    $0, -16(%esp)  # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    jz      DoReturn
+    cmpl    $1, -20(%esp)  # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+    jz      ErrorCode
+    jmp     *-16(%esp)
+ErrorCode:
+    subl    $4, %esp
+    jmp     *-12(%esp)
+
+DoReturn:
+    cmpl    $0, ASM_PFX(mDoFarReturnFlag)
+    jz      DoIret
+    pushl   8(%esp)       # save EFLAGS
+    addl    $16, %esp
+    pushl   -8(%esp)      # save CS in new location
+    pushl   -8(%esp)      # save EIP in new location
+    pushl   -8(%esp)      # save EFLAGS in new location
+    popfl                 # restore EFLAGS
+    lret                  # far return
+
+DoIret:
+    iretl
+
+
+#---------------------------------------;
+# _AsmGetTemplateAddressMap             ;
+#---------------------------------------;
+# 
+# Protocol prototype
+#   AsmGetTemplateAddressMap (
+#     EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+#   );
+#           
+# Routine Description:
+# 
+#  Return address map of interrupt handler template so that C code can generate
+#  interrupt table.
+# 
+# Arguments:
+# 
+# 
+# Returns: 
+# 
+#   Nothing
+#
+# 
+# Input:  [ebp][0]  = Original ebp
+#         [ebp][4]  = Return address
+#          
+# Output: Nothing
+#          
+# Destroys: Nothing
+#-----------------------------------------------------------------------------;
+#-------------------------------------------------------------------------------------
+#  AsmGetAddressMap (&AddressMap);
+#-------------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(AsmGetTemplateAddressMap)
+ASM_PFX(AsmGetTemplateAddressMap):
+
+        pushl       %ebp
+        movl        %esp,%ebp
+        pushal
+
+        movl        0x8(%ebp), %ebx
+        movl        $Exception0Handle, (%ebx)
+        movl        $(Exception1Handle - Exception0Handle), 0x4(%ebx)
+        movl        $(HookAfterStubBegin), 0x8(%ebx)
+
+        popal
+        popl        %ebp
+        ret
+#-------------------------------------------------------------------------------------
+#  AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
+#-------------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(AsmVectorNumFixup)
+ASM_PFX(AsmVectorNumFixup):
+        movl  8(%esp), %eax
+        movl  4(%esp), %ecx
+        movb  %al, (VectorNum - HookAfterStubBegin)(%ecx)
+        ret
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm	(revision 58464)
@@ -0,0 +1,445 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   ExceptionHandlerAsm.Asm
+;
+; Abstract:
+;
+;   IA32 CPU Exception Handler
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    .686
+    .model  flat,C
+
+;
+; CommonExceptionHandler()
+;
+CommonExceptionHandler             PROTO   C
+
+.data
+
+EXTRN mErrorCodeFlag:DWORD            ; Error code flags for exceptions
+EXTRN mDoFarReturnFlag:DWORD          ; Do far return flag
+
+.code
+
+ALIGN   8
+
+;
+; exception handler stub table
+;
+AsmIdtVectorBegin:
+REPEAT  32
+    db      6ah        ; push  #VectorNum
+    db      ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
+    push    eax
+    mov     eax, CommonInterruptEntry
+    jmp     eax
+ENDM
+AsmIdtVectorEnd:
+
+HookAfterStubBegin:
+    db      6ah        ; push
+VectorNum:
+    db      0          ; 0 will be fixed 
+    push    eax
+    mov     eax, HookAfterStubHeaderEnd
+    jmp     eax
+HookAfterStubHeaderEnd:
+    pop     eax
+    sub     esp, 8     ; reserve room for filling exception data later
+    push    [esp + 8]
+    xchg    ecx, [esp] ; get vector number
+    bt      mErrorCodeFlag, ecx
+    jnc     @F
+    push    [esp]      ; addition push if exception data needed
+@@:
+    xchg    ecx, [esp] ; restore ecx
+    push    eax
+
+;----------------------------------------------------------------------------;
+; CommonInterruptEntry                                                               ;
+;----------------------------------------------------------------------------;
+; The follow algorithm is used for the common interrupt routine.
+; Entry from each interrupt with a push eax and eax=interrupt number
+; Stack:
+; +---------------------+
+; +    EFlags           +
+; +---------------------+
+; +    CS               +
+; +---------------------+
+; +    EIP              +
+; +---------------------+
+; +    Error Code       +
+; +---------------------+
+; +    Vector Number    +
+; +---------------------+
+; +    EBP              +
+; +---------------------+ <-- EBP
+CommonInterruptEntry PROC PUBLIC
+    cli
+    pop    eax
+    ;
+    ; All interrupt handlers are invoked through interrupt gates, so
+    ; IF flag automatically cleared at the entry point
+    ;
+
+    ;
+    ; Get vector number from top of stack
+    ;
+    xchg    ecx, [esp]
+    and     ecx, 0FFh       ; Vector number should be less than 256
+    cmp     ecx, 32         ; Intel reserved vector for exceptions?
+    jae     NoErrorCode
+    bt      mErrorCodeFlag, ecx
+    jc      HasErrorCode
+
+NoErrorCode:
+
+    ;
+    ; Stack:
+    ; +---------------------+
+    ; +    EFlags           +
+    ; +---------------------+
+    ; +    CS               +
+    ; +---------------------+
+    ; +    EIP              +
+    ; +---------------------+
+    ; +    ECX              +
+    ; +---------------------+ <-- ESP
+    ;
+    ; Registers:
+    ;   ECX - Vector Number
+    ;
+
+    ;
+    ; Put Vector Number on stack
+    ;
+    push    ecx
+
+    ;
+    ; Put 0 (dummy) error code on stack, and restore ECX
+    ;
+    xor     ecx, ecx  ; ECX = 0
+    xchg    ecx, [esp+4]
+
+    jmp     ErrorCodeAndVectorOnStack
+
+HasErrorCode:
+
+    ;
+    ; Stack:
+    ; +---------------------+
+    ; +    EFlags           +
+    ; +---------------------+
+    ; +    CS               +
+    ; +---------------------+
+    ; +    EIP              +
+    ; +---------------------+
+    ; +    Error Code       +
+    ; +---------------------+
+    ; +    ECX              +
+    ; +---------------------+ <-- ESP
+    ;
+    ; Registers:
+    ;   ECX - Vector Number
+    ;
+
+    ;
+    ; Put Vector Number on stack and restore ECX
+    ;
+    xchg    ecx, [esp]
+
+ErrorCodeAndVectorOnStack:
+    push    ebp
+    mov     ebp, esp
+
+    ;
+    ; Stack:
+    ; +---------------------+
+    ; +    EFlags           +
+    ; +---------------------+
+    ; +    CS               +
+    ; +---------------------+
+    ; +    EIP              +
+    ; +---------------------+
+    ; +    Error Code       +
+    ; +---------------------+
+    ; +    Vector Number    +
+    ; +---------------------+
+    ; +    EBP              +
+    ; +---------------------+ <-- EBP
+    ;
+
+    ;
+    ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
+    ; is 16-byte aligned
+    ;
+    and     esp, 0fffffff0h
+    sub     esp, 12
+
+    sub     esp, 8
+    push    0            ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    push    0            ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+       
+;; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+    push    eax
+    push    ecx
+    push    edx
+    push    ebx
+    lea     ecx, [ebp + 6 * 4]
+    push    ecx                          ; ESP
+    push    dword ptr [ebp]              ; EBP
+    push    esi
+    push    edi
+
+;; UINT32  Gs, Fs, Es, Ds, Cs, Ss;
+    mov     eax, ss
+    push    eax
+    movzx   eax, word ptr [ebp + 4 * 4]
+    push    eax
+    mov     eax, ds
+    push    eax
+    mov     eax, es
+    push    eax
+    mov     eax, fs
+    push    eax
+    mov     eax, gs
+    push    eax
+
+;; UINT32  Eip;
+    mov     eax, [ebp + 3 * 4]
+    push    eax
+
+;; UINT32  Gdtr[2], Idtr[2];
+    sub     esp, 8
+    sidt    [esp]
+    mov     eax, [esp + 2]
+    xchg    eax, [esp]
+    and     eax, 0FFFFh
+    mov     [esp+4], eax
+
+    sub     esp, 8
+    sgdt    [esp]
+    mov     eax, [esp + 2]
+    xchg    eax, [esp]
+    and     eax, 0FFFFh
+    mov     [esp+4], eax
+
+;; UINT32  Ldtr, Tr;
+    xor     eax, eax
+    str     ax
+    push    eax
+    sldt    ax
+    push    eax
+
+;; UINT32  EFlags;
+    mov     eax, [ebp + 5 * 4]
+    push    eax
+
+;; UINT32  Cr0, Cr1, Cr2, Cr3, Cr4;
+    mov     eax, cr4
+    or      eax, 208h
+    mov     cr4, eax
+    push    eax
+    mov     eax, cr3
+    push    eax
+    mov     eax, cr2
+    push    eax
+    xor     eax, eax
+    push    eax
+    mov     eax, cr0
+    push    eax
+
+;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+    mov     eax, dr7
+    push    eax
+    mov     eax, dr6
+    push    eax
+    mov     eax, dr3
+    push    eax
+    mov     eax, dr2
+    push    eax
+    mov     eax, dr1
+    push    eax
+    mov     eax, dr0
+    push    eax
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+    sub     esp, 512
+    mov     edi, esp
+    db      0fh, 0aeh, 07h ;fxsave [edi]
+
+;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
+    cld
+
+;; UINT32  ExceptionData;
+    push    dword ptr [ebp + 2 * 4]
+
+;; Prepare parameter and call
+    mov     edx, esp
+    push    edx
+    mov     edx, dword ptr [ebp + 1 * 4]
+    push    edx
+
+    ;
+    ; Call External Exception Handler
+    ;
+    mov     eax, CommonExceptionHandler
+    call    eax
+    add     esp, 8
+
+    cli
+;; UINT32  ExceptionData;
+    add     esp, 4
+
+;; FX_SAVE_STATE_IA32 FxSaveState;
+    mov     esi, esp
+    db      0fh, 0aeh, 0eh ; fxrstor [esi]
+    add     esp, 512
+
+;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+;; Skip restoration of DRx registers to support in-circuit emualators
+;; or debuggers set breakpoint in interrupt/exception context
+    add     esp, 4 * 6
+
+;; UINT32  Cr0, Cr1, Cr2, Cr3, Cr4;
+    pop     eax
+    mov     cr0, eax
+    add     esp, 4    ; not for Cr1
+    pop     eax
+    mov     cr2, eax
+    pop     eax
+    mov     cr3, eax
+    pop     eax
+    mov     cr4, eax
+
+;; UINT32  EFlags;
+    pop     dword ptr [ebp + 5 * 4]
+
+;; UINT32  Ldtr, Tr;
+;; UINT32  Gdtr[2], Idtr[2];
+;; Best not let anyone mess with these particular registers...
+    add     esp, 24
+
+;; UINT32  Eip;
+    pop     dword ptr [ebp + 3 * 4]
+
+;; UINT32  Gs, Fs, Es, Ds, Cs, Ss;
+;; NOTE - modified segment registers could hang the debugger...  We
+;;        could attempt to insulate ourselves against this possibility,
+;;        but that poses risks as well.
+;;
+    pop     gs
+    pop     fs
+    pop     es
+    pop     ds
+    pop     dword ptr [ebp + 4 * 4]
+    pop     ss
+
+;; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
+    pop     edi
+    pop     esi
+    add     esp, 4   ; not for ebp
+    add     esp, 4   ; not for esp
+    pop     ebx
+    pop     edx
+    pop     ecx
+    pop     eax
+
+    pop     dword ptr [ebp - 8]
+    pop     dword ptr [ebp - 4]
+    mov     esp, ebp
+    pop     ebp
+    add     esp, 8
+    cmp     dword ptr [esp - 16], 0   ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    jz      DoReturn
+    cmp     dword ptr [esp - 20], 1   ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+    jz      ErrorCode
+    jmp     dword ptr [esp - 16]
+ErrorCode:
+    sub     esp, 4
+    jmp     dword ptr [esp - 12]
+
+DoReturn:    
+    cmp     mDoFarReturnFlag, 0   ; Check if need to do far return instead of IRET
+    jz      DoIret
+    push    [esp + 8]    ; save EFLAGS
+    add     esp, 16
+    push    [esp - 8]    ; save CS in new location
+    push    [esp - 8]    ; save EIP in new location
+    push    [esp - 8]    ; save EFLAGS in new location
+    popfd                ; restore EFLAGS
+    retf                 ; far return
+
+DoIret:
+    iretd
+
+CommonInterruptEntry ENDP
+
+;---------------------------------------;
+; _AsmGetTemplateAddressMap                  ;
+;----------------------------------------------------------------------------;
+; 
+; Protocol prototype
+;   AsmGetTemplateAddressMap (
+;     EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+;   );
+;           
+; Routine Description:
+; 
+;  Return address map of interrupt handler template so that C code can generate
+;  interrupt table.
+; 
+; Arguments:
+; 
+; 
+; Returns: 
+; 
+;   Nothing
+;
+; 
+; Input:  [ebp][0]  = Original ebp
+;         [ebp][4]  = Return address
+;          
+; Output: Nothing
+;           
+; Destroys: Nothing
+;-----------------------------------------------------------------------------;
+AsmGetTemplateAddressMap  proc near public
+    push    ebp                 ; C prolog
+    mov     ebp, esp
+    pushad
+
+    mov ebx, dword ptr [ebp + 08h]
+    mov dword ptr [ebx],      AsmIdtVectorBegin
+    mov dword ptr [ebx + 4h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
+    mov dword ptr [ebx + 8h], HookAfterStubBegin
+  
+    popad
+    pop     ebp
+    ret
+AsmGetTemplateAddressMap  ENDP
+
+;-------------------------------------------------------------------------------------
+;  AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
+;-------------------------------------------------------------------------------------
+AsmVectorNumFixup   proc near public
+    mov     eax, dword ptr [esp + 8]
+    mov     ecx, [esp + 4]
+    mov     [ecx + (VectorNum - HookAfterStubBegin)], al
+    ret
+AsmVectorNumFixup   ENDP
+END
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c	(revision 58464)
@@ -0,0 +1,183 @@
+/** @file
+  CPU exception handler library implemenation for SEC/PEIM modules.
+
+Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include "CpuExceptionCommon.h"
+
+//
+// Image Aglinment size for SEC/PEI phase
+//
+CONST UINTN    mImageAlignSize   = 4;
+CONST UINTN    mDoFarReturnFlag  = 0;
+
+/**
+  Common exception handler.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+EFIAPI
+CommonExceptionHandler (
+  IN EFI_EXCEPTION_TYPE   ExceptionType, 
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  //
+  // Display ExceptionType, CPU information and Image information
+  //  
+  DumpCpuContent (ExceptionType, SystemContext);
+  
+  //
+  // Enter a dead loop.
+  //
+  CpuDeadLoop ();
+}
+
+/**
+  Initializes all CPU exceptions entries and provides the default exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+  Note: Before invoking this API, caller must allocate memory for IDT table and load 
+        IDTR by AsmWriteIdtr().
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  EFI_STATUS                       Status;  
+  RESERVED_VECTORS_DATA            ReservedVectorData[CPU_EXCEPTION_NUM];
+  IA32_DESCRIPTOR                  IdtDescriptor;
+  UINTN                            IdtEntryCount;
+  UINT16                           CodeSegment;
+  EXCEPTION_HANDLER_TEMPLATE_MAP   TemplateMap;
+  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;
+  UINTN                            Index;
+  UINTN                            InterruptHandler;
+
+  if (VectorInfo != NULL) {
+    SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
+    Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM);
+    if (EFI_ERROR (Status)) {
+      return EFI_INVALID_PARAMETER;
+    }
+  }
+  //
+  // Read IDT descriptor and calculate IDT size
+  //
+  AsmReadIdtr (&IdtDescriptor);
+  IdtEntryCount = (IdtDescriptor.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR);
+  if (IdtEntryCount > CPU_EXCEPTION_NUM) {
+    //
+    // CPU exeption library only setup CPU_EXCEPTION_NUM exception handler at most
+    //
+    IdtEntryCount = CPU_EXCEPTION_NUM;
+  }
+  //
+  // Use current CS as the segment selector of interrupt gate in IDT
+  //
+  CodeSegment = AsmReadCs ();
+
+  AsmGetTemplateAddressMap (&TemplateMap);
+  IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
+  for (Index = 0; Index < IdtEntryCount; Index ++) {
+    IdtTable[Index].Bits.Selector = CodeSegment;
+    //
+    // Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK
+    // supported in this instance
+    //
+    if (VectorInfo != NULL) {
+      if (ReservedVectorData[Index].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {
+        continue;
+      }
+    }
+    //
+    // Update IDT entry
+    //
+    InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
+    ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
+  }
+  return EFI_SUCCESS;
+}
+
+/**
+  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
+                                with default interrupt/exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  This function registers and enables the handler specified by InterruptHandler for a processor 
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  The installed handler is called once for each processor interrupt or exception.
+  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+  InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  )
+{
+  return EFI_UNSUPPORTED;
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf	(revision 58464)
@@ -0,0 +1,57 @@
+## @file
+#  CPU Exception Handler library instance for SEC/PEI modules.
+#
+#  Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SecPeiCpuExceptionHandlerLib
+  MODULE_UNI_FILE                = SecPeiCpuExceptionHandlerLib.uni
+  FILE_GUID                      = CA4BBC99-DFC6-4234-B553-8B6586B7B113
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpuExceptionHandlerLib|SEC PEI_CORE PEIM
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Sources.Ia32]
+  Ia32/ExceptionHandlerAsm.asm
+  Ia32/ExceptionHandlerAsm.S   |GCC
+  Ia32/ArchExceptionHandler.c
+  Ia32/ArchInterruptDefs.h
+
+[Sources.X64]
+  X64/ExceptionHandlerAsm.asm
+  X64/ExceptionHandlerAsm.S   |GCC
+  X64/ArchExceptionHandler.c
+  X64/ArchInterruptDefs.h
+
+[Sources.common]
+  CpuExceptionCommon.h
+  CpuExceptionCommon.c
+  SecPeiCpuException.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  SerialPortLib
+  PrintLib
+  LocalApicLib
+  PeCoffGetEntryPointLib
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// CPU Exception Handler library instance for SEC/PEI modules.
+//
+// CPU Exception Handler library instance for SEC/PEI modules.
+//
+// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "CPU Exception Handler library instance for SEC/PEI modules."
+
+#string STR_MODULE_DESCRIPTION          #language en-US "CPU Exception Handler library instance for SEC/PEI modules."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf	(revision 58464)
@@ -0,0 +1,61 @@
+## @file
+#  CPU Exception Handler library instance for SMM modules.
+#
+#  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#  
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SmmCpuExceptionHandlerLib
+  MODULE_UNI_FILE                = SmmCpuExceptionHandlerLib.uni
+  FILE_GUID                      = 8D2C439B-3981-42ff-9CE5-1B50ECA502D6
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CpuExceptionHandlerLib|DXE_SMM_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Sources.Ia32]
+  Ia32/ExceptionHandlerAsm.asm
+  Ia32/ExceptionHandlerAsm.S   |GCC
+  Ia32/ArchExceptionHandler.c
+  Ia32/ArchInterruptDefs.h
+
+[Sources.X64]
+  X64/ExceptionHandlerAsm.asm
+  X64/ExceptionHandlerAsm.S     |GCC
+  X64/ArchExceptionHandler.c
+  X64/ArchInterruptDefs.h
+
+[Sources.common]
+  CpuExceptionCommon.h
+  CpuExceptionCommon.c
+  DxeSmmCpuException.c
+  SmmException.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  SerialPortLib
+  PrintLib
+  SynchronizationLib
+  LocalApicLib
+  PeCoffGetEntryPointLib
+  DebugLib
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// CPU Exception Handler library instance for SMM modules.
+//
+// CPU Exception Handler library instance for SMM modules.
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "CPU Exception Handler library instance for SMM modules."
+
+#string STR_MODULE_DESCRIPTION          #language en-US "CPU Exception Handler library instance for SMM modules."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c	(revision 58464)
@@ -0,0 +1,101 @@
+/** @file
+  CPU exception handler library implemenation for SMM modules.
+
+  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiSmm.h>
+#include "CpuExceptionCommon.h"
+
+CONST UINTN   mDoFarReturnFlag   = 1; 
+
+/**
+  Initializes all CPU exceptions entries and provides the default exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
+                                with default exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return InitializeCpuExceptionHandlersWorker (VectorInfo);
+}
+
+/**
+  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+  
+  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
+  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+  @param[in]  VectorInfo    Pointer to reserved vector list.
+  
+  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
+                                with default interrupt/exception handlers.
+  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+  @retval EFI_UNSUPPORTED       This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Registers a function to be called from the processor interrupt handler.
+
+  This function registers and enables the handler specified by InterruptHandler for a processor 
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  The installed handler is called once for each processor interrupt or exception.
+  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+  InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+  @param[in]  InterruptType     Defines which interrupt or exception to hook.
+  @param[in]  InterruptHandler  A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+                                when a processor interrupt occurs. If this parameter is NULL, then the handler
+                                will be uninstalled.
+
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was
+                                previously installed.
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+                                previously installed.
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported,
+                                or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+  IN EFI_EXCEPTION_TYPE            InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  )
+{
+  return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler);
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c	(revision 58464)
@@ -0,0 +1,233 @@
+/** @file
+  x64 CPU Exception Handler.
+
+  Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuExceptionCommon.h"
+
+/**
+  Return address map of exception handler template so that C code can generate
+  exception tables.
+
+  @param IdtEntry          Pointer to IDT entry to be updated.
+  @param InterruptHandler  IDT handler value.
+**/
+VOID
+ArchUpdateIdtEntry (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry,
+  IN UINTN                           InterruptHandler
+  )
+{
+  IdtEntry->Bits.OffsetLow   = (UINT16)(UINTN)InterruptHandler;
+  IdtEntry->Bits.OffsetHigh  = (UINT16)((UINTN)InterruptHandler >> 16);
+  IdtEntry->Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);	
+  IdtEntry->Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+}
+
+/**
+  Read IDT handler value from IDT entry.
+
+  @param IdtEntry          Pointer to IDT entry to be read.
+
+**/
+UINTN
+ArchGetIdtHandler (
+  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry
+  )
+{
+  return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh)  << 16) +
+                                    (((UINTN) IdtEntry->Bits.OffsetUpper) << 32);
+}
+
+/**
+  Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+ArchSaveExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  )
+{
+  IA32_EFLAGS32           Eflags;
+  //
+  // Save Exception context in global variable
+  //
+  mReservedVectors[ExceptionType].OldSs         = SystemContext.SystemContextX64->Ss;
+  mReservedVectors[ExceptionType].OldSp         = SystemContext.SystemContextX64->Rsp;
+  mReservedVectors[ExceptionType].OldFlags      = SystemContext.SystemContextX64->Rflags;
+  mReservedVectors[ExceptionType].OldCs         = SystemContext.SystemContextX64->Cs;
+  mReservedVectors[ExceptionType].OldIp         = SystemContext.SystemContextX64->Rip;
+  mReservedVectors[ExceptionType].ExceptionData = SystemContext.SystemContextX64->ExceptionData;
+  //
+  // Clear IF flag to avoid old IDT handler enable interrupt by IRET
+  //
+  Eflags.UintN = SystemContext.SystemContextX64->Rflags;
+  Eflags.Bits.IF = 0; 
+  SystemContext.SystemContextX64->Rflags = Eflags.UintN;
+  //
+  // Modify the EIP in stack, then old IDT handler will return to the stub code
+  //
+  SystemContext.SystemContextX64->Rip = (UINTN) mReservedVectors[ExceptionType].HookAfterStubHeaderCode;
+}
+
+/**
+  Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+ArchRestoreExceptionContext (
+  IN UINTN                ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext 
+  )
+{
+  SystemContext.SystemContextX64->Ss            = mReservedVectors[ExceptionType].OldSs;
+  SystemContext.SystemContextX64->Rsp           = mReservedVectors[ExceptionType].OldSp;
+  SystemContext.SystemContextX64->Rflags        = mReservedVectors[ExceptionType].OldFlags;
+  SystemContext.SystemContextX64->Cs            = mReservedVectors[ExceptionType].OldCs;
+  SystemContext.SystemContextX64->Rip           = mReservedVectors[ExceptionType].OldIp;
+  SystemContext.SystemContextX64->ExceptionData = mReservedVectors[ExceptionType].ExceptionData;
+}
+
+/**
+  Display CPU information.
+
+  @param ExceptionType  Exception type.
+  @param SystemContext  Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpCpuContent (
+  IN EFI_EXCEPTION_TYPE   ExceptionType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  UINTN                   ImageBase;
+  UINTN                   EntryPoint;
+
+  InternalPrintMessage (
+    "!!!! X64 Exception Type - %016lx     CPU Apic ID - %08x !!!!\n",
+    ExceptionType,
+    GetApicId ()
+    );
+  InternalPrintMessage (
+    "RIP  - %016lx, CS  - %016lx, RFLAGS - %016lx\n",
+    SystemContext.SystemContextX64->Rip,
+    SystemContext.SystemContextX64->Cs,
+    SystemContext.SystemContextX64->Rflags
+    );
+  if (mErrorCodeFlag & (1 << ExceptionType)) {
+    InternalPrintMessage (
+      "ExceptionData - %016lx\n",
+      SystemContext.SystemContextX64->ExceptionData
+      );
+  }
+  InternalPrintMessage (
+    "RAX  - %016lx, RCX - %016lx, RDX - %016lx\n",
+    SystemContext.SystemContextX64->Rax,
+    SystemContext.SystemContextX64->Rcx,
+    SystemContext.SystemContextX64->Rdx
+    );
+  InternalPrintMessage (
+    "RBX  - %016lx, RSP - %016lx, RBP - %016lx\n",
+    SystemContext.SystemContextX64->Rbx,
+    SystemContext.SystemContextX64->Rsp,
+    SystemContext.SystemContextX64->Rbp
+    );
+  InternalPrintMessage (
+    "RSI  - %016lx, RDI - %016lx\n",
+    SystemContext.SystemContextX64->Rsi,
+    SystemContext.SystemContextX64->Rdi
+    );
+  InternalPrintMessage (
+    "R8   - %016lx, R9  - %016lx, R10 - %016lx\n",
+    SystemContext.SystemContextX64->R8,
+    SystemContext.SystemContextX64->R9,
+    SystemContext.SystemContextX64->R10
+    );
+  InternalPrintMessage (
+    "R11  - %016lx, R12 - %016lx, R13 - %016lx\n",
+    SystemContext.SystemContextX64->R11,
+    SystemContext.SystemContextX64->R12,
+    SystemContext.SystemContextX64->R13
+    );
+  InternalPrintMessage (
+    "R14  - %016lx, R15 - %016lx\n",
+    SystemContext.SystemContextX64->R14,
+    SystemContext.SystemContextX64->R15
+    );
+  InternalPrintMessage (
+    "DS   - %016lx, ES  - %016lx, FS  - %016lx\n",
+    SystemContext.SystemContextX64->Ds,
+    SystemContext.SystemContextX64->Es,
+    SystemContext.SystemContextX64->Fs
+    );
+  InternalPrintMessage (
+    "GS   - %016lx, SS  - %016lx\n",
+    SystemContext.SystemContextX64->Gs,
+    SystemContext.SystemContextX64->Ss
+    );
+  InternalPrintMessage (
+    "CR0  - %016lx, CR2 - %016lx, CR3 - %016lx\n",
+    SystemContext.SystemContextX64->Cr0,
+    SystemContext.SystemContextX64->Cr2,
+    SystemContext.SystemContextX64->Cr3
+    );
+  InternalPrintMessage (
+    "CR4  - %016lx, CR8 - %016lx\n",
+    SystemContext.SystemContextX64->Cr4,
+    SystemContext.SystemContextX64->Cr8
+    );
+  InternalPrintMessage (
+    "DR0  - %016lx, DR1 - %016lx, DR2 - %016lx\n",
+    SystemContext.SystemContextX64->Dr0,
+    SystemContext.SystemContextX64->Dr1,
+    SystemContext.SystemContextX64->Dr2
+    );
+  InternalPrintMessage (
+    "DR3  - %016lx, DR6 - %016lx, DR7 - %016lx\n",
+    SystemContext.SystemContextX64->Dr3,
+    SystemContext.SystemContextX64->Dr6,
+    SystemContext.SystemContextX64->Dr7
+    );
+  InternalPrintMessage (
+    "GDTR - %016lx %016lx, LDTR - %016lx\n",
+    SystemContext.SystemContextX64->Gdtr[0],
+    SystemContext.SystemContextX64->Gdtr[1],
+    SystemContext.SystemContextX64->Ldtr
+    );
+  InternalPrintMessage (
+    "IDTR - %016lx %016lx,   TR - %016lx\n",
+    SystemContext.SystemContextX64->Idtr[0],
+    SystemContext.SystemContextX64->Idtr[1],
+    SystemContext.SystemContextX64->Tr
+    );
+	InternalPrintMessage (
+    "FXSAVE_STATE - %016lx\n",
+    &SystemContext.SystemContextX64->FxSaveState
+    );
+
+  //
+  // Find module image base and module entry point by RIP
+  //
+  ImageBase = FindModuleImageBase (SystemContext.SystemContextX64->Rip, &EntryPoint);
+  if (ImageBase != 0) {
+    InternalPrintMessage (
+      " (ImageBase=%016lx, EntryPoint=%016lx) !!!!\n",
+      ImageBase,
+      EntryPoint
+      );
+  }
+}
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h	(revision 58464)
@@ -0,0 +1,46 @@
+/** @file
+  X64 arch definition for CPU Exception Handler Library.
+
+  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ARCH_CPU_INTERRUPT_DEFS_H_
+#define _ARCH_CPU_INTERRUPT_DEFS_H_
+
+typedef struct {
+  EFI_SYSTEM_CONTEXT_X64  SystemContext;
+  BOOLEAN                 ExceptionDataFlag;
+  UINTN                   OldIdtHandler;
+} EXCEPTION_HANDLER_CONTEXT;
+
+//
+// Register Structure Definitions
+//
+typedef struct {
+  EFI_STATUS_CODE_DATA      Header;
+  EFI_SYSTEM_CONTEXT_X64    SystemContext;
+} CPU_STATUS_CODE_TEMPLATE;
+
+typedef struct {
+  SPIN_LOCK   SpinLock;
+  UINT32      ApicId;
+  UINT32      Attribute;
+  UINTN       ExceptonHandler;
+  UINTN       OldSs;
+  UINTN       OldSp;
+  UINTN       OldFlags;
+  UINTN       OldCs;
+  UINTN       OldIp;
+  UINTN       ExceptionData;
+  UINT8       HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
+} RESERVED_VECTORS_DATA;
+
+#endif
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.S
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.S	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.S	(revision 58464)
@@ -0,0 +1,433 @@
+#------------------------------------------------------------------------------ ;
+# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#   ExceptionHandlerAsm.S
+#
+# Abstract:
+#
+#   x64 CPU Exception Handler
+#
+# Notes:
+#
+#------------------------------------------------------------------------------
+
+
+
+ASM_GLOBAL ASM_PFX(CommonExceptionHandler)
+
+#EXTRN ASM_PFX(mErrorCodeFlag):DWORD    # Error code flags for exceptions
+#EXTRN ASM_PFX(mDoFarReturnFlag):QWORD  # Do far return flag
+.text
+
+#ifdef __APPLE__
+# macros are different between GNU and Xcode as. 
+.macro IDT_MACRO 
+  push     $0
+#else
+.macro IDT_MACRO arg
+  push    \arg
+#endif
+  jmp    ASM_PFX(CommonInterruptEntry)
+.endm
+
+AsmIdtVectorBegin:
+  IDT_MACRO $0
+  IDT_MACRO $1
+  IDT_MACRO $2
+  IDT_MACRO $3
+  IDT_MACRO $4
+  IDT_MACRO $5
+  IDT_MACRO $6
+  IDT_MACRO $7
+  IDT_MACRO $8
+  IDT_MACRO $9
+  IDT_MACRO $10
+  IDT_MACRO $11
+  IDT_MACRO $12
+  IDT_MACRO $13
+  IDT_MACRO $14
+  IDT_MACRO $15
+  IDT_MACRO $16
+  IDT_MACRO $17
+  IDT_MACRO $18
+  IDT_MACRO $19
+  IDT_MACRO $20
+  IDT_MACRO $21
+  IDT_MACRO $22
+  IDT_MACRO $23
+  IDT_MACRO $24
+  IDT_MACRO $25
+  IDT_MACRO $26
+  IDT_MACRO $27
+  IDT_MACRO $28
+  IDT_MACRO $29
+  IDT_MACRO $30
+  IDT_MACRO $31
+AsmIdtVectorEnd:
+
+HookAfterStubHeaderBegin:
+    .byte   0x6a      # push
+PatchVectorNum:
+    .byte   0         # 0 will be fixed 
+    .byte   0xe9      # jmp     ASM_PFX(HookAfterStubHeaderEnd)
+PatchFuncAddress:
+     .set   HOOK_ADDRESS, ASM_PFX(HookAfterStubHeaderEnd) - . - 4
+    .long   HOOK_ADDRESS  # will be fixed
+ASM_GLOBAL ASM_PFX(HookAfterStubHeaderEnd)
+ASM_PFX(HookAfterStubHeaderEnd):
+    pushq   %rax
+    movq    %rsp, %rax
+    andl    $0x0fffffff0, %esp  # make sure 16-byte aligned for exception context
+    subq    $0x18, %rsp         # reserve room for filling exception data later
+    pushq   %rcx
+    movq    8(%rax), %rcx
+    bt      %ecx, ASM_PFX(mErrorCodeFlag)(%rip)
+    jnc     NoErrorData
+    pushq   (%rsp)            # push additional rcx to make stack alignment
+NoErrorData:
+    xchgq   (%rsp), %rcx      # restore rcx, save Exception Number in stack
+    movq    (%rax), %rax      # restore rax
+
+#---------------------------------------;
+# CommonInterruptEntry                  ;
+#---------------------------------------;
+# The follow algorithm is used for the common interrupt routine.
+
+ASM_GLOBAL ASM_PFX(CommonInterruptEntry)
+ASM_PFX(CommonInterruptEntry):
+    cli
+    #
+    # All interrupt handlers are invoked through interrupt gates, so
+    # IF flag automatically cleared at the entry point
+    #
+    #
+    # Calculate vector number
+    #
+    xchgq   (%rsp), %rcx       # get the return address of call, actually, it is the address of vector number.
+    andq     $0x0FF, %rcx
+    cmp     $32, %ecx          # Intel reserved vector for exceptions?
+    jae     NoErrorCode
+    pushq   %rax
+    movl    ASM_PFX(mErrorCodeFlag)(%rip), %eax
+    bt      %ecx, %eax
+    popq    %rax
+    jc      CommonInterruptEntry_al_0000
+
+NoErrorCode:
+
+    #
+    # Push a dummy error code on the stack
+    # to maintain coherent stack map
+    #
+    pushq   (%rsp)
+    movq    $0, 8(%rsp)
+CommonInterruptEntry_al_0000:
+    pushq   %rbp
+    movq    %rsp, %rbp
+    pushq   $0          # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    pushq   $0          # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+
+    #
+    # Stack:
+    # +---------------------+ <-- 16-byte aligned ensured by processor
+    # +    Old SS           +
+    # +---------------------+
+    # +    Old RSP          +
+    # +---------------------+
+    # +    RFlags           +
+    # +---------------------+
+    # +    CS               +
+    # +---------------------+
+    # +    RIP              +
+    # +---------------------+
+    # +    Error Code       +
+    # +---------------------+
+    # + RCX / Vector Number +
+    # +---------------------+
+    # +    RBP              +
+    # +---------------------+ <-- RBP, 16-byte aligned
+    #
+
+
+    #
+    # Since here the stack pointer is 16-byte aligned, so
+    # EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
+    # is 16-byte aligned
+    #
+
+#; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
+#; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;
+    pushq    %r15
+    pushq    %r14
+    pushq    %r13
+    pushq    %r12
+    pushq    %r11
+    pushq    %r10
+    pushq    %r9
+    pushq    %r8
+    pushq    %rax
+    pushq    8(%rbp)   # RCX
+    pushq    %rdx
+    pushq    %rbx
+    pushq    48(%rbp)  # RSP
+    pushq    (%rbp)    # RBP
+    pushq    %rsi
+    pushq    %rdi
+
+#; UINT64  Gs, Fs, Es, Ds, Cs, Ss;  insure high 16 bits of each is zero
+    movzwq  56(%rbp), %rax
+    pushq   %rax                      # for ss
+    movzwq  32(%rbp), %rax
+    pushq   %rax                      # for cs
+    mov     %ds, %rax
+    pushq   %rax
+    mov     %es, %rax
+    pushq   %rax
+    mov     %fs, %rax
+    pushq   %rax
+    mov     %gs, %rax
+    pushq   %rax
+
+    movq    %rcx, 8(%rbp)                # save vector number
+
+#; UINT64  Rip;
+    pushq   24(%rbp)
+
+#; UINT64  Gdtr[2], Idtr[2];
+    xorq    %rax, %rax
+    pushq   %rax
+    pushq   %rax
+    sidt    (%rsp)
+    xchgq   2(%rsp), %rax
+    xchgq   (%rsp), %rax
+    xchgq   8(%rsp), %rax
+
+    xorq    %rax, %rax
+    pushq   %rax
+    pushq   %rax
+    sgdt    (%rsp)
+    xchgq   2(%rsp), %rax
+    xchgq   (%rsp), %rax
+    xchgq   8(%rsp), %rax
+
+#; UINT64  Ldtr, Tr;
+    xorq    %rax, %rax
+    str     %ax
+    pushq   %rax
+    sldt    %ax
+    pushq   %rax
+
+#; UINT64  RFlags;
+    pushq   40(%rbp)
+
+#; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
+    movq    %cr8, %rax
+    pushq   %rax
+    movq    %cr4, %rax
+    orq     $0x208, %rax 
+    movq    %rax, %cr4 
+    pushq   %rax
+    mov     %cr3, %rax 
+    pushq   %rax
+    mov     %cr2, %rax 
+    pushq   %rax
+    xorq    %rax, %rax
+    pushq   %rax
+    mov     %cr0, %rax 
+    pushq   %rax
+
+#; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+    movq    %dr7, %rax
+    pushq   %rax
+    movq    %dr6, %rax
+    pushq   %rax
+    movq    %dr3, %rax
+    pushq   %rax
+    movq    %dr2, %rax
+    pushq   %rax
+    movq    %dr1, %rax
+    pushq   %rax
+    movq    %dr0, %rax
+    pushq   %rax
+
+#; FX_SAVE_STATE_X64 FxSaveState;
+    subq    $512, %rsp
+    movq    %rsp, %rdi
+    .byte 0x0f, 0x0ae, 0x07 #fxsave [rdi]
+
+#; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
+    cld
+
+#; UINT32  ExceptionData;
+    pushq   16(%rbp)
+
+#; Prepare parameter and call
+    mov     8(%rbp), %rcx
+    mov     %rsp, %rdx
+    #
+    # Per X64 calling convention, allocate maximum parameter stack space
+    # and make sure RSP is 16-byte aligned
+    #
+    subq    $40, %rsp 
+    call    ASM_PFX(CommonExceptionHandler)
+    addq    $40, %rsp
+
+    cli
+#; UINT64  ExceptionData;
+    addq    $8, %rsp
+
+#; FX_SAVE_STATE_X64 FxSaveState;
+
+    movq    %rsp, %rsi
+    .byte   0x0f, 0x0ae, 0x0E # fxrstor [rsi]
+    addq    $512, %rsp
+
+#; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+#; Skip restoration of DRx registers to support in-circuit emualators
+#; or debuggers set breakpoint in interrupt/exception context
+    addq    $48, %rsp
+
+#; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
+    popq    %rax
+    movq    %rax, %cr0
+    addq    $8, %rsp   # not for Cr1
+    popq    %rax
+    movq    %rax, %cr2
+    popq    %rax
+    movq    %rax, %cr3
+    popq    %rax
+    movq    %rax, %cr4
+    popq    %rax
+    movq    %rax, %cr8
+
+#; UINT64  RFlags;
+    popq    40(%rbp)
+
+#; UINT64  Ldtr, Tr;
+#; UINT64  Gdtr[2], Idtr[2];
+#; Best not let anyone mess with these particular registers...
+    addq    $48, %rsp
+
+#; UINT64  Rip;
+    popq    24(%rbp)
+
+#; UINT64  Gs, Fs, Es, Ds, Cs, Ss;
+    popq    %rax
+    # mov   %rax, %gs ; not for gs
+    popq    %rax
+    # mov   %rax, %fs ; not for fs
+    # (X64 will not use fs and gs, so we do not restore it)
+    popq    %rax
+    mov     %rax, %es
+    popq    %rax
+    mov     %rax, %ds
+    popq    32(%rbp)  # for cs
+    popq    56(%rbp)  # for ss
+
+#; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
+#; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;
+    popq    %rdi
+    popq    %rsi
+    addq    $8, %rsp              # not for rbp
+    popq    48(%rbp)              # for rsp
+    popq    %rbx
+    popq    %rdx
+    popq    %rcx
+    popq    %rax
+    popq    %r8
+    popq    %r9
+    popq    %r10
+    popq    %r11
+    popq    %r12
+    popq    %r13
+    popq    %r14
+    popq    %r15
+
+    movq    %rbp, %rsp
+    popq    %rbp
+    addq    $16, %rsp
+    cmpq    $0, -32(%rsp)      # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    jz      DoReturn           # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+    cmpb    $1, -40(%rsp)
+    jz      ErrorCode
+    jmp     *-32(%rsp)
+ErrorCode:
+    subq    $8, %rsp
+    jmp     *-24(%rsp)
+
+DoReturn:
+    pushq   %rax
+    movq    ASM_PFX(mDoFarReturnFlag)(%rip), %rax
+    cmpq    $0, %rax          # Check if need to do far return instead of IRET
+    popq    %rax
+    jz      DoIret
+    pushq   %rax
+    movq    %rsp, %rax        # save old RSP to rax
+    movq    0x20(%rsp), %rsp
+    pushq   0x10(%rax)        # save CS in new location
+    pushq   0x8(%rax)         # save EIP in new location
+    pushq   0x18(%rax)        # save EFLAGS in new location
+    movq    (%rax), %rax      # restore rax
+    popfq                     # restore EFLAGS
+    lretq                     # far return
+DoIret:
+    iretq
+
+
+#-------------------------------------------------------------------------------------
+#  AsmGetTemplateAddressMap (&AddressMap);
+#-------------------------------------------------------------------------------------
+# comments here for definition of address map
+ASM_GLOBAL ASM_PFX(AsmGetTemplateAddressMap)
+ASM_PFX(AsmGetTemplateAddressMap):
+    pushq     %rbp
+    movq      %rsp, %rbp
+
+    leaq         AsmIdtVectorBegin(%rip), %rax
+    movq         %rax, (%rcx)
+    .set         ENTRY_SIZE, ASM_PFX(HookAfterStubHeaderEnd) - HookAfterStubHeaderBegin
+    movq         $(ENTRY_SIZE), 0x08(%rcx)
+    leaq         HookAfterStubHeaderBegin(%rip), %rax
+    movq         %rax, 0x10(%rcx)
+
+    popq      %rbp
+    ret
+
+#-------------------------------------------------------------------------------------
+# VOID
+# EFIAPI
+# AsmVectorNumFixup (
+#   IN VOID    *NewVectorAddr,  // RCX
+#   IN UINT8   VectorNum        // RDX
+#   IN VOID    *OldVectorAddr,  // R8
+#  );
+#-------------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(AsmVectorNumFixup)
+ASM_PFX(AsmVectorNumFixup):
+    pushq     %rbp
+    movq      %rsp, %rbp
+
+# Patch vector #
+    movb      %dl, (PatchVectorNum - HookAfterStubHeaderBegin)(%rcx)
+
+# Patch Function address
+    subq      %rcx, %r8     # Calculate the offset value
+    movl      (PatchFuncAddress - HookAfterStubHeaderBegin)(%rcx), %eax
+    addq      %r8, %rax
+    movl      %eax, (PatchFuncAddress - HookAfterStubHeaderBegin)(%rcx)
+
+    popq      %rbp
+    ret
+
+#END
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.asm	(revision 58464)
@@ -0,0 +1,389 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   ExceptionHandlerAsm.Asm
+;
+; Abstract:
+;
+;   x64 CPU Exception Handler
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+;
+; CommonExceptionHandler()
+;
+externdef CommonExceptionHandler:near
+
+EXTRN mErrorCodeFlag:DWORD    ; Error code flags for exceptions
+EXTRN mDoFarReturnFlag:QWORD  ; Do far return flag
+
+data SEGMENT
+
+.code
+
+ALIGN   8
+
+AsmIdtVectorBegin:
+REPEAT  32
+    db      6ah        ; push  #VectorNum
+    db      ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
+    push    rax
+    mov     rax, CommonInterruptEntry
+    jmp     rax
+ENDM
+AsmIdtVectorEnd:
+
+HookAfterStubHeaderBegin:
+    db      6ah        ; push
+@VectorNum:
+    db      0          ; 0 will be fixed 
+    push    rax
+    mov     rax, HookAfterStubHeaderEnd
+    jmp     rax
+HookAfterStubHeaderEnd:
+    mov     rax, rsp
+    and     sp,  0fff0h        ; make sure 16-byte aligned for exception context
+    sub     rsp, 18h           ; reserve room for filling exception data later
+    push    rcx
+    mov     rcx, [rax + 8]
+    bt      mErrorCodeFlag, ecx
+    jnc     @F
+    push    [rsp]             ; push additional rcx to make stack alignment
+@@:
+    xchg    rcx, [rsp]        ; restore rcx, save Exception Number in stack
+    push    [rax]             ; push rax into stack to keep code consistence
+
+;---------------------------------------;
+; CommonInterruptEntry                  ;
+;---------------------------------------;
+; The follow algorithm is used for the common interrupt routine.
+; Entry from each interrupt with a push eax and eax=interrupt number
+; Stack frame would be as follows as specified in IA32 manuals:
+;
+; +---------------------+ <-- 16-byte aligned ensured by processor
+; +    Old SS           +
+; +---------------------+
+; +    Old RSP          +
+; +---------------------+
+; +    RFlags           +
+; +---------------------+
+; +    CS               +
+; +---------------------+
+; +    RIP              +
+; +---------------------+
+; +    Error Code       +
+; +---------------------+
+; +   Vector Number     +
+; +---------------------+
+; +    RBP              +
+; +---------------------+ <-- RBP, 16-byte aligned
+; The follow algorithm is used for the common interrupt routine.
+CommonInterruptEntry PROC PUBLIC  
+    cli
+    pop     rax
+    ;
+    ; All interrupt handlers are invoked through interrupt gates, so
+    ; IF flag automatically cleared at the entry point
+    ;
+    xchg    rcx, [rsp]      ; Save rcx into stack and save vector number into rcx
+    and     rcx, 0FFh
+    cmp     ecx, 32         ; Intel reserved vector for exceptions?
+    jae     NoErrorCode
+    bt      mErrorCodeFlag, ecx
+    jc      @F
+
+NoErrorCode:
+
+    ;
+    ; Push a dummy error code on the stack
+    ; to maintain coherent stack map
+    ;
+    push    [rsp]
+    mov     qword ptr [rsp + 8], 0
+@@:       
+    push    rbp
+    mov     rbp, rsp
+    push    0             ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    push    0             ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+
+    ;
+    ; Stack:
+    ; +---------------------+ <-- 16-byte aligned ensured by processor
+    ; +    Old SS           +
+    ; +---------------------+
+    ; +    Old RSP          +
+    ; +---------------------+
+    ; +    RFlags           +
+    ; +---------------------+
+    ; +    CS               +
+    ; +---------------------+
+    ; +    RIP              +
+    ; +---------------------+
+    ; +    Error Code       +
+    ; +---------------------+
+    ; + RCX / Vector Number +
+    ; +---------------------+
+    ; +    RBP              +
+    ; +---------------------+ <-- RBP, 16-byte aligned
+    ;
+
+
+    ;
+    ; Since here the stack pointer is 16-byte aligned, so
+    ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
+    ; is 16-byte aligned
+    ;
+
+;; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
+;; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;
+    push r15
+    push r14
+    push r13
+    push r12
+    push r11
+    push r10
+    push r9
+    push r8
+    push rax
+    push qword ptr [rbp + 8]   ; RCX
+    push rdx
+    push rbx
+    push qword ptr [rbp + 48]  ; RSP
+    push qword ptr [rbp]       ; RBP
+    push rsi
+    push rdi
+
+;; UINT64  Gs, Fs, Es, Ds, Cs, Ss;  insure high 16 bits of each is zero
+    movzx   rax, word ptr [rbp + 56]
+    push    rax                      ; for ss
+    movzx   rax, word ptr [rbp + 32]
+    push    rax                      ; for cs
+    mov     rax, ds
+    push    rax
+    mov     rax, es
+    push    rax
+    mov     rax, fs
+    push    rax
+    mov     rax, gs
+    push    rax
+
+    mov     [rbp + 8], rcx               ; save vector number
+
+;; UINT64  Rip;
+    push    qword ptr [rbp + 24]
+
+;; UINT64  Gdtr[2], Idtr[2];
+    xor     rax, rax
+    push    rax
+    push    rax
+    sidt    [rsp]
+    xchg    rax, [rsp + 2]
+    xchg    rax, [rsp]
+    xchg    rax, [rsp + 8]
+
+    xor     rax, rax
+    push    rax
+    push    rax
+    sgdt    [rsp]
+    xchg    rax, [rsp + 2]
+    xchg    rax, [rsp]
+    xchg    rax, [rsp + 8]
+
+;; UINT64  Ldtr, Tr;
+    xor     rax, rax
+    str     ax
+    push    rax
+    sldt    ax
+    push    rax
+
+;; UINT64  RFlags;
+    push    qword ptr [rbp + 40]
+
+;; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
+    mov     rax, cr8
+    push    rax
+    mov     rax, cr4
+    or      rax, 208h
+    mov     cr4, rax
+    push    rax
+    mov     rax, cr3
+    push    rax
+    mov     rax, cr2
+    push    rax
+    xor     rax, rax
+    push    rax
+    mov     rax, cr0
+    push    rax
+
+;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+    mov     rax, dr7
+    push    rax
+    mov     rax, dr6
+    push    rax
+    mov     rax, dr3
+    push    rax
+    mov     rax, dr2
+    push    rax
+    mov     rax, dr1
+    push    rax
+    mov     rax, dr0
+    push    rax
+
+;; FX_SAVE_STATE_X64 FxSaveState;
+    sub rsp, 512
+    mov rdi, rsp
+    db 0fh, 0aeh, 07h ;fxsave [rdi]
+
+;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
+    cld
+
+;; UINT32  ExceptionData;
+    push    qword ptr [rbp + 16]
+
+;; Prepare parameter and call
+    mov     rcx, [rbp + 8]
+    mov     rdx, rsp
+    ;
+    ; Per X64 calling convention, allocate maximum parameter stack space
+    ; and make sure RSP is 16-byte aligned
+    ;
+    sub     rsp, 4 * 8 + 8
+    mov     rax, CommonExceptionHandler
+    call    rax
+    add     rsp, 4 * 8 + 8
+
+    cli
+;; UINT64  ExceptionData;
+    add     rsp, 8
+
+;; FX_SAVE_STATE_X64 FxSaveState;
+
+    mov rsi, rsp
+    db 0fh, 0aeh, 0Eh ; fxrstor [rsi]
+    add rsp, 512
+
+;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
+;; Skip restoration of DRx registers to support in-circuit emualators
+;; or debuggers set breakpoint in interrupt/exception context
+    add     rsp, 8 * 6
+
+;; UINT64  Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
+    pop     rax
+    mov     cr0, rax
+    add     rsp, 8   ; not for Cr1
+    pop     rax
+    mov     cr2, rax
+    pop     rax
+    mov     cr3, rax
+    pop     rax
+    mov     cr4, rax
+    pop     rax
+    mov     cr8, rax
+
+;; UINT64  RFlags;
+    pop     qword ptr [rbp + 40]
+
+;; UINT64  Ldtr, Tr;
+;; UINT64  Gdtr[2], Idtr[2];
+;; Best not let anyone mess with these particular registers...
+    add     rsp, 48
+
+;; UINT64  Rip;
+    pop     qword ptr [rbp + 24]
+
+;; UINT64  Gs, Fs, Es, Ds, Cs, Ss;
+    pop     rax
+    ; mov     gs, rax ; not for gs
+    pop     rax
+    ; mov     fs, rax ; not for fs
+    ; (X64 will not use fs and gs, so we do not restore it)
+    pop     rax
+    mov     es, rax
+    pop     rax
+    mov     ds, rax
+    pop     qword ptr [rbp + 32]  ; for cs
+    pop     qword ptr [rbp + 56]  ; for ss
+
+;; UINT64  Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
+;; UINT64  R8, R9, R10, R11, R12, R13, R14, R15;
+    pop     rdi
+    pop     rsi
+    add     rsp, 8               ; not for rbp
+    pop     qword ptr [rbp + 48] ; for rsp
+    pop     rbx
+    pop     rdx
+    pop     rcx
+    pop     rax
+    pop     r8
+    pop     r9
+    pop     r10
+    pop     r11
+    pop     r12
+    pop     r13
+    pop     r14
+    pop     r15
+
+    mov     rsp, rbp
+    pop     rbp
+    add     rsp, 16
+    cmp     qword ptr [rsp - 32], 0  ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
+    jz      DoReturn
+    cmp     qword ptr [rsp - 40], 1  ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
+    jz      ErrorCode
+    jmp     qword ptr [rsp - 32]
+ErrorCode:
+    sub     rsp, 8
+    jmp     qword ptr [rsp - 24]
+
+DoReturn:
+    cmp     mDoFarReturnFlag, 0   ; Check if need to do far return instead of IRET
+    jz      DoIret
+    push    rax
+    mov     rax, rsp          ; save old RSP to rax
+    mov     rsp, [rsp + 20h]   
+    push    [rax + 10h]       ; save CS in new location
+    push    [rax + 8h]        ; save EIP in new location
+    push    [rax + 18h]       ; save EFLAGS in new location
+    mov     rax, [rax]        ; restore rax
+    popfq                     ; restore EFLAGS
+    DB      48h               ; prefix to composite "retq" with next "retf"
+    retf                      ; far return
+DoIret:
+    iretq
+
+CommonInterruptEntry ENDP
+
+;-------------------------------------------------------------------------------------
+;  GetTemplateAddressMap (&AddressMap);
+;-------------------------------------------------------------------------------------
+; comments here for definition of address map
+AsmGetTemplateAddressMap   PROC
+    mov     rax, offset AsmIdtVectorBegin
+    mov     qword ptr [rcx], rax
+    mov     qword ptr [rcx + 8h],  (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
+    mov     rax, offset HookAfterStubHeaderBegin
+    mov     qword ptr [rcx + 10h], rax
+    ret
+AsmGetTemplateAddressMap   ENDP
+
+;-------------------------------------------------------------------------------------
+;  AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
+;-------------------------------------------------------------------------------------
+AsmVectorNumFixup   PROC
+    mov     rax, rdx
+    mov     [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al
+    ret
+AsmVectorNumFixup   ENDP
+
+END
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/MtrrLib/MtrrLib.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/MtrrLib/MtrrLib.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/MtrrLib/MtrrLib.uni	(revision 58464)
@@ -0,0 +1,22 @@
+﻿// /** @file
+// MTRR library provides APIs for MTRR operation.
+//
+// MTRR library provides APIs for MTRR operation.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "MTRR library provides APIs for MTRR operation"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "MTRR library provides APIs for MTRR operation."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.uni	(revision 58464)
@@ -0,0 +1,31 @@
+﻿// /** @file
+// Instance of Timer Library only using CPU resources.
+//
+// Timer Library that only uses CPU resources to provide calibrated delays
+// on IA-32, x64, and IPF.
+// Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib
+// in their initialization without any issues. They only have to be careful in
+// the implementation of runtime services and SMI handlers.
+// Because CPU Local APIC and ITC could be programmed by OS, it cannot be
+// used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM
+// drivers and runtime drivers.
+// 
+// This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in
+// that it uses the local APIC library so that it supports x2APIC mode.
+//
+// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Instance of Timer Library only using CPU resources"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Timer Library that only uses CPU resources to provide calibrated delays on IA-32, x64, and IPF. Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib in their initialization without any issues. They only have to be careful in the implementation of runtime services and SMI handlers. Because CPU Local APIC and ITC could be programmed by OS, it cannot be used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM drivers and runtime drivers. This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in that it uses the local APIC library so that it supports x2APIC mode."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/License.txt
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/License.txt	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/License.txt	(revision 58464)
@@ -0,0 +1,25 @@
+Copyright (c) 2012, Intel Corporation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVector.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVector.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVector.uni	(revision 58464)
@@ -0,0 +1,21 @@
+﻿// /** @file
+// Reset Vector
+//
+// This VTF requires build time fixups in order to find the SEC entry point.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Reset Vector"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "This VTF requires build time fixups in order to find the SEC entry point"
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVectorExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVectorExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/ResetVectorExtra.uni	(revision 58464)
@@ -0,0 +1,17 @@
+﻿// /** @file
+// ResetVector Localized Strings and Content
+//
+// Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME #language en-US "ResetVector module"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf	(revision 58464)
@@ -0,0 +1,38 @@
+## @file
+#  Reset Vector
+#  
+#  This VTF requires build time fixups in order to find the SEC entry point.
+#
+#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ResetVector
+  FILE_GUID                      = 1BA0062E-C779-4582-8566-336AE8F78F09
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.1
+  MODULE_UNI_FILE                = ResetVector.uni
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Sources]
+  Vtf.nasmb
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  ResetVectorExtra.uni
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb	(revision 58464)
@@ -0,0 +1,60 @@
+;------------------------------------------------------------------------------
+; @file
+; First code exectuted by processor after resetting.
+;
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+BITS    16
+
+ALIGN   16                      ; 0xffffffd0
+
+applicationProcessorEntryPoint:
+;
+; Application Processors entry point
+;
+; GenFv generates code aligned on a 4k boundary which will jump to this
+; location.  (0xffffffd0)  This allows the Local APIC Startup IPI to be
+; used to wake up the application processors.
+;
+    jmp     short resetVector
+
+ALIGN   16                      ; 0xffffffe0
+
+peiCoreEntryPoint:
+;
+; PEI Core entry point
+;
+; GenFv fills the address of the PEI Core into this location
+;
+    DD      0x12345678
+
+ALIGN   16                      ; 0xfffffff0
+
+resetVector:
+;
+; Reset Vector
+;
+; This is where the processor will begin execution
+;
+    nop
+    nop
+    jmp     near $
+
+ALIGN   8
+
+ApStartupSegment:
+    DD      0x12345678
+
+BootFvBaseAddress:
+    DD      0x12345678
+
+ALIGN   16                      ; 0x100000000
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.uni	(revision 58464)
@@ -0,0 +1,21 @@
+﻿// /** @file
+// Reset Vector binary
+//
+// Reset Vector binary
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Reset Vector binary"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Reset Vector binary"
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVectorExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVectorExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVectorExtra.uni	(revision 58464)
@@ -0,0 +1,17 @@
+﻿// /** @file
+// ResetVector Localized Strings and Content
+//
+// Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME #language en-US "ResetVector module"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm	(revision 58464)
@@ -0,0 +1,30 @@
+;------------------------------------------------------------------------------
+; @file
+; Sets the CR3 register for 64-bit paging
+;
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+BITS    32
+
+;
+; Modified:  EAX
+;
+SetCr3ForPageTables64:
+
+    ;
+    ; These pages are built into the ROM image in X64/PageTables.asm
+    ;
+    mov     eax, ADDR_OF(TopLevelPageDirectory)
+    mov     cr3, eax
+
+    OneTimeCallRet SetCr3ForPageTables64
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni	(revision 58464)
@@ -0,0 +1,21 @@
+﻿// /** @file
+// Reset Vector
+//
+// Reset Vector
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Reset Vector"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Reset Vector"
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni	(revision 58464)
@@ -0,0 +1,17 @@
+﻿// /** @file
+// ResetVector Localized Strings and Content
+//
+// Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME #language en-US "ResetVector module"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf	(revision 58464)
@@ -0,0 +1,36 @@
+## @file
+#  Reset Vector
+#
+#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ResetVector
+  FILE_GUID                      = 1BA0062E-C779-4582-8566-336AE8F78F09
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.1
+  MODULE_UNI_FILE                = ResetVector.uni
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+[Sources]
+  Vtf0.nasmb
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  ResetVectorExtra.uni
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb	(revision 58464)
@@ -0,0 +1,70 @@
+;------------------------------------------------------------------------------
+; @file
+; This file includes all other code files to assemble the reset vector code
+;
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+;
+; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include
+; Base.h to use the C pre-processor to determine the architecture.
+;
+%ifndef ARCH_IA32
+  %ifndef ARCH_X64
+    #include <Base.h>
+    #if defined (MDE_CPU_IA32)
+      %define ARCH_IA32
+    #elif defined (MDE_CPU_X64)
+      %define ARCH_X64
+    #endif
+  %endif
+%endif
+
+%ifdef ARCH_IA32
+  %ifdef ARCH_X64
+    %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."
+  %endif
+%elifdef ARCH_X64
+%else
+  %error "Either ARCH_IA32 or ARCH_X64 must be defined."
+%endif
+
+%include "CommonMacros.inc"
+
+%include "PostCodes.inc"
+
+%ifdef ARCH_X64
+%include "X64/PageTables.asm"
+%endif
+
+%ifdef DEBUG_PORT80
+  %include "Port80Debug.asm"
+%elifdef DEBUG_SERIAL
+  %include "SerialDebug.asm"
+%else
+  %include "DebugDisabled.asm"
+%endif
+
+%include "Ia32/SearchForBfvBase.asm"
+%include "Ia32/SearchForSecEntry.asm"
+
+%ifdef ARCH_X64
+%include "Ia32/Flat32ToFlat64.asm"
+%include "Ia32/PageTables64.asm"
+%endif
+
+%include "Ia16/Real16ToFlat32.asm"
+%include "Ia16/Init16.asm"
+
+%include "Main.asm"
+
+%include "Ia16/ResetVectorVtf0.asm"
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm	(revision 58464)
@@ -0,0 +1,78 @@
+;------------------------------------------------------------------------------
+; @file
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
+;
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+BITS    64
+
+%define ALIGN_TOP_TO_4K_FOR_PAGING
+
+%define PAGE_PRESENT            0x01
+%define PAGE_READ_WRITE         0x02
+%define PAGE_USER_SUPERVISOR    0x04
+%define PAGE_WRITE_THROUGH      0x08
+%define PAGE_CACHE_DISABLE     0x010
+%define PAGE_ACCESSED          0x020
+%define PAGE_DIRTY             0x040
+%define PAGE_PAT               0x080
+%define PAGE_GLOBAL           0x0100
+%define PAGE_2M_MBO            0x080
+%define PAGE_2M_PAT          0x01000
+
+%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
+                          PAGE_ACCESSED + \
+                          PAGE_DIRTY + \
+                          PAGE_READ_WRITE + \
+                          PAGE_PRESENT)
+
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+                       PAGE_READ_WRITE + \
+                       PAGE_PRESENT)
+
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+                     PAGE_PDP_ATTR)
+%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
+
+TopLevelPageDirectory:
+
+    ;
+    ; Top level Page Directory Pointers (1 * 512GB entry)
+    ;
+    DQ      PDP(0x1000)
+
+
+    ;
+    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
+    ;
+    TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+
+    DQ      PDP(0x2000)
+    DQ      PDP(0x3000)
+    DQ      PDP(0x4000)
+    DQ      PDP(0x5000)
+
+    ;
+    ; Page Table Entries (2048 * 2MB entries => 4GB)
+    ;
+    TIMES 0x2000-PGTBLS_OFFSET($) DB 0
+
+%assign i 0
+%rep    0x800
+    DQ      PTE_2MB(i)
+    %assign i i+1
+%endrep
+
+EndOfPageTables:
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkg.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkg.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkg.uni	(revision 58464)
@@ -0,0 +1,34 @@
+﻿// /** @file
+// This Package provides UEFI compatible CPU modules and libraries.
+//
+// This Package provides UEFI compatible CPU modules and libraries.
+//
+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials are licensed and made available under
+// the terms and conditions of the BSD License which accompanies this distribution.
+// The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT            #language en-US "Provides UEFI compatible CPU modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION         #language en-US "This Package provides UEFI compatible CPU modules and libraries."
+
+
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuLocalApicBaseAddress_PROMPT  #language en-US "Configure base address of CPU Local APIC"
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuLocalApicBaseAddress_HELP  #language en-US "This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_ERR_80000001 #language en-US "Invalid value provided."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuInitIpiDelayInMicroSeconds_PROMPT  #language en-US "Configure delay value after send an INIT IPI"
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuInitIpiDelayInMicroSeconds_HELP  #language en-US "Specifies delay value in microseconds after sending out an INIT IPI."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkgExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkgExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkgExtra.uni	(revision 58464)
@@ -0,0 +1,20 @@
+﻿// /** @file
+// UefiCpu Package Localized Strings and Content.
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials are licensed and made available under
+// the terms and conditions of the BSD License which accompanies this distribution.
+// The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME 
+#language en-US 
+"UefiCpu package"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.S
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.S	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.S	(revision 58464)
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------
+#*
+#*   Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+#*   This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*    AsmFuncs.S
+#*
+#*   Abstract:
+#*
+#*     Assembly function to set segment selectors.
+#
+#------------------------------------------------------------------------------
+
+.text
+
+#------------------------------------------------------------------------------
+# 
+# VOID
+# EFIAPI
+# AsmSetDataSelectors (
+#   IN UINT16   SelectorValue
+#   );
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(AsmSetDataSelectors)
+ASM_PFX(AsmSetDataSelectors):
+    movl    4(%esp),  %eax
+    movw    %ax, %ss
+    movw    %ax, %ds
+    movw    %ax, %es
+    movw    %ax, %fs
+    movw    %ax, %gs 
+    ret
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.asm	(revision 58464)
@@ -0,0 +1,45 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   AsmFuncs.Asm
+;
+; Abstract:
+;
+;   Assembly function to set segment selectors.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+.686
+.model  flat,C
+
+.code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmSetDataSelectors (
+;   IN UINT16   SelectorValue
+;   );
+;------------------------------------------------------------------------------
+AsmSetDataSelectors   PROC near public
+  mov     eax, [esp + 4]
+  mov     ds, ax
+  mov     es, ax
+  mov     fs, ax
+  mov     gs, ax
+  mov     ss, ax   
+  ret
+AsmSetDataSelectors   ENDP
+
+END
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.uni	(revision 58464)
@@ -0,0 +1,26 @@
+﻿// /** @file
+// S3 Resume Module installs EFI_PEI_S3_RESUME2_PPI.
+//
+// This module works with StandAloneBootScriptExecutor to S3 resume to OS.
+// This module will excute the boot script saved during last boot and after that,
+// control is passed to OS waking up handler.
+//
+// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials are
+// licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+// 
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "S3 Resume Module installs EFI_PEI_S3_RESUME2_PPI"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "This module works with StandAloneBootScriptExecutor to S3 resume to OS.\n"
+                                                        "This module will execute the boot script saved during last boot and after that,\n"
+                                                        "control is passed to the OS waking up handler."
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2PeiExtra.uni
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2PeiExtra.uni	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2PeiExtra.uni	(revision 58464)
@@ -0,0 +1,20 @@
+﻿// /** @file
+// S3Resume2Pei Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials are
+// licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME 
+#language en-US 
+"S3 Resume v2 PEI Module"
+
+
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.S
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.S	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.S	(revision 58464)
@@ -0,0 +1,37 @@
+#------------------------------------------------------------------------------
+#*
+#*   Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+#*   This program and the accompanying materials
+#*   are licensed and made available under the terms and conditions of the BSD License
+#*   which accompanies this distribution.  The full text of the license may be found at
+#*   http://opensource.org/licenses/bsd-license.php
+#*
+#*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#*    AsmFuncs.S
+#*
+#*   Abstract:
+#*
+#*     Assembly function to set segment selectors.
+#
+#------------------------------------------------------------------------------
+
+.text
+
+#------------------------------------------------------------------------------
+# 
+# VOID
+# EFIAPI
+# AsmSetDataSelectors (
+#   IN UINT16   SelectorValue
+#   );
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(AsmSetDataSelectors)
+ASM_PFX(AsmSetDataSelectors):
+    movw    %cx, %ss
+    movw    %cx, %ds
+    movw    %cx, %es
+    movw    %cx, %fs
+    movw    %cx, %gs 
+    ret
Index: trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.asm
===================================================================
--- trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.asm	(revision 58464)
+++ trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.asm	(revision 58464)
@@ -0,0 +1,41 @@
+;------------------------------------------------------------------------------ ;
+; Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+;   AsmFuncs.Asm
+;
+; Abstract:
+;
+;   Assembly function to set segment selectors.
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+.code
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; AsmSetDataSelectors (
+;   IN UINT16   SelectorValue
+;   );
+;------------------------------------------------------------------------------
+AsmSetDataSelectors   PROC
+  mov     ds, cx
+  mov     es, cx
+  mov     fs, cx
+  mov     gs, cx
+  mov     ss, cx   
+  ret
+AsmSetDataSelectors   ENDP
+
+END
