Changeset 58466 in vbox for trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg
- Timestamp:
- Oct 29, 2015 4:30:44 AM (9 years ago)
- svn:sync-xref-src-repo-rev:
- 103777
- Location:
- trunk/src/VBox/Devices/EFI/Firmware
- Files:
-
- 35 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/EFI/Firmware
- Property svn:mergeinfo changed
/vendor/edk2/current merged: 103769-103776
- Property svn:mergeinfo changed
-
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
r58459 r58466 3 3 # 4 4 # Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR> 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 # 13 13 ## … … 26 26 MdePkg/MdePkg.dec 27 27 IntelFrameworkPkg/IntelFrameworkPkg.dec 28 28 29 29 [LibraryClasses] 30 30 UefiBootServicesTableLib … … 39 39 40 40 [Protocols] 41 gEfiCpuArchProtocolGuid ## CONSUMES 41 gEfiCpuArchProtocolGuid ## CONSUMES 42 42 gEfiLegacy8259ProtocolGuid ## CONSUMES 43 43 gEfiTimerArchProtocolGuid ## PRODUCES -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/8254TimerDxe/Timer.c
r58459 r58466 3 3 4 4 Copyright (c) 2005 - 2012, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 13 **/ … … 298 298 UINT16 IRQMask; 299 299 EFI_TPL OriginalTPL; 300 300 301 301 // 302 302 // If the timer interrupt is enabled, then the registered handler will be invoked. … … 316 316 mTimerNotifyFunction (mTimerPeriod); 317 317 } 318 318 319 319 gBS->RestoreTPL (OriginalTPL); 320 320 } else { -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/8254TimerDxe/Timer.h
r58459 r58466 3 3 4 4 Copyright (c) 2005 - 2012, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 **/ 13 13 -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c
r58459 r58466 214 214 IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI); 215 215 IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI); 216 216 217 217 gBS->RestoreTPL (OriginalTpl); 218 218 -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
r58459 r58466 3 3 # 4 4 # Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.<BR> 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 # 13 13 ## … … 30 30 IntelFrameworkPkg/IntelFrameworkPkg.dec 31 31 PcAtChipsetPkg/PcAtChipsetPkg.dec 32 32 33 33 [LibraryClasses] 34 34 UefiBootServicesTableLib … … 37 37 IoLib 38 38 PcdLib 39 39 40 40 [Protocols] 41 41 gEfiLegacy8259ProtocolGuid ## PRODUCES … … 45 45 gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask ## CONSUMES 46 46 gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel ## CONSUMES 47 47 48 48 [Depex] 49 49 TRUE -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/ComponentName.c
r48674 r58466 74 74 is the name of the driver specified by This in the language 75 75 specified by Language. 76 76 77 77 @retval EFI_SUCCESS The Unicode string for the Driver specified by This 78 78 and the language specified by Language was returned … … 102 102 /** 103 103 Retrieves a Unicode string that is the user readable name of the controller 104 that is being managed by an EFI Driver. 104 that is being managed by an EFI Driver. 105 105 106 106 @param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance. … … 125 125 specified by Language from the point of view of the 126 126 driver specified by This. 127 127 128 128 @retval EFI_SUCCESS The Unicode string for the user readable name in the 129 129 language specified by Language for the driver -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeController.h
r48674 r58466 119 119 /** 120 120 Returns the information about the specified IDE channel. 121 121 122 122 This function can be used to obtain information about a particular IDE channel. 123 The driver entity uses this information during the enumeration process. 124 125 If Enabled is set to FALSE, the driver entity will not scan the channel. Note 123 The driver entity uses this information during the enumeration process. 124 125 If Enabled is set to FALSE, the driver entity will not scan the channel. Note 126 126 that it will not prevent an operating system driver from scanning the channel. 127 128 For most of today's controllers, MaxDevices will either be 1 or 2. For SATA 129 controllers, this value will always be 1. SATA configurations can contain SATA 127 128 For most of today's controllers, MaxDevices will either be 1 or 2. For SATA 129 controllers, this value will always be 1. SATA configurations can contain SATA 130 130 port multipliers. SATA port multipliers behave like SATA bridges and can support 131 up to 16 devices on the other side. If a SATA port out of the IDE controller 132 is connected to a port multiplier, MaxDevices will be set to the number of SATA 133 devices that the port multiplier supports. Because today's port multipliers 134 support up to fifteen SATA devices, this number can be as large as fifteen. The IDE 135 bus driver is required to scan for the presence of port multipliers behind an SATA 136 controller and enumerate up to MaxDevices number of devices behind the port 137 multiplier. 138 139 In this context, the devices behind a port multiplier constitute a channel. 140 131 up to 16 devices on the other side. If a SATA port out of the IDE controller 132 is connected to a port multiplier, MaxDevices will be set to the number of SATA 133 devices that the port multiplier supports. Because today's port multipliers 134 support up to fifteen SATA devices, this number can be as large as fifteen. The IDE 135 bus driver is required to scan for the presence of port multipliers behind an SATA 136 controller and enumerate up to MaxDevices number of devices behind the port 137 multiplier. 138 139 In this context, the devices behind a port multiplier constitute a channel. 140 141 141 @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. 142 142 @param[in] Channel Zero-based channel number. 143 @param[out] Enabled TRUE if this channel is enabled. Disabled channels 143 @param[out] Enabled TRUE if this channel is enabled. Disabled channels 144 144 are not scanned to see if any devices are present. 145 145 @param[out] MaxDevices The maximum number of IDE devices that the bus driver 146 can expect on this channel. For the ATA/ATAPI 147 specification, version 6, this number will either be 148 one or two. For Serial ATA (SATA) configurations with a 146 can expect on this channel. For the ATA/ATAPI 147 specification, version 6, this number will either be 148 one or two. For Serial ATA (SATA) configurations with a 149 149 port multiplier, this number can be as large as fifteen. 150 150 … … 166 166 The notifications from the driver entity that it is about to enter a certain 167 167 phase of the IDE channel enumeration process. 168 169 This function can be used to notify the IDE controller driver to perform 170 specific actions, including any chipset-specific initialization, so that the 171 chipset is ready to enter the next phase. Seven notification points are defined 172 at this time. 173 174 More synchronization points may be added as required in the future. 168 169 This function can be used to notify the IDE controller driver to perform 170 specific actions, including any chipset-specific initialization, so that the 171 chipset is ready to enter the next phase. Seven notification points are defined 172 at this time. 173 174 More synchronization points may be added as required in the future. 175 175 176 176 @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. … … 181 181 @retval EFI_UNSUPPORTED Phase is not supported. 182 182 @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). 183 @retval EFI_NOT_READY This phase cannot be entered at this time; for 184 example, an attempt was made to enter a Phase 185 without having entered one or more previous 183 @retval EFI_NOT_READY This phase cannot be entered at this time; for 184 example, an attempt was made to enter a Phase 185 without having entered one or more previous 186 186 Phase. 187 187 … … 199 199 Submits the device information to the IDE controller driver. 200 200 201 This function is used by the driver entity to pass detailed information about 202 a particular device to the IDE controller driver. The driver entity obtains 201 This function is used by the driver entity to pass detailed information about 202 a particular device to the IDE controller driver. The driver entity obtains 203 203 this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData 204 is the pointer to the response data buffer. The IdentifyData buffer is owned 205 by the driver entity, and the IDE controller driver must make a local copy 206 of the entire buffer or parts of the buffer as needed. The original IdentifyData 204 is the pointer to the response data buffer. The IdentifyData buffer is owned 205 by the driver entity, and the IDE controller driver must make a local copy 206 of the entire buffer or parts of the buffer as needed. The original IdentifyData 207 207 buffer pointer may not be valid when 208 208 209 209 - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or 210 210 - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point. 211 212 The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to 213 compute the optimum mode for the device. These fields are not limited to the 214 timing information. For example, an implementation of the IDE controller driver 215 may examine the vendor and type/mode field to match known bad drives. 216 217 The driver entity may submit drive information in any order, as long as it 218 submits information for all the devices belonging to the enumeration group 211 212 The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to 213 compute the optimum mode for the device. These fields are not limited to the 214 timing information. For example, an implementation of the IDE controller driver 215 may examine the vendor and type/mode field to match known bad drives. 216 217 The driver entity may submit drive information in any order, as long as it 218 submits information for all the devices belonging to the enumeration group 219 219 before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device 220 220 in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 221 should be called with IdentifyData set to NULL. The IDE controller driver may 222 not have any other mechanism to know whether a device is present or not. Therefore, 223 setting IdentifyData to NULL does not constitute an error condition. 224 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a 225 given (Channel, Device) pair. 226 221 should be called with IdentifyData set to NULL. The IDE controller driver may 222 not have any other mechanism to know whether a device is present or not. Therefore, 223 setting IdentifyData to NULL does not constitute an error condition. 224 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a 225 given (Channel, Device) pair. 226 227 227 @param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. 228 228 @param[in] Channel Zero-based channel number. … … 248 248 Disqualifies specific modes for an IDE device. 249 249 250 This function allows the driver entity or other drivers (such as platform 250 This function allows the driver entity or other drivers (such as platform 251 251 drivers) to reject certain timing modes and request the IDE controller driver 252 to recalculate modes. This function allows the driver entity and the IDE 253 controller driver to negotiate the timings on a per-device basis. This function 254 is useful in the case of drives that lie about their capabilities. An example 255 is when the IDE device fails to accept the timing modes that are calculated 252 to recalculate modes. This function allows the driver entity and the IDE 253 controller driver to negotiate the timings on a per-device basis. This function 254 is useful in the case of drives that lie about their capabilities. An example 255 is when the IDE device fails to accept the timing modes that are calculated 256 256 by the IDE controller driver based on the response to the Identify Drive command. 257 257 258 If the driver entity does not want to limit the ATA timing modes and leave that 259 decision to the IDE controller driver, it can either not call this function for 260 the given device or call this function and set the Valid flag to FALSE for all 258 If the driver entity does not want to limit the ATA timing modes and leave that 259 decision to the IDE controller driver, it can either not call this function for 260 the given device or call this function and set the Valid flag to FALSE for all 261 261 modes that are listed in EFI_ATA_COLLECTIVE_MODE. 262 263 The driver entity may disqualify modes for a device in any order and any number 262 263 The driver entity may disqualify modes for a device in any order and any number 264 264 of times. 265 266 This function can be called multiple times to invalidate multiple modes of the 267 same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI 268 specification for more information on PIO modes. 269 265 266 This function can be called multiple times to invalidate multiple modes of the 267 same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI 268 specification for more information on PIO modes. 269 270 270 For Serial ATA (SATA) controllers, this member function can be used to disqualify 271 271 a higher transfer rate mode on a given channel. For example, a platform driver 272 may inform the IDE controller driver to not use second-generation (Gen2) speeds 272 may inform the IDE controller driver to not use second-generation (Gen2) speeds 273 273 for a certain SATA drive. 274 274 275 275 @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. 276 276 @param[in] Channel The zero-based channel number. … … 283 283 @retval EFI_INVALID_PARAMETER Device is invalid. 284 284 @retval EFI_INVALID_PARAMETER IdentifyData is NULL. 285 285 286 286 **/ 287 287 EFI_STATUS … … 299 299 300 300 This function is used by the driver entity to obtain the optimum ATA modes for 301 a specific device. The IDE controller driver takes into account the following 301 a specific device. The IDE controller driver takes into account the following 302 302 while calculating the mode: 303 303 - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 304 304 - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() 305 305 306 The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 307 for all the devices that belong to an enumeration group before calling 308 EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group. 309 310 The IDE controller driver will use controller- and possibly platform-specific 311 algorithms to arrive at SupportedModes. The IDE controller may base its 312 decision on user preferences and other considerations as well. This function 313 may be called multiple times because the driver entity may renegotiate the mode 306 The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 307 for all the devices that belong to an enumeration group before calling 308 EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group. 309 310 The IDE controller driver will use controller- and possibly platform-specific 311 algorithms to arrive at SupportedModes. The IDE controller may base its 312 decision on user preferences and other considerations as well. This function 313 may be called multiple times because the driver entity may renegotiate the mode 314 314 with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode(). 315 316 The driver entity may collect timing information for various devices in any 315 316 The driver entity may collect timing information for various devices in any 317 317 order. The driver entity is responsible for making sure that all the dependencies 318 are satisfied. For example, the SupportedModes information for device A that 319 was previously returned may become stale after a call to 318 are satisfied. For example, the SupportedModes information for device A that 319 was previously returned may become stale after a call to 320 320 EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B. 321 322 The buffer SupportedModes is allocated by the callee because the caller does 323 not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE 324 is defined in a way that allows for future extensibility and can be of variable 325 length. This memory pool should be deallocated by the caller when it is no 326 longer necessary. 327 328 The IDE controller driver for a Serial ATA (SATA) controller can use this 329 member function to force a lower speed (first-generation [Gen1] speeds on a 330 second-generation [Gen2]-capable hardware). The IDE controller driver can 331 also allow the driver entity to stay with the speed that has been negotiated 321 322 The buffer SupportedModes is allocated by the callee because the caller does 323 not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE 324 is defined in a way that allows for future extensibility and can be of variable 325 length. This memory pool should be deallocated by the caller when it is no 326 longer necessary. 327 328 The IDE controller driver for a Serial ATA (SATA) controller can use this 329 member function to force a lower speed (first-generation [Gen1] speeds on a 330 second-generation [Gen2]-capable hardware). The IDE controller driver can 331 also allow the driver entity to stay with the speed that has been negotiated 332 332 by the physical layer. 333 333 334 334 @param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance. 335 335 @param[in] Channel A zero-based channel number. … … 339 339 @retval EFI_SUCCESS SupportedModes was returned. 340 340 @retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount). 341 @retval EFI_INVALID_PARAMETER Device is invalid. 341 @retval EFI_INVALID_PARAMETER Device is invalid. 342 342 @retval EFI_INVALID_PARAMETER SupportedModes is NULL. 343 @retval EFI_NOT_READY Modes cannot be calculated due to a lack of 344 data. This error may happen if 345 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 346 and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData() 347 were not called for at least one drive in the 343 @retval EFI_NOT_READY Modes cannot be calculated due to a lack of 344 data. This error may happen if 345 EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 346 and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData() 347 were not called for at least one drive in the 348 348 same enumeration group. 349 349 … … 363 363 so that the specified device can operate at the specified mode. 364 364 365 This function is used by the driver entity to instruct the IDE controller 366 driver to program the IDE controller hardware to the specified modes. This 367 function can be called only once for a particular device. For a Serial ATA 365 This function is used by the driver entity to instruct the IDE controller 366 driver to program the IDE controller hardware to the specified modes. This 367 function can be called only once for a particular device. For a Serial ATA 368 368 (SATA) Advanced Host Controller Interface (AHCI) controller, no controller- 369 369 specific programming may be required. -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
r58459 r58466 53 53 54 54 @param This The EFI_TIMER_ARCH_PROTOCOL instance. 55 @param NotifyFunction The function to call when a timer interrupt fires. 56 This function executes at TPL_HIGH_LEVEL. The DXE 57 Core will register a handler for the timer interrupt, 58 so it can know how much time has passed. This 59 information is used to signal timer based events. 55 @param NotifyFunction The function to call when a timer interrupt fires. 56 This function executes at TPL_HIGH_LEVEL. The DXE 57 Core will register a handler for the timer interrupt, 58 so it can know how much time has passed. This 59 information is used to signal timer based events. 60 60 NULL will unregister the handler. 61 61 … … 91 91 @param This The EFI_TIMER_ARCH_PROTOCOL instance. 92 92 @param TimerPeriod The rate to program the timer interrupt in 100 nS units. 93 If the timer hardware is not programmable, then 94 EFI_UNSUPPORTED is returned. If the timer is programmable, 95 then the timer period will be rounded up to the nearest 96 timer period that is supported by the timer hardware. 97 If TimerPeriod is set to 0, then the timer interrupts 93 If the timer hardware is not programmable, then 94 EFI_UNSUPPORTED is returned. If the timer is programmable, 95 then the timer period will be rounded up to the nearest 96 timer period that is supported by the timer hardware. 97 If TimerPeriod is set to 0, then the timer interrupts 98 98 will be disabled. 99 99 … … 143 143 144 144 @retval EFI_SUCCESS The soft timer interrupt was generated. 145 @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft 145 @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft 146 146 timer interrupts. 147 147 … … 152 152 IN EFI_TIMER_ARCH_PROTOCOL *This 153 153 ); 154 154 155 155 /// 156 156 /// The handle onto which the Timer Architectural Protocol will be installed. … … 223 223 224 224 /// 225 /// Cached state of the Configuration register for the HPET Timer managed by 225 /// Cached state of the Configuration register for the HPET Timer managed by 226 226 /// this driver. Caching the state reduces the number of times the configuration 227 227 /// register is read. … … 278 278 ) 279 279 { 280 mHpetGeneralConfiguration.Bits.MainCounterEnable = Enable ? 1 : 0; 280 mHpetGeneralConfiguration.Bits.MainCounterEnable = Enable ? 1 : 0; 281 281 HpetWrite (HPET_GENERAL_CONFIGURATION_OFFSET, mHpetGeneralConfiguration.Uint64); 282 282 } … … 287 287 If a notification function is registered, then the amount of time since the last 288 288 HPET interrupt is passed to that notification function in 100 ns units. The HPET 289 time is updated to generate another interrupt in the required time period. 289 time is updated to generate another interrupt in the required time period. 290 290 291 291 @param InterruptType The type of interrupt that occured. … … 323 323 // 324 324 HpetEnable (FALSE); 325 325 326 326 // 327 327 // Capture main counter value … … 364 364 // 365 365 HpetEnable (TRUE); 366 366 367 367 // 368 368 // Check to see if there is a registered notification function … … 370 370 if (mTimerNotifyFunction != NULL) { 371 371 // 372 // Compute time since last notification in 100 ns units (10 ^ -7) 372 // Compute time since last notification in 100 ns units (10 ^ -7) 373 373 // 374 374 if (MainCounter > mPreviousMainCounter) { … … 387 387 Delta & mCounterMask, 388 388 mHpetGeneralCapabilities.Bits.CounterClockPeriod 389 ), 389 ), 390 390 100000000 391 391 ); 392 392 393 393 // 394 394 // Call registered notification function passing in the time since the last 395 395 // interrupt in 100 ns units. 396 // 396 // 397 397 mTimerNotifyFunction (TimerPeriod); 398 398 } 399 399 400 400 // 401 401 // Save main counter value … … 418 418 419 419 @param This The EFI_TIMER_ARCH_PROTOCOL instance. 420 @param NotifyFunction The function to call when a timer interrupt fires. 421 This function executes at TPL_HIGH_LEVEL. The DXE 422 Core will register a handler for the timer interrupt, 423 so it can know how much time has passed. This 424 information is used to signal timer based events. 420 @param NotifyFunction The function to call when a timer interrupt fires. 421 This function executes at TPL_HIGH_LEVEL. The DXE 422 Core will register a handler for the timer interrupt, 423 so it can know how much time has passed. This 424 information is used to signal timer based events. 425 425 NULL will unregister the handler. 426 426 … … 474 474 @param This The EFI_TIMER_ARCH_PROTOCOL instance. 475 475 @param TimerPeriod The rate to program the timer interrupt in 100 nS units. 476 If the timer hardware is not programmable, then 477 EFI_UNSUPPORTED is returned. If the timer is programmable, 478 then the timer period will be rounded up to the nearest 479 timer period that is supported by the timer hardware. 480 If TimerPeriod is set to 0, then the timer interrupts 476 If the timer hardware is not programmable, then 477 EFI_UNSUPPORTED is returned. If the timer is programmable, 478 then the timer period will be rounded up to the nearest 479 timer period that is supported by the timer hardware. 480 If TimerPeriod is set to 0, then the timer interrupts 481 481 will be disabled. 482 482 … … 497 497 UINT64 CurrentComparator; 498 498 HPET_TIMER_MSI_ROUTE_REGISTER HpetTimerMsiRoute; 499 499 500 500 // 501 501 // Disable HPET timer when adjusting the timer period 502 502 // 503 503 HpetEnable (FALSE); 504 504 505 505 if (TimerPeriod == 0) { 506 506 if (mTimerPeriod != 0) { … … 511 511 if (MainCounter < mPreviousMainCounter) { 512 512 Delta = (mCounterMask - mPreviousMainCounter) + MainCounter; 513 } else { 513 } else { 514 514 Delta = MainCounter - mPreviousMainCounter; 515 515 } … … 530 530 // If TimerPeriod is 0, then mask HPET Timer interrupts 531 531 // 532 532 533 533 if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) { 534 534 // … … 542 542 IoApicEnableInterrupt (mTimerIrq, FALSE); 543 543 } 544 545 // 546 // Disable HPET timer interrupt 544 545 // 546 // Disable HPET timer interrupt 547 547 // 548 548 mTimerConfiguration.Bits.InterruptEnable = 0; … … 550 550 } else { 551 551 // 552 // Convert TimerPeriod to femtoseconds and divide by the number if femtoseconds 552 // Convert TimerPeriod to femtoseconds and divide by the number if femtoseconds 553 553 // per tick of the HPET counter to determine the number of HPET counter ticks 554 554 // in TimerPeriod 100 ns units. 555 // 555 // 556 556 mTimerCount = DivU64x32 ( 557 557 MultU64x32 (TimerPeriod, 100000000), … … 565 565 if (MainCounter > mPreviousMainCounter) { 566 566 Delta = MainCounter - mPreviousMainCounter; 567 } else { 567 } else { 568 568 Delta = (mCounterMask - mPreviousMainCounter) + MainCounter; 569 569 } 570 570 if ((Delta & mCounterMask) >= mTimerCount) { 571 571 HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (MainCounter + 1) & mCounterMask); 572 } else { 572 } else { 573 573 HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (mPreviousMainCounter + mTimerCount) & mCounterMask); 574 574 } 575 575 576 576 // 577 577 // Enable HPET Timer interrupt generation … … 604 604 HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64); 605 605 } 606 606 607 607 // 608 608 // Save the new timer period … … 617 617 // 618 618 HpetEnable (TRUE); 619 619 620 620 return EFI_SUCCESS; 621 621 } … … 663 663 664 664 @retval EFI_SUCCESS The soft timer interrupt was generated. 665 @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft 665 @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft 666 666 timer interrupts. 667 667 … … 680 680 // 681 681 // Disable interrupts 682 // 682 // 683 683 Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); 684 684 685 685 // 686 686 // Capture main counter value … … 693 693 if (mTimerNotifyFunction != NULL) { 694 694 // 695 // Compute time since last interrupt in 100 ns units (10 ^ -7) 695 // Compute time since last interrupt in 100 ns units (10 ^ -7) 696 696 // 697 697 if (MainCounter > mPreviousMainCounter) { … … 711 711 Delta & mCounterMask, 712 712 mHpetGeneralCapabilities.Bits.CounterClockPeriod 713 ), 713 ), 714 714 100000000 715 715 ); 716 716 717 717 // 718 718 // Call registered notification function passing in the time since the last 719 719 // interrupt in 100 ns units. 720 // 720 // 721 721 mTimerNotifyFunction (TimerPeriod); 722 722 } … … 726 726 // 727 727 mPreviousMainCounter = MainCounter; 728 728 729 729 // 730 730 // Restore interrupts 731 // 731 // 732 732 gBS->RestoreTPL (Tpl); 733 733 734 734 return EFI_SUCCESS; 735 735 } … … 773 773 // 774 774 // Retrieve HPET Capabilities and Configuration Information 775 // 775 // 776 776 mHpetGeneralCapabilities.Uint64 = HpetRead (HPET_GENERAL_CAPABILITIES_ID_OFFSET); 777 777 mHpetGeneralConfiguration.Uint64 = HpetRead (HPET_GENERAL_CONFIGURATION_OFFSET); 778 779 // 780 // If Revision is not valid, then ASSERT() and unload the driver because the HPET 778 779 // 780 // If Revision is not valid, then ASSERT() and unload the driver because the HPET 781 781 // device is not present. 782 // 782 // 783 783 ASSERT (mHpetGeneralCapabilities.Uint64 != 0); 784 784 ASSERT (mHpetGeneralCapabilities.Uint64 != 0xFFFFFFFFFFFFFFFFULL); … … 795 795 // 796 796 // Dump HPET Configuration Information 797 // 797 // 798 798 DEBUG_CODE ( 799 799 DEBUG ((DEBUG_INFO, "HPET Base Address = 0x%08x\n", PcdGet32 (PcdHpetBaseAddress))); … … 809 809 } 810 810 ); 811 811 812 812 // 813 813 // Capture the current HPET main counter value. 814 814 // 815 815 mPreviousMainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET); 816 817 // 818 // Determine the interrupt mode to use for the HPET Timer. 816 817 // 818 // Determine the interrupt mode to use for the HPET Timer. 819 819 // Look for MSI first, then unused PIC mode interrupt, then I/O APIC mode interrupt 820 // 820 // 821 821 MsiTimerIndex = HPET_INVALID_TIMER_INDEX; 822 822 mTimerIndex = HPET_INVALID_TIMER_INDEX; … … 826 826 // 827 827 mTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + TimerIndex * HPET_TIMER_STRIDE); 828 829 // 830 // Check to see if this HPET Timer supports MSI 828 829 // 830 // Check to see if this HPET Timer supports MSI 831 831 // 832 832 if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) { … … 838 838 } 839 839 } 840 840 841 841 // 842 842 // Check to see if this HPET Timer supports I/O APIC interrupts … … 881 881 return EFI_DEVICE_ERROR; 882 882 } 883 883 884 884 // 885 885 // Initialize I/O APIC entry for HPET Timer Interrupt … … 901 901 // 902 902 // Configure the selected HPET Timer with settings common to both MSI mode and I/O APIC mode 903 // Clear InterruptEnable to keep interrupts disabled until full init is complete 904 // Clear PeriodicInterruptEnable to use one-shot mode 905 // Configure as a 32-bit counter 903 // Clear InterruptEnable to keep interrupts disabled until full init is complete 904 // Clear PeriodicInterruptEnable to use one-shot mode 905 // Configure as a 32-bit counter 906 906 // 907 907 mTimerConfiguration.Bits.InterruptEnable = 0; … … 909 909 mTimerConfiguration.Bits.CounterSizeEnable = 1; 910 910 HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64); 911 911 912 912 // 913 913 // Read the HPET Timer Capabilities and Configuration register back again. … … 960 960 DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n")); 961 961 DEBUG ((DEBUG_INFO, "HPET I/O APIC IRQ = 0x%02x\n", mTimerIrq)); 962 } 962 } 963 963 DEBUG ((DEBUG_INFO, "HPET Interrupt Vector = 0x%02x\n", PcdGet8 (PcdHpetLocalApicVector))); 964 964 DEBUG ((DEBUG_INFO, "HPET Counter Mask = 0x%016lx\n", mCounterMask)); … … 971 971 // 972 972 // Wait for a few timer interrupts to fire before continuing 973 // 973 // 974 974 while (mNumTicks < 10); 975 975 ); 976 976 977 977 // 978 978 // Install the Timer Architectural Protocol onto a new handle -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
r58459 r58466 3 3 # 4 4 # Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR> 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 # This program and the accompanying materials 6 # are licensed and made available under the terms and conditions of the BSD License 7 # which accompanies this distribution. The full text of the license may be found at 8 # http://opensource.org/licenses/bsd-license.php 9 # 10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 # 13 13 ## … … 31 31 [Sources] 32 32 HpetTimer.c 33 33 34 34 [Packages] 35 35 MdePkg/MdePkg.dec 36 36 UefiCpuPkg/UefiCpuPkg.dec 37 37 PcAtChipsetPkg/PcAtChipsetPkg.dec 38 38 39 39 [LibraryClasses] 40 40 PcdLib -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Library/IoApicLib.h
r48674 r58466 22 22 23 23 If Index is >= 0x100, then ASSERT(). 24 24 25 25 @param Index Specifies the I/O APIC register to read. 26 26 … … 37 37 38 38 If Index is >= 0x100, then ASSERT(). 39 39 40 40 @param Index Specifies the I/O APIC register to write. 41 41 @param Value Specifies the value to write to the I/O APIC register specified by Index. … … 53 53 Set the interrupt mask of an I/O APIC interrupt. 54 54 55 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 56 55 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 56 57 57 @param Irq Specifies the I/O APIC interrupt to enable or disable. 58 58 @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq. … … 68 68 /** 69 69 Configures an I/O APIC interrupt. 70 70 71 71 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical 72 mode to the Local APIC of the currntly executing CPU. The default state of the 72 mode to the Local APIC of the currntly executing CPU. The default state of the 73 73 entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must 74 74 be used to enable(unmask) the I/O APIC Interrupt. 75 75 76 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 76 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 77 77 If Vector >= 0x100, then ASSERT(). 78 78 If DeliveryMode is not supported, then ASSERT(). -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Register/Hpet.h
r48674 r58466 1 1 /** @file 2 HPET register definitions from the IA-PC HPET (High Precision Event Timers) 2 HPET register definitions from the IA-PC HPET (High Precision Event Timers) 3 3 Specification, Revision 1.0a, October 2004. 4 4 -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Register/IoApic.h
r48674 r58466 1 1 /** @file 2 I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt 2 I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt 3 3 Controller (IOAPIC), 1996. 4 4 5 5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR> 6 6 This program and the accompanying materials -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/IsaAcpiDxe/ComponentName.c
r48674 r58466 3 3 4 4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 **/ 13 13 … … 220 220 Language, 221 221 This->SupportedLanguages, 222 mPcatIsaAcpiDriverNameTable, 222 mPcatIsaAcpiDriverNameTable, 223 223 DriverName, 224 224 (BOOLEAN)(This == &gPcatIsaAcpiComponentName) -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.c
r58459 r58466 3 3 4 4 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 **/ 13 13 … … 147 147 Enumerate the ISA devices on the ISA bus. 148 148 149 @param Device Point to device ID instance 149 @param Device Point to device ID instance 150 150 @param IsaAcpiDevice On return, point to resource data for Isa device 151 151 @param NextIsaAcpiDevice On return, point to resource data for next Isa device … … 168 168 } else { 169 169 for(Index = 0; gPcatIsaAcpiDeviceList[Index].ResourceItem != NULL; Index++) { 170 if (Device->HID == gPcatIsaAcpiDeviceList[Index].Device.HID && 170 if (Device->HID == gPcatIsaAcpiDeviceList[Index].Device.HID && 171 171 Device->UID == gPcatIsaAcpiDeviceList[Index].Device.UID ) { 172 172 break; … … 189 189 190 190 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 191 @param Device Point to device ID instance 191 @param Device Point to device ID instance 192 192 193 193 @retval EFI_NOT_FOUND Can not found the next Isa device. … … 218 218 219 219 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 220 @param Device Point to device ID instance 220 @param Device Point to device ID instance 221 221 @param OnOff TRUE for setting isa device power on, 222 222 FALSE for setting isa device power off … … 233 233 { 234 234 return EFI_SUCCESS; 235 } 235 } 236 236 237 237 /** … … 239 239 240 240 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 241 @param Device Point to device ID instance 241 @param Device Point to device ID instance 242 242 @param ResourceList On return, point to resources instances for given isa device 243 243 … … 249 249 IsaGetCurrentResource ( 250 250 IN EFI_ISA_ACPI_PROTOCOL *This, 251 IN EFI_ISA_ACPI_DEVICE_ID *Device, 251 IN EFI_ISA_ACPI_DEVICE_ID *Device, 252 252 OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList 253 253 ) … … 262 262 /** 263 263 Get possible resource for the specific ISA device. 264 265 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 266 @param Device Point to device ID instance 264 265 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 266 @param Device Point to device ID instance 267 267 @param ResourceList On return, point to resources instances for given isa device 268 268 … … 273 273 IsaGetPossibleResource ( 274 274 IN EFI_ISA_ACPI_PROTOCOL *This, 275 IN EFI_ISA_ACPI_DEVICE_ID *Device, 275 IN EFI_ISA_ACPI_DEVICE_ID *Device, 276 276 OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList 277 277 ) … … 284 284 285 285 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 286 @param Device Point to device ID instance 286 @param Device Point to device ID instance 287 287 @param ResourceList Point to resources instances for given isa device 288 288 … … 294 294 IsaSetResource ( 295 295 IN EFI_ISA_ACPI_PROTOCOL *This, 296 IN EFI_ISA_ACPI_DEVICE_ID *Device, 296 IN EFI_ISA_ACPI_DEVICE_ID *Device, 297 297 IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList 298 298 ) … … 300 300 return EFI_SUCCESS; 301 301 } 302 302 303 303 /** 304 304 Enable/Disable the specific ISA device. 305 305 306 306 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 307 @param Device Point to device ID instance 307 @param Device Point to device ID instance 308 308 @param Enable Enable/Disable 309 309 … … 319 319 ) 320 320 { 321 return EFI_SUCCESS; 321 return EFI_SUCCESS; 322 322 } 323 323 … … 326 326 327 327 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 328 @param Device Point to device ID instance 328 @param Device Point to device ID instance 329 329 330 330 @return EFI_SUCESS Success to initialize. … … 354 354 IsaInterfaceInit ( 355 355 IN EFI_ISA_ACPI_PROTOCOL *This 356 ) 357 { 358 return EFI_SUCCESS; 359 } 356 ) 357 { 358 return EFI_SUCCESS; 359 } -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c
r58459 r58466 43 43 { 44 44 return EfiLibInstallDriverBindingComponentName2 ( 45 ImageHandle, 46 SystemTable, 45 ImageHandle, 46 SystemTable, 47 47 &gPcatIsaAcpiDriverBinding, 48 48 ImageHandle, … … 55 55 ControllerDriver Protocol Method 56 56 57 @param This Driver Binding protocol instance pointer. 57 @param This Driver Binding protocol instance pointer. 58 58 @param Controller Handle of device to test. 59 59 @param RemainingDevicePath Optional parameter use to pick a specific child … … 81 81 // 82 82 // Get PciIo protocol instance 83 // 83 // 84 84 Status = gBS->OpenProtocol ( 85 Controller, 86 &gEfiPciIoProtocolGuid, 85 Controller, 86 &gEfiPciIoProtocolGuid, 87 87 (VOID**)&PciIo, 88 88 This->DriverBindingHandle, … … 98 98 EfiPciIoWidthUint32, 99 99 0, 100 sizeof(Pci) / sizeof(UINT32), 100 sizeof(Pci) / sizeof(UINT32), 101 101 &Pci); 102 102 … … 110 110 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) { 111 111 Status = EFI_SUCCESS; 112 } 112 } 113 113 114 114 // 115 115 // See if this is an Intel PCI to ISA bridge in Positive Decode Mode 116 116 // 117 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE && 117 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE && 118 118 Pci.Hdr.VendorId == 0x8086 ) { 119 119 // 120 // See if this is on Function #0 to avoid false positives on 121 // PCI_CLASS_BRIDGE_OTHER that has the same value as 120 // See if this is on Function #0 to avoid false positives on 121 // PCI_CLASS_BRIDGE_OTHER that has the same value as 122 122 // PCI_CLASS_BRIDGE_ISA_PDECODE 123 123 // 124 124 Status = PciIo->GetLocation ( 125 PciIo, 126 &SegmentNumber, 127 &BusNumber, 128 &DeviceNumber, 125 PciIo, 126 &SegmentNumber, 127 &BusNumber, 128 &DeviceNumber, 129 129 &FunctionNumber 130 130 ); … … 135 135 } 136 136 } 137 } 137 } 138 138 } 139 139 } 140 140 141 141 gBS->CloseProtocol ( 142 Controller, 143 &gEfiPciIoProtocolGuid, 144 This->DriverBindingHandle, 145 Controller 142 Controller, 143 &gEfiPciIoProtocolGuid, 144 This->DriverBindingHandle, 145 Controller 146 146 ); 147 147 148 148 return Status; 149 149 } … … 183 183 PciIo = NULL; 184 184 Status = gBS->OpenProtocol ( 185 Controller, 186 &gEfiPciIoProtocolGuid, 185 Controller, 186 &gEfiPciIoProtocolGuid, 187 187 (VOID**)&PciIo, 188 This->DriverBindingHandle, 189 Controller, 190 EFI_OPEN_PROTOCOL_BY_DRIVER 188 This->DriverBindingHandle, 189 Controller, 190 EFI_OPEN_PROTOCOL_BY_DRIVER 191 191 ); 192 192 if (EFI_ERROR (Status)) { … … 211 211 Status = EFI_UNSUPPORTED; 212 212 goto Done; 213 } 213 } 214 214 215 215 Enabled = TRUE; 216 216 Status = PciIo->Attributes ( 217 PciIo, 218 EfiPciIoAttributeOperationEnable, 219 EFI_PCI_DEVICE_ENABLE | Supports | EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO, 220 NULL 217 PciIo, 218 EfiPciIoAttributeOperationEnable, 219 EFI_PCI_DEVICE_ENABLE | Supports | EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO, 220 NULL 221 221 ); 222 222 if (EFI_ERROR (Status)) { 223 223 goto Done; 224 224 } 225 225 226 226 // 227 227 // Allocate memory for the PCAT ISA ACPI Device structure … … 248 248 // 249 249 InitializePcatIsaAcpiDeviceList (); 250 250 251 251 // 252 252 // IsaAcpi interface … … 260 260 (PcatIsaAcpiDev->IsaAcpi).InitDevice = IsaInitDevice; 261 261 (PcatIsaAcpiDev->IsaAcpi).InterfaceInit = IsaInterfaceInit; 262 262 263 263 // 264 264 // Install the ISA ACPI Protocol interface … … 274 274 if (PciIo != NULL && Enabled) { 275 275 PciIo->Attributes ( 276 PciIo, 277 EfiPciIoAttributeOperationDisable, 276 PciIo, 277 EfiPciIoAttributeOperationDisable, 278 278 EFI_PCI_DEVICE_ENABLE | Supports | EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO, 279 NULL 279 NULL 280 280 ); 281 281 } 282 282 gBS->CloseProtocol ( 283 Controller, 284 &gEfiPciIoProtocolGuid, 285 This->DriverBindingHandle, 283 Controller, 284 &gEfiPciIoProtocolGuid, 285 This->DriverBindingHandle, 286 286 Controller 287 287 ); … … 291 291 return Status; 292 292 } 293 293 294 294 return EFI_SUCCESS; 295 295 } … … 323 323 PCAT_ISA_ACPI_DEV *PcatIsaAcpiDev; 324 324 UINT64 Supports; 325 325 326 326 // 327 327 // Get the ISA ACPI Protocol Interface 328 // 328 // 329 329 Status = gBS->OpenProtocol ( 330 Controller, 331 &gEfiIsaAcpiProtocolGuid, 330 Controller, 331 &gEfiIsaAcpiProtocolGuid, 332 332 (VOID**)&IsaAcpi, 333 This->DriverBindingHandle, 334 Controller, 333 This->DriverBindingHandle, 334 Controller, 335 335 EFI_OPEN_PROTOCOL_GET_PROTOCOL 336 336 ); … … 360 360 361 361 PcatIsaAcpiDev->PciIo->Attributes ( 362 PcatIsaAcpiDev->PciIo, 363 EfiPciIoAttributeOperationDisable, 362 PcatIsaAcpiDev->PciIo, 363 EfiPciIoAttributeOperationDisable, 364 364 EFI_PCI_DEVICE_ENABLE | Supports | EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO, 365 NULL 365 NULL 366 366 ); 367 367 368 368 // 369 369 // Uninstall protocol interface: EFI_ISA_ACPI_PROTOCOL … … 378 378 379 379 gBS->CloseProtocol ( 380 Controller, 381 &gEfiPciIoProtocolGuid, 382 This->DriverBindingHandle, 380 Controller, 381 &gEfiPciIoProtocolGuid, 382 This->DriverBindingHandle, 383 383 Controller 384 384 ); 385 385 386 386 gBS->FreePool (PcatIsaAcpiDev); 387 387 388 388 return EFI_SUCCESS; 389 389 } -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.h
r48674 r58466 3 3 4 4 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 13 **/ … … 41 41 typedef struct { 42 42 UINTN Signature; 43 EFI_HANDLE Handle; 43 EFI_HANDLE Handle; 44 44 EFI_ISA_ACPI_PROTOCOL IsaAcpi; 45 45 EFI_PCI_IO_PROTOCOL *PciIo; … … 64 64 ControllerDriver Protocol Method 65 65 66 @param This Driver Binding protocol instance pointer. 66 @param This Driver Binding protocol instance pointer. 67 67 @param Controller Handle of device to test. 68 68 @param RemainingDevicePath Optional parameter use to pick a specific child … … 131 131 132 132 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 133 @param Device Point to device ID instance 133 @param Device Point to device ID instance 134 134 135 135 @retval EFI_NOT_FOUND Can not found the next Isa device. … … 149 149 150 150 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 151 @param Device Point to device ID instance 151 @param Device Point to device ID instance 152 152 @param OnOff TRUE for setting isa device power on, 153 153 FALSE for setting isa device power off … … 162 162 IN BOOLEAN OnOff 163 163 ); 164 164 165 165 /** 166 166 Get current resource for the specific ISA device. 167 167 168 168 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 169 @param Device Point to device ID instance 169 @param Device Point to device ID instance 170 170 @param ResourceList On return, point to resources instances for given isa device 171 171 … … 180 180 OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList 181 181 ); 182 182 183 183 /** 184 184 Get possible resource for the specific ISA device. 185 186 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 187 @param Device Point to device ID instance 185 186 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 187 @param Device Point to device ID instance 188 188 @param ResourceList On return, point to resources instances for given isa device 189 189 … … 194 194 IsaGetPossibleResource ( 195 195 IN EFI_ISA_ACPI_PROTOCOL *This, 196 IN EFI_ISA_ACPI_DEVICE_ID *Device, 196 IN EFI_ISA_ACPI_DEVICE_ID *Device, 197 197 OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList 198 198 ); 199 199 200 200 /** 201 201 Set resource for the specific ISA device. 202 202 203 203 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 204 @param Device Point to device ID instance 204 @param Device Point to device ID instance 205 205 @param ResourceList Point to resources instances for given isa device 206 206 … … 215 215 IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList 216 216 ); 217 217 218 218 /** 219 219 Enable/Disable the specific ISA device. 220 220 221 221 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 222 @param Device Point to device ID instance 222 @param Device Point to device ID instance 223 223 @param Enable Enable/Disable 224 224 … … 238 238 239 239 @param This Point to instance of EFI_ISA_ACPI_PROTOCOL 240 @param Device Point to device ID instance 240 @param Device Point to device ID instance 241 241 242 242 @return EFI_SUCESS Success to initialize. … … 249 249 IN EFI_ISA_ACPI_DEVICE_ID *Device 250 250 ); 251 251 252 252 /** 253 253 Initialize the ISA interface. … … 262 262 IsaInterfaceInit ( 263 263 IN EFI_ISA_ACPI_PROTOCOL *This 264 ); 264 ); 265 265 266 266 /** -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/KbcResetDxe/Reset.inf
r58459 r58466 5 5 # 6 6 # Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> 7 # This program and the accompanying materials 8 # are licensed and made available under the terms and conditions of the BSD License 9 # which accompanies this distribution. The full text of the license may be found at 10 # http://opensource.org/licenses/bsd-license.php 11 # 12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 7 # This program and the accompanying materials 8 # are licensed and made available under the terms and conditions of the BSD License 9 # which accompanies this distribution. The full text of the license may be found at 10 # http://opensource.org/licenses/bsd-license.php 11 # 12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 14 # 15 15 # Module Name: -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/KbcResetDxe/ResetEntry.c
r48674 r58466 3 3 4 4 Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 **/ 13 13 … … 66 66 Initialize the state information for the Reset Architectural Protocol. 67 67 68 @param ImageHandle Handle of the loaded driver 68 @param ImageHandle Handle of the loaded driver 69 69 @param SystemTable Pointer to the System Table 70 70 -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/AcpiTimerLib/AcpiTimerLib.c
r58464 r58466 57 57 58 58 // 59 // ASSERT for the invalid PCD values. They must be configured to the real value. 59 // ASSERT for the invalid PCD values. They must be configured to the real value. 60 60 // 61 61 ASSERT (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0xFFFF); … … 63 63 64 64 // 65 // If the register offset to the BAR for the ACPI I/O Port Base Address is 0x0000, then 65 // If the register offset to the BAR for the ACPI I/O Port Base Address is 0x0000, then 66 66 // no PCI register programming is required to enable access to the the ACPI registers 67 67 // specified by PcdAcpiIoPortBaseAddress … … 72 72 73 73 // 74 // ASSERT for the invalid PCD values. They must be configured to the real value. 74 // ASSERT for the invalid PCD values. They must be configured to the real value. 75 75 // 76 76 ASSERT (PcdGet8 (PcdAcpiIoPciDeviceNumber) != 0xFF); … … 100 100 ); 101 101 } 102 102 103 103 return RETURN_SUCCESS; 104 104 } … … 118 118 { 119 119 UINT16 Port; 120 120 121 121 Port = PcdGet16 (PcdAcpiIoPortBaseAddress); 122 123 // 124 // If the register offset to the BAR for the ACPI I/O Port Base Address is not 0x0000, then 125 // read the PCI register for the ACPI BAR value in case the BAR has been programmed to a 122 123 // 124 // If the register offset to the BAR for the ACPI I/O Port Base Address is not 0x0000, then 125 // read the PCI register for the ACPI BAR value in case the BAR has been programmed to a 126 126 // value other than PcdAcpiIoPortBaseAddress 127 127 // 128 128 if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) != 0x0000) { 129 129 Port = PciRead16 (PCI_LIB_ADDRESS ( 130 PcdGet8 (PcdAcpiIoPciBusNumber), 131 PcdGet8 (PcdAcpiIoPciDeviceNumber), 132 PcdGet8 (PcdAcpiIoPciFunctionNumber), 130 PcdGet8 (PcdAcpiIoPciBusNumber), 131 PcdGet8 (PcdAcpiIoPciDeviceNumber), 132 PcdGet8 (PcdAcpiIoPciFunctionNumber), 133 133 PcdGet16 (PcdAcpiIoPciBarRegisterOffset) 134 134 )); 135 135 } 136 136 137 137 return (Port & PcdGet16 (PcdAcpiIoPortBaseAddressMask)) + PcdGet16 (PcdAcpiPm1TmrOffset); 138 138 } -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
r58464 r58466 28 28 InternalGetPerformanceCounterFrequency ( 29 29 VOID 30 ) 30 ) 31 31 { 32 32 BOOLEAN InterruptState; 33 33 UINT64 Count; 34 34 UINT64 Frequency; 35 35 36 36 InterruptState = SaveAndDisableInterrupts (); 37 37 Count = GetPerformanceCounter (); -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
r58464 r58466 3 3 # 4 4 # Provides basic timer support using the ACPI timer hardware. The performance 5 # counter features are provided by the processors time stamp counter. 5 # counter features are provided by the processors time stamp counter. 6 6 # 7 7 # Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR> … … 29 29 AcpiTimerLib.c 30 30 BaseAcpiTimerLib.c 31 31 32 32 [Packages] 33 33 MdePkg/MdePkg.dec -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
r58464 r58466 33 33 InternalGetPerformanceCounterFrequency ( 34 34 VOID 35 ) 35 ) 36 36 { 37 37 BOOLEAN InterruptState; -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
r58464 r58466 3 3 # 4 4 # Provides basic timer support using the ACPI timer hardware. The performance 5 # counter features are provided by the processors time stamp counter. 5 # counter features are provided by the processors time stamp counter. 6 6 # 7 7 # Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR> -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
r48674 r58466 1 /** @file 1 /** @file 2 2 I/O APIC library. 3 3 … … 31 31 32 32 If Index is >= 0x100, then ASSERT(). 33 33 34 34 @param Index Specifies the I/O APIC register to read. 35 35 … … 51 51 52 52 If Index is >= 0x100, then ASSERT(). 53 53 54 54 @param Index Specifies the I/O APIC register to write. 55 55 @param Value Specifies the value to write to the I/O APIC register specified by Index. … … 72 72 Set the interrupt mask of an I/O APIC interrupt. 73 73 74 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 74 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 75 75 76 76 @param Irq Specifies the I/O APIC interrupt to enable or disable. … … 99 99 /** 100 100 Configures an I/O APIC interrupt. 101 101 102 102 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical 103 mode to the Local APIC of the currntly executing CPU. The default state of the 103 mode to the Local APIC of the currntly executing CPU. The default state of the 104 104 entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must 105 105 be used to enable(unmask) the I/O APIC Interrupt. 106 107 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 106 107 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 108 108 If Vector >= 0x100, then ASSERT(). 109 109 If DeliveryMode is not supported, then ASSERT(). … … 143 143 ASSERT (Vector <= 0xFF); 144 144 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3); 145 145 146 146 Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2); 147 147 Entry.Bits.Vector = (UINT8)Vector; 148 148 Entry.Bits.DeliveryMode = (UINT32)DeliveryMode; 149 Entry.Bits.DestinationMode = 0; 149 Entry.Bits.DestinationMode = 0; 150 150 Entry.Bits.Polarity = AssertionLevel ? 0 : 1; 151 151 Entry.Bits.TriggerMode = LevelTriggered ? 1 : 0; -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
r48674 r58466 53 53 /** 54 54 Initialize the serial device hardware. 55 55 56 56 If no initialization is required, then return RETURN_SUCCESS. 57 57 If the serial device was successfuly initialized, then return RETURN_SUCCESS. 58 58 If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. 59 59 60 60 @retval RETURN_SUCCESS The serial device was initialized. 61 61 @retval RETURN_DEVICE_ERROR The serail device could not be initialized. … … 81 81 // 82 82 Divisor = 115200 / gBps; 83 83 84 84 // 85 85 // Set communications format … … 104 104 105 105 /** 106 Write data from buffer to serial device. 107 108 Writes NumberOfBytes data bytes from Buffer to the serial device. 106 Write data from buffer to serial device. 107 108 Writes NumberOfBytes data bytes from Buffer to the serial device. 109 109 The number of bytes actually written to the serial device is returned. 110 110 If the return value is less than NumberOfBytes, then the write operation failed. 111 111 112 If Buffer is NULL, then ASSERT(). 112 If Buffer is NULL, then ASSERT(). 113 113 114 114 If NumberOfBytes is zero, then return 0. … … 118 118 119 119 @retval 0 NumberOfBytes is 0. 120 @retval >0 The number of bytes written to the serial device. 120 @retval >0 The number of bytes written to the serial device. 121 121 If this value is less than NumberOfBytes, then the read operation failed. 122 122 … … 159 159 160 160 @retval 0 NumberOfBytes is 0. 161 @retval >0 The number of bytes read from the serial device. 161 @retval >0 The number of bytes read from the serial device. 162 162 If this value is less than NumberOfBytes, then the read operation failed. 163 163 -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcAtChipsetPkg.dec
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r58459 r58466 31 31 # 32 32 IoApicLib|Include/Library/IoApicLib.h 33 33 34 34 [Guids] 35 35 gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } } … … 47 47 # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR> 48 48 # 2) If platform install CSM and use thunk module:<BR> 49 # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit 49 # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit 50 50 # should be opened as 0.<BR> 51 51 # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then … … 55 55 # 56 56 # The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely 57 # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to 57 # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to 58 58 # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR> 59 59 # @Prompt 8259 Legacy Mode mask. 60 60 gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001 61 61 62 62 ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller. 63 63 # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered. … … 113 113 # @Prompt Default period of HPET timer. 114 114 gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B 115 115 116 116 ## This PCD specifies the base address of the IO APIC. 117 117 # @Prompt IO APIC base address. … … 125 125 # @Prompt Maximal valid year in RTC. 126 126 gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099|UINT16|0x0000000E 127 127 128 128 [PcdsFixedAtBuild, PcdsPatchableInModule] 129 129 ## Defines the ACPI register set base address. 130 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 130 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 131 131 # @Prompt ACPI Timer IO Port Address 132 132 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010 … … 137 137 138 138 ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers. 139 # The invalid 0xFF is as its default value. It must be configured to the real value. 139 # The invalid 0xFF is as its default value. It must be configured to the real value. 140 140 # @Prompt ACPI Hardware PCI Device Number 141 141 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012 142 142 143 143 ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers. 144 # The invalid 0xFF is as its default value. It must be configured to the real value. 144 # The invalid 0xFF is as its default value. It must be configured to the real value. 145 145 # @Prompt ACPI Hardware PCI Function Number 146 146 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013 147 147 148 148 ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers. 149 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 149 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 150 150 # @Prompt ACPI Hardware PCI Register Offset 151 151 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014 152 152 153 153 ## Defines the bit mask that must be set to enable the APIC hardware register BAR. 154 154 # @Prompt ACPI Hardware PCI Bar Enable BitMask 155 155 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015 156 156 157 157 ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers. 158 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 158 # The invalid 0xFFFF is as its default value. It must be configured to the real value. 159 159 # @Prompt ACPI Hardware PCI Bar Register Offset 160 160 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016 -
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trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcAtChipsetPkg.dsc
r58459 r58466 28 28 BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf 29 29 DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf 30 DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf 30 DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf 31 31 DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf 32 32 IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
r58459 r58466 17 17 /** 18 18 Compare the Hour, Minute and Second of the From time and the To time. 19 19 20 20 Only compare H/M/S in EFI_TIME and ignore other fields here. 21 21 … … 165 165 166 166 Century = RtcRead (RTC_ADDRESS_CENTURY); 167 167 168 168 // 169 169 // Set RTC configuration after get original time … … 178 178 EfiReleaseLock (&Global->RtcLock); 179 179 } 180 180 181 181 // 182 182 // Get the data of Daylight saving and time zone, if they have been … … 196 196 } else { 197 197 Time.TimeZone = EFI_UNSPECIFIED_TIMEZONE; 198 Time.Daylight = 0; 198 Time.Daylight = 0; 199 199 } 200 200 … … 232 232 return EFI_DEVICE_ERROR; 233 233 } 234 234 235 235 // 236 236 // Reset wakeup time value to valid state when wakeup alarm is disabled and wakeup time is invalid. … … 242 242 return EFI_SUCCESS; 243 243 } 244 245 // 246 // When wakeup time is disabled and invalid, reset wakeup time register to valid state 244 245 // 246 // When wakeup time is disabled and invalid, reset wakeup time register to valid state 247 247 // but keep wakeup alarm disabled. 248 248 // … … 273 273 return EFI_DEVICE_ERROR; 274 274 } 275 275 276 276 ConvertEfiTimeToRtcTime (&Time, RegisterB, &Century); 277 277 … … 292 292 return EFI_DEVICE_ERROR; 293 293 } 294 294 295 295 // 296 296 // Inhibit updates of the RTC … … 298 298 RegisterB.Bits.Set = 1; 299 299 RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data); 300 300 301 301 // 302 302 // Set RTC alarm time registers … … 311 311 RegisterB.Bits.Set = 0; 312 312 RtcWrite (RTC_ADDRESS_REGISTER_B, RegisterB.Data); 313 313 314 314 // 315 315 // Release RTC Lock. … … 385 385 386 386 Century = RtcRead (RTC_ADDRESS_CENTURY); 387 387 388 388 // 389 389 // Release RTC Lock. … … 480 480 return Status; 481 481 } 482 482 483 483 // 484 484 // Write timezone and daylight to RTC variable … … 768 768 return EFI_DEVICE_ERROR; 769 769 } 770 770 771 771 // 772 772 // Inhibit updates of the RTC … … 905 905 906 906 @retval EFI_DEVICE_ERROR RTC device error. 907 @retval EFI_SUCCESS RTC is updated and ready. 907 @retval EFI_SUCCESS RTC is updated and ready. 908 908 **/ 909 909 EFI_STATUS … … 1106 1106 /** 1107 1107 Compare the Hour, Minute and Second of the From time and the To time. 1108 1108 1109 1109 Only compare H/M/S in EFI_TIME and ignore other fields here. 1110 1110 … … 1171 1171 ASSERT (From->Month >=1); 1172 1172 ASSERT (From->Month <=12); 1173 1173 1174 1174 if (From->Year == To->Year) { 1175 1175 if (From->Month == To->Month) { -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
r58459 r58466 330 330 331 331 @retval EFI_DEVICE_ERROR RTC device error. 332 @retval EFI_SUCCESS RTC is updated and ready. 332 @retval EFI_SUCCESS RTC is updated and ready. 333 333 **/ 334 334 EFI_STATUS -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
r58459 r58466 60 60 [Depex] 61 61 gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid 62 62 63 63 [Pcd] 64 64 gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout ## CONSUMES -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PciHostBridgeDxe/IoFifo.h
r58464 r58466 7 7 which accompanies this distribution. The full text of the license may be found at 8 8 http://opensource.org/licenses/bsd-license.php 9 9 10 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 **/ 13 **/ 14 14 15 15 #ifndef _IO_FIFO_H_INCLUDED_ -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
r58459 r58466 11 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 **/ 13 **/ 14 14 15 15 #include "PciHostBridge.h" … … 40 40 0 41 41 }, 42 42 43 43 { 44 44 END_DEVICE_PATH_TYPE, … … 104 104 PCI_HOST_BRIDGE_INSTANCE *HostBridge; 105 105 PCI_ROOT_BRIDGE_INSTANCE *PrivateData; 106 106 107 107 mDriverImageHandle = ImageHandle; 108 108 109 109 // 110 110 // Create Host Bridge Device Handle … … 115 115 return EFI_OUT_OF_RESOURCES; 116 116 } 117 117 118 118 HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1]; 119 119 InitializeListHead (&HostBridge->Head); 120 120 121 121 Status = gBS->InstallMultipleProtocolInterfaces ( 122 &HostBridge->HostBridgeHandle, 122 &HostBridge->HostBridgeHandle, 123 123 &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, 124 124 NULL … … 128 128 return EFI_DEVICE_ERROR; 129 129 } 130 130 131 131 // 132 132 // Create Root Bridge Device Handle in this Host Bridge 133 133 // 134 134 135 135 for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) { 136 136 PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE)); … … 143 143 144 144 RootBridgeConstructor ( 145 &PrivateData->Io, 146 HostBridge->HostBridgeHandle, 147 RootBridgeAttribute[Loop1][Loop2], 145 &PrivateData->Io, 146 HostBridge->HostBridgeHandle, 147 RootBridgeAttribute[Loop1][Loop2], 148 148 &mResAppeture[Loop1][Loop2] 149 149 ); 150 150 151 151 Status = gBS->InstallMultipleProtocolInterfaces( 152 &PrivateData->Handle, 152 &PrivateData->Handle, 153 153 &gEfiDevicePathProtocolGuid, PrivateData->DevicePath, 154 154 &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io, … … 159 159 return EFI_DEVICE_ERROR; 160 160 } 161 161 162 162 InsertTailList (&HostBridge->Head, &PrivateData->Link); 163 163 } 164 } 164 } 165 165 166 166 return EFI_SUCCESS; … … 248 248 EFI_STATUS Status; 249 249 EFI_STATUS ReturnStatus; 250 250 251 251 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 252 252 253 253 switch (Phase) { 254 254 … … 256 256 if (HostBridgeInstance->CanRestarted) { 257 257 // 258 // Reset the Each Root Bridge 258 // Reset the Each Root Bridge 259 259 // 260 260 List = HostBridgeInstance->Head.ForwardLink; 261 261 262 262 while (List != &HostBridgeInstance->Head) { 263 263 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); … … 268 268 RootBridgeInstance->ResAllocNode[Index].Status = ResNone; 269 269 } 270 270 271 271 List = List->ForwardLink; 272 272 } 273 273 274 274 HostBridgeInstance->ResourceSubmited = FALSE; 275 275 HostBridgeInstance->CanRestarted = TRUE; … … 277 277 // 278 278 // Can not restart 279 // 279 // 280 280 return EFI_NOT_READY; 281 } 281 } 282 282 break; 283 283 … … 310 310 if (HostBridgeInstance->ResourceSubmited) { 311 311 // 312 // Take care of the resource dependencies between the root bridges 312 // Take care of the resource dependencies between the root bridges 313 313 // 314 314 List = HostBridgeInstance->Head.ForwardLink; … … 318 318 for (Index = TypeIo; Index < TypeBus; Index++) { 319 319 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) { 320 320 321 321 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; 322 322 323 323 // 324 324 // Get the number of '1' in Alignment. 325 325 // 326 326 BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1); 327 327 328 328 switch (Index) { 329 329 330 case TypeIo: 330 case TypeIo: 331 331 // 332 332 // It is impossible for this chipset to align 0xFFFF for IO16 … … 336 336 BitsOfAlignment = 0; 337 337 } 338 338 339 339 Status = gDS->AllocateIoSpace ( 340 EfiGcdAllocateAnySearchBottomUp, 341 EfiGcdIoTypeIo, 340 EfiGcdAllocateAnySearchBottomUp, 341 EfiGcdIoTypeIo, 342 342 BitsOfAlignment, 343 343 AddrLen, … … 346 346 NULL 347 347 ); 348 348 349 349 if (!EFI_ERROR (Status)) { 350 350 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress; 351 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; 351 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; 352 352 } else { 353 ReturnStatus = Status; 353 ReturnStatus = Status; 354 354 if (Status != EFI_OUT_OF_RESOURCES) { 355 355 RootBridgeInstance->ResAllocNode[Index].Length = 0; … … 363 363 // 364 364 // It is impossible for this chipset to align 0xFFFFFFFF for Mem32 365 // So clear it 365 // So clear it 366 366 // 367 367 368 368 if (BitsOfAlignment >= 32) { 369 369 BitsOfAlignment = 0; 370 370 } 371 371 372 372 Status = gDS->AllocateMemorySpace ( 373 EfiGcdAllocateAnySearchBottomUp, 374 EfiGcdMemoryTypeMemoryMappedIo, 373 EfiGcdAllocateAnySearchBottomUp, 374 EfiGcdMemoryTypeMemoryMappedIo, 375 375 BitsOfAlignment, 376 376 AddrLen, … … 379 379 NULL 380 380 ); 381 381 382 382 if (!EFI_ERROR (Status)) { 383 383 // We were able to allocate the PCI memory 384 384 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress; 385 385 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; 386 386 387 387 } else { 388 388 // Not able to allocate enough PCI memory 389 ReturnStatus = Status; 390 389 ReturnStatus = Status; 390 391 391 if (Status != EFI_OUT_OF_RESOURCES) { 392 392 RootBridgeInstance->ResAllocNode[Index].Length = 0; 393 } 393 } 394 394 ASSERT (FALSE); 395 395 } 396 396 break; 397 398 case TypePMem32: 399 case TypeMem64: 397 398 case TypePMem32: 399 case TypeMem64: 400 400 case TypePMem64: 401 401 ReturnStatus = EFI_ABORTED; 402 break; 402 break; 403 403 default: 404 404 ASSERT (FALSE); … … 407 407 } 408 408 } 409 409 410 410 List = List->ForwardLink; 411 411 } 412 412 413 413 return ReturnStatus; 414 414 … … 432 432 switch (Index) { 433 433 434 case TypeIo: 435 Status = gDS->FreeIoSpace (BaseAddress, AddrLen); 434 case TypeIo: 435 Status = gDS->FreeIoSpace (BaseAddress, AddrLen); 436 436 if (EFI_ERROR (Status)) { 437 437 ReturnStatus = Status; … … 453 453 454 454 case TypePMem64: 455 break; 455 break; 456 456 457 457 default: … … 466 466 } 467 467 } 468 468 469 469 List = List->ForwardLink; 470 470 } 471 471 472 472 HostBridgeInstance->ResourceSubmited = FALSE; 473 HostBridgeInstance->CanRestarted = TRUE; 473 HostBridgeInstance->CanRestarted = TRUE; 474 474 return ReturnStatus; 475 475 … … 481 481 return EFI_INVALID_PARAMETER; 482 482 } 483 484 return EFI_SUCCESS; 483 484 return EFI_SUCCESS; 485 485 } 486 486 … … 500 500 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 501 501 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge. 502 502 503 503 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the 504 specific Host bridge and return EFI_SUCCESS. 504 specific Host bridge and return EFI_SUCCESS. 505 505 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge. 506 506 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was … … 514 514 ) 515 515 { 516 BOOLEAN NoRootBridge; 517 LIST_ENTRY *List; 516 BOOLEAN NoRootBridge; 517 LIST_ENTRY *List; 518 518 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 519 519 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; 520 520 521 521 NoRootBridge = TRUE; 522 522 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 523 523 List = HostBridgeInstance->Head.ForwardLink; 524 525 524 525 526 526 while (List != &HostBridgeInstance->Head) { 527 527 NoRootBridge = FALSE; … … 542 542 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); 543 543 *RootBridgeHandle = RootBridgeInstance->Handle; 544 return EFI_SUCCESS; 544 return EFI_SUCCESS; 545 545 } else { 546 546 return EFI_NOT_FOUND; … … 548 548 } 549 549 } 550 550 551 551 List = List->ForwardLink; 552 552 } //end while 553 553 554 554 if (NoRootBridge) { 555 555 return EFI_NOT_FOUND; … … 569 569 GetNextRootBridge(). The attributes are static in the sense that they do not change during or 570 570 after the enumeration process. The hardware may provide mechanisms to change the attributes on 571 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is 571 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is 572 572 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in 573 573 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests. 574 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to 575 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any 574 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to 575 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any 576 576 prefetchable memory. 577 577 Attribute Description … … 591 591 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 592 592 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter 593 593 594 594 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL 595 595 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. … … 605 605 ) 606 606 { 607 LIST_ENTRY *List; 607 LIST_ENTRY *List; 608 608 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 609 609 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; 610 610 611 611 if (Attributes == NULL) { 612 612 return EFI_INVALID_PARAMETER; 613 613 } 614 614 615 615 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 616 616 List = HostBridgeInstance->Head.ForwardLink; 617 617 618 618 while (List != &HostBridgeInstance->Head) { 619 619 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); … … 624 624 List = List->ForwardLink; 625 625 } 626 627 // 628 // RootBridgeHandle is not an EFI_HANDLE 626 627 // 628 // RootBridgeHandle is not an EFI_HANDLE 629 629 // that was returned on a previous call to GetNextRootBridge() 630 630 // … … 641 641 @param[in] RootBridgeHandle The PCI Root Bridge to be set up. 642 642 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor. 643 643 644 644 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle 645 645 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag. … … 655 655 ) 656 656 { 657 LIST_ENTRY *List; 657 LIST_ENTRY *List; 658 658 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 659 659 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; … … 662 662 UINT64 BusStart; 663 663 UINT64 BusEnd; 664 664 665 665 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 666 666 List = HostBridgeInstance->Head.ForwardLink; 667 667 668 668 while (List != &HostBridgeInstance->Head) { 669 669 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); … … 677 677 // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR 678 678 // 679 679 680 680 Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)); 681 681 if (Buffer == NULL) { 682 682 return EFI_OUT_OF_RESOURCES; 683 683 } 684 684 685 685 Temp = (UINT8 *)Buffer; 686 686 687 687 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A; 688 688 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B; 689 689 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2; 690 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0; 690 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0; 691 691 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0; 692 692 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0; 693 693 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart; 694 694 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0; 695 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0; 695 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0; 696 696 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1; 697 697 698 698 Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); 699 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79; 699 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79; 700 700 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0; 701 702 *Configuration = Buffer; 701 702 *Configuration = Buffer; 703 703 return EFI_SUCCESS; 704 704 } 705 705 List = List->ForwardLink; 706 706 } 707 707 708 708 return EFI_INVALID_PARAMETER; 709 709 } … … 719 719 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed 720 720 @param[in] Configuration The pointer to the PCI bus resource descriptor 721 721 722 722 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 723 723 @retval EFI_INVALID_PARAMETER Configuration is NULL. 724 724 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 725 725 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor. 726 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than 726 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than 727 727 bus descriptors. 728 728 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors. … … 741 741 ) 742 742 { 743 LIST_ENTRY *List; 743 LIST_ENTRY *List; 744 744 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 745 745 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; … … 748 748 UINTN BusEnd; 749 749 UINTN BusLen; 750 750 751 751 if (Configuration == NULL) { 752 752 return EFI_INVALID_PARAMETER; 753 753 } 754 754 755 755 Ptr = Configuration; 756 756 757 757 // 758 758 // Check the Configuration is valid … … 761 761 return EFI_INVALID_PARAMETER; 762 762 } 763 763 764 764 if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) { 765 765 return EFI_INVALID_PARAMETER; … … 770 770 return EFI_INVALID_PARAMETER; 771 771 } 772 772 773 773 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 774 774 List = HostBridgeInstance->Head.ForwardLink; 775 775 776 776 Ptr = Configuration; 777 777 778 778 while (List != &HostBridgeInstance->Head) { 779 779 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); … … 782 782 BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen; 783 783 BusEnd = BusStart + BusLen - 1; 784 784 785 785 if (BusStart > BusEnd) { 786 786 return EFI_INVALID_PARAMETER; 787 787 } 788 788 789 789 if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) { 790 790 return EFI_INVALID_PARAMETER; 791 791 } 792 792 793 793 // 794 794 // Update the Bus Range … … 797 797 RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen; 798 798 RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated; 799 799 800 800 // 801 801 // Program the Root Bridge Hardware 802 802 // 803 803 804 804 return EFI_SUCCESS; 805 805 } 806 806 807 807 List = List->ForwardLink; 808 808 } 809 809 810 810 return EFI_INVALID_PARAMETER; 811 811 } … … 823 823 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted. 824 824 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor. 825 825 826 826 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted. 827 827 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 828 828 @retval EFI_INVALID_PARAMETER Configuration is NULL. 829 829 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 830 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are 831 not supported by this PCI root bridge. This error will happen if the caller 830 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are 831 not supported by this PCI root bridge. This error will happen if the caller 832 832 did not combine resources according to Attributes that were returned by 833 833 GetAllocAttributes(). … … 845 845 ) 846 846 { 847 LIST_ENTRY *List; 847 LIST_ENTRY *List; 848 848 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 849 849 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; … … 852 852 UINT64 AddrLen; 853 853 UINT64 Alignment; 854 854 855 855 // 856 856 // Check the input parameter: Configuration … … 859 859 return EFI_INVALID_PARAMETER; 860 860 } 861 861 862 862 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 863 863 List = HostBridgeInstance->Head.ForwardLink; 864 864 865 865 Temp = (UINT8 *)Configuration; 866 while ( *Temp == 0x8A) { 866 while ( *Temp == 0x8A) { 867 867 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; 868 868 } … … 870 870 return EFI_INVALID_PARAMETER; 871 871 } 872 872 873 873 Temp = (UINT8 *)Configuration; 874 874 while (List != &HostBridgeInstance->Head) { … … 891 891 return EFI_INVALID_PARAMETER; 892 892 } 893 893 894 894 switch (Ptr->ResType) { 895 895 896 896 case 0: 897 897 898 898 // 899 899 // Check invalid Address Sapce Granularity … … 902 902 return EFI_INVALID_PARAMETER; 903 903 } 904 904 905 905 // 906 906 // check the memory resource request is supported by PCI root bridge … … 910 910 return EFI_INVALID_PARAMETER; 911 911 } 912 912 913 913 AddrLen = Ptr->AddrLen; 914 914 Alignment = Ptr->AddrRangeMax; … … 922 922 RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen; 923 923 RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment; 924 RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested; 924 RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested; 925 925 HostBridgeInstance->ResourceSubmited = TRUE; 926 926 } … … 942 942 RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment; 943 943 RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested; 944 HostBridgeInstance->ResourceSubmited = TRUE; 944 HostBridgeInstance->ResourceSubmited = TRUE; 945 945 break; 946 946 … … 948 948 break; 949 949 }; 950 950 951 951 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; 952 } 953 952 } 953 954 954 return EFI_SUCCESS; 955 955 } 956 956 957 957 List = List->ForwardLink; 958 958 } 959 959 960 960 return EFI_INVALID_PARAMETER; 961 961 } … … 974 974 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 975 975 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor. 976 976 977 977 @retval EFI_SUCCESS The requested parameters were returned. 978 978 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. … … 989 989 ) 990 990 { 991 LIST_ENTRY *List; 991 LIST_ENTRY *List; 992 992 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 993 993 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; 994 994 UINTN Index; 995 UINTN Number; 996 VOID *Buffer; 995 UINTN Number; 996 VOID *Buffer; 997 997 UINT8 *Temp; 998 998 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; 999 999 UINT64 ResStatus; 1000 1000 1001 1001 Buffer = NULL; 1002 1002 Number = 0; … … 1006 1006 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); 1007 1007 List = HostBridgeInstance->Head.ForwardLink; 1008 1008 1009 1009 // 1010 1010 // Enumerate the root bridges in this host bridge … … 1016 1016 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) { 1017 1017 Number ++; 1018 } 1019 } 1020 1018 } 1019 } 1020 1021 1021 if (Number == 0) { 1022 1022 return EFI_INVALID_PARAMETER; … … 1027 1027 return EFI_OUT_OF_RESOURCES; 1028 1028 } 1029 1029 1030 1030 Temp = Buffer; 1031 1031 for (Index = 0; Index < TypeBus; Index ++) { … … 1033 1033 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ; 1034 1034 ResStatus = RootBridgeInstance->ResAllocNode[Index].Status; 1035 1035 1036 1036 switch (Index) { 1037 1037 … … 1043 1043 Ptr->Len = 0x2B; 1044 1044 Ptr->ResType = 1; 1045 Ptr->GenFlag = 0; 1045 Ptr->GenFlag = 0; 1046 1046 Ptr->SpecificFlag = 0; 1047 1047 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; … … 1055 1055 // 1056 1056 // Memory 32 1057 // 1057 // 1058 1058 Ptr->Desc = 0x8A; 1059 1059 Ptr->Len = 0x2B; 1060 1060 Ptr->ResType = 0; 1061 Ptr->GenFlag = 0; 1061 Ptr->GenFlag = 0; 1062 1062 Ptr->SpecificFlag = 0; 1063 1063 Ptr->AddrSpaceGranularity = 32; … … 1065 1065 Ptr->AddrRangeMax = 0; 1066 1066 Ptr->AddrTranslationOffset = \ 1067 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; 1067 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; 1068 1068 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; 1069 1069 break; … … 1076 1076 Ptr->Len = 0x2B; 1077 1077 Ptr->ResType = 0; 1078 Ptr->GenFlag = 0; 1078 Ptr->GenFlag = 0; 1079 1079 Ptr->SpecificFlag = 6; 1080 1080 Ptr->AddrSpaceGranularity = 32; 1081 1081 Ptr->AddrRangeMin = 0; 1082 1082 Ptr->AddrRangeMax = 0; 1083 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1083 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1084 1084 Ptr->AddrLen = 0; 1085 1085 break; … … 1092 1092 Ptr->Len = 0x2B; 1093 1093 Ptr->ResType = 0; 1094 Ptr->GenFlag = 0; 1094 Ptr->GenFlag = 0; 1095 1095 Ptr->SpecificFlag = 0; 1096 1096 Ptr->AddrSpaceGranularity = 64; 1097 1097 Ptr->AddrRangeMin = 0; 1098 1098 Ptr->AddrRangeMax = 0; 1099 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1099 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1100 1100 Ptr->AddrLen = 0; 1101 1101 break; … … 1108 1108 Ptr->Len = 0x2B; 1109 1109 Ptr->ResType = 0; 1110 Ptr->GenFlag = 0; 1110 Ptr->GenFlag = 0; 1111 1111 Ptr->SpecificFlag = 6; 1112 1112 Ptr->AddrSpaceGranularity = 64; 1113 1113 Ptr->AddrRangeMin = 0; 1114 1114 Ptr->AddrRangeMax = 0; 1115 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1115 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT; 1116 1116 Ptr->AddrLen = 0; 1117 1117 break; 1118 1118 }; 1119 1119 1120 1120 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); 1121 } 1122 } 1123 1124 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79; 1121 } 1122 } 1123 1124 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79; 1125 1125 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0; 1126 1127 *Configuration = Buffer; 1128 1126 1127 *Configuration = Buffer; 1128 1129 1129 return EFI_SUCCESS; 1130 1130 } 1131 1131 1132 1132 List = List->ForwardLink; 1133 1133 } 1134 1134 1135 1135 return EFI_INVALID_PARAMETER; 1136 1136 } … … 1152 1152 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for 1153 1153 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. 1154 @param Phase The phase of the PCI device enumeration. 1155 1154 @param Phase The phase of the PCI device enumeration. 1155 1156 1156 @retval EFI_SUCCESS The requested parameters were returned. 1157 1157 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. … … 1174 1174 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; 1175 1175 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; 1176 LIST_ENTRY *List; 1176 LIST_ENTRY *List; 1177 1177 1178 1178 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.h
r48674 r58466 1 1 /** @file 2 The Header file of the Pci Host Bridge Driver 2 The Header file of the Pci Host Bridge Driver 3 3 4 4 Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR> … … 7 7 which accompanies this distribution. The full text of the license may be found at 8 8 http://opensource.org/licenses/bsd-license.php 9 9 10 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 **/ 13 **/ 14 14 15 15 #ifndef _PCI_HOST_BRIDGE_H_ … … 60 60 UINTN RootBridgeNumber; 61 61 LIST_ENTRY Head; 62 BOOLEAN ResourceSubmited; 63 BOOLEAN CanRestarted; 62 BOOLEAN ResourceSubmited; 63 BOOLEAN CanRestarted; 64 64 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; 65 65 } PCI_HOST_BRIDGE_INSTANCE; … … 67 67 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \ 68 68 CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) 69 69 70 70 // 71 71 // HostBridge Resource Allocation interface … … 158 158 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 159 159 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge. 160 160 161 161 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the 162 specific Host bridge and return EFI_SUCCESS. 162 specific Host bridge and return EFI_SUCCESS. 163 163 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge. 164 164 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was … … 171 171 IN OUT EFI_HANDLE *RootBridgeHandle 172 172 ); 173 173 174 174 /** 175 175 Returns the allocation attributes of a PCI root bridge. … … 182 182 GetNextRootBridge(). The attributes are static in the sense that they do not change during or 183 183 after the enumeration process. The hardware may provide mechanisms to change the attributes on 184 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is 184 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is 185 185 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in 186 186 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests. 187 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to 188 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any 187 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to 188 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any 189 189 prefetchable memory. 190 190 Attribute Description … … 204 204 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 205 205 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter 206 206 207 207 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL 208 208 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. 209 209 @retval EFI_SUCCESS Success to get attribute of interested root bridge. 210 210 211 **/ 211 **/ 212 212 EFI_STATUS 213 213 EFIAPI … … 217 217 OUT UINT64 *Attributes 218 218 ); 219 219 220 220 /** 221 221 Sets up the specified PCI root bridge for the bus enumeration process. … … 227 227 @param[in] RootBridgeHandle The PCI Root Bridge to be set up. 228 228 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor. 229 229 230 230 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle 231 231 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag. … … 240 240 OUT VOID **Configuration 241 241 ); 242 242 243 243 /** 244 244 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range. … … 251 251 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed 252 252 @param[in] Configuration The pointer to the PCI bus resource descriptor 253 253 254 254 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 255 255 @retval EFI_INVALID_PARAMETER Configuration is NULL. 256 256 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 257 257 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor. 258 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than 258 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than 259 259 bus descriptors. 260 260 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors. … … 272 272 IN VOID *Configuration 273 273 ); 274 274 275 275 /** 276 276 Submits the I/O and memory resource requirements for the specified PCI root bridge. … … 284 284 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted. 285 285 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor. 286 286 287 287 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted. 288 288 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 289 289 @retval EFI_INVALID_PARAMETER Configuration is NULL. 290 290 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 291 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are 292 not supported by this PCI root bridge. This error will happen if the caller 291 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are 292 not supported by this PCI root bridge. This error will happen if the caller 293 293 did not combine resources according to Attributes that were returned by 294 294 GetAllocAttributes(). … … 305 305 IN VOID *Configuration 306 306 ); 307 307 308 308 /** 309 309 Returns the proposed resource settings for the specified PCI root bridge. … … 319 319 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 320 320 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor. 321 321 322 322 @retval EFI_SUCCESS The requested parameters were returned. 323 323 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. … … 350 350 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for 351 351 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. 352 @param Phase The phase of the PCI device enumeration. 353 352 @param Phase The phase of the PCI device enumeration. 353 354 354 @retval EFI_SUCCESS The requested parameters were returned. 355 355 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. … … 372 372 373 373 // 374 // Define resource status constant 374 // Define resource status constant 375 375 // 376 376 #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL … … 397 397 typedef struct { 398 398 UINT64 BusBase; 399 UINT64 BusLimit; 400 401 UINT64 MemBase; 402 UINT64 MemLimit; 403 404 UINT64 IoBase; 405 UINT64 IoLimit; 399 UINT64 BusLimit; 400 401 UINT64 MemBase; 402 UINT64 MemLimit; 403 404 UINT64 IoBase; 405 UINT64 IoLimit; 406 406 } PCI_ROOT_BRIDGE_RESOURCE_APPETURE; 407 407 … … 441 441 UINT64 Attributes; 442 442 UINT64 Supports; 443 443 444 444 // 445 445 // Specific for this memory controller: Bus, I/O, Mem 446 446 // 447 447 PCI_RES_NODE ResAllocNode[6]; 448 448 449 449 // 450 450 // Addressing for Memory and I/O and Bus arrange 451 451 // 452 452 UINT64 BusBase; 453 UINT64 MemBase; 454 UINT64 IoBase; 455 UINT64 BusLimit; 456 UINT64 MemLimit; 457 UINT64 IoLimit; 453 UINT64 MemBase; 454 UINT64 IoBase; 455 UINT64 BusLimit; 456 UINT64 MemLimit; 457 UINT64 IoLimit; 458 458 459 459 UINTN PciAddress; 460 460 UINTN PciData; 461 461 462 462 EFI_DEVICE_PATH_PROTOCOL *DevicePath; 463 463 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; -
trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
r58460 r58466 11 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 12 13 **/ 13 **/ 14 14 15 15 #include "PciHostBridge.h" … … 27 27 RESOURCE_CONFIGURATION Configuration = { 28 28 {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0}, 29 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, 29 {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, 30 30 {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0}, 31 31 {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0}, … … 40 40 41 41 /** 42 Polls an address in memory mapped I/O space until an exit condition is met, or 43 a timeout occurs. 42 Polls an address in memory mapped I/O space until an exit condition is met, or 43 a timeout occurs. 44 44 45 45 This function provides a standard way to poll a PCI memory location. A PCI memory read … … 60 60 be of poorer granularity. 61 61 @param[out] Result Pointer to the last value read from the memory location. 62 62 63 63 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 64 64 @retval EFI_INVALID_PARAMETER Width is invalid. … … 70 70 EFI_STATUS 71 71 EFIAPI 72 RootBridgeIoPollMem ( 72 RootBridgeIoPollMem ( 73 73 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 74 74 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, … … 79 79 OUT UINT64 *Result 80 80 ); 81 81 82 82 /** 83 83 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is … … 101 101 be of poorer granularity. 102 102 @param[out] Result Pointer to the last value read from the memory location. 103 103 104 104 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 105 105 @retval EFI_INVALID_PARAMETER Width is invalid. … … 111 111 EFI_STATUS 112 112 EFIAPI 113 RootBridgeIoPollIo ( 113 RootBridgeIoPollIo ( 114 114 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 115 115 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, … … 120 120 OUT UINT64 *Result 121 121 ); 122 122 123 123 /** 124 124 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. … … 137 137 @param[out] Buffer For read operations, the destination buffer to store the results. For 138 138 write operations, the source buffer to write data from. 139 139 140 140 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 141 141 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 170 170 @param[in] Buffer For read operations, the destination buffer to store the results. For 171 171 write operations, the source buffer to write data from. 172 172 173 173 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 174 174 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 197 197 @param[out] UserBuffer For read operations, the destination buffer to store the results. For 198 198 write operations, the source buffer to write data from. 199 199 200 200 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 201 201 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 225 225 @param[in] UserBuffer For read operations, the destination buffer to store the results. For 226 226 write operations, the source buffer to write data from. 227 227 228 228 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 229 229 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 260 260 @param[in] Count The number of memory operations to perform. Bytes moved is 261 261 Width size * Count, starting at DestAddress and SrcAddress. 262 262 263 263 @retval EFI_SUCCESS The data was copied from one memory region to another memory region. 264 264 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 292 292 @param[out] Buffer For read operations, the destination buffer to store the results. For 293 293 write operations, the source buffer to write data from. 294 294 295 295 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 296 296 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 325 325 @param[in] Buffer For read operations, the destination buffer to store the results. For 326 326 write operations, the source buffer to write data from. 327 327 328 328 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 329 329 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 356 356 to access the system memory's HostAddress. 357 357 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete. 358 358 359 359 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 360 360 @retval EFI_INVALID_PARAMETER Operation is invalid. … … 385 385 If the operation was an EfiPciOperationBusMasterWrite or 386 386 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory. 387 Any resources used for the mapping are freed. 387 Any resources used for the mapping are freed. 388 388 389 389 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 390 390 @param[in] Mapping The mapping value returned from Map(). 391 391 392 392 @retval EFI_SUCCESS The range was unmapped. 393 393 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map(). … … 405 405 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or 406 406 EfiPciOperationBusMasterCommonBuffer64 mapping. 407 407 408 408 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 409 409 @param Type This parameter is not used and must be ignored. … … 412 412 @param HostAddress A pointer to store the base system memory address of the allocated range. 413 413 @param Attributes The requested bit mask of attributes for the allocated range. Only 414 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, 414 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, 415 415 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function. 416 416 417 417 @retval EFI_SUCCESS The requested memory pages were allocated. 418 418 @retval EFI_INVALID_PARAMETER MemoryType is invalid. … … 442 442 @param Pages The number of pages to free. 443 443 @param HostAddress The base system memory address of the allocated range. 444 444 445 445 @retval EFI_SUCCESS The requested memory pages were freed. 446 446 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages … … 468 468 469 469 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 470 470 471 471 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host 472 472 bridge to system memory. … … 483 483 /** 484 484 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the 485 attributes that a PCI root bridge is currently using. 485 attributes that a PCI root bridge is currently using. 486 486 487 487 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports … … 493 493 @param Attributes A pointer to the mask of attributes that this PCI root bridge is 494 494 currently using. 495 495 496 496 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root 497 497 bridge supports is returned in Supports. If Attributes is … … 533 533 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the 534 534 attributes specified by Attributes. 535 535 536 536 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. 537 537 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. … … 545 545 IN UINT64 Attributes, 546 546 IN OUT UINT64 *ResourceBase, 547 IN OUT UINT64 *ResourceLength 548 ); 547 IN OUT UINT64 *ResourceLength 548 ); 549 549 550 550 /** … … 565 565 caller must treat the return buffer as read-only data, and the buffer 566 566 must not be freed by the caller. 567 567 568 568 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. 569 569 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. … … 664 664 PrivateData->BusBase = ResAppeture->BusBase; 665 665 PrivateData->BusLimit = ResAppeture->BusLimit; 666 666 667 667 // 668 668 // Specific for this chipset … … 674 674 PrivateData->ResAllocNode[Index].Status = ResNone; 675 675 } 676 676 677 677 PrivateData->PciAddress = 0xCF8; 678 678 PrivateData->PciData = 0xCFC; 679 679 680 680 PrivateData->RootBridgeAttrib = Attri; 681 681 682 682 PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ 683 683 EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ … … 687 687 688 688 Protocol->ParentHandle = HostBridgeHandle; 689 689 690 690 Protocol->PollMem = RootBridgeIoPollMem; 691 691 Protocol->PollIo = RootBridgeIoPollIo; … … 726 726 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO. 727 727 728 The I/O operations are carried out exactly as requested. The caller is responsible 729 for satisfying any alignment and I/O width restrictions that a PI System on a 730 platform might require. For example on some platforms, width requests of 731 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 728 The I/O operations are carried out exactly as requested. The caller is responsible 729 for satisfying any alignment and I/O width restrictions that a PI System on a 730 platform might require. For example on some platforms, width requests of 731 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 732 732 be handled by the driver. 733 733 734 734 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 735 735 @param[in] OperationType I/O operation type: IO/MMIO/PCI. 736 736 @param[in] Width Signifies the width of the I/O or Memory operation. 737 @param[in] Address The base address of the I/O operation. 738 @param[in] Count The number of I/O operations to perform. The number of 737 @param[in] Address The base address of the I/O operation. 738 @param[in] Count The number of I/O operations to perform. The number of 739 739 bytes moved is Width size * Count, starting at Address. 740 740 @param[in] Buffer For read operations, the destination buffer to store the results. … … 745 745 @retval EFI_INVALID_PARAMETER Buffer is NULL. 746 746 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. 747 @retval EFI_UNSUPPORTED The address range specified by Address, Width, 747 @retval EFI_UNSUPPORTED The address range specified by Address, Width, 748 748 and Count is not valid for this PI system. 749 749 … … 806 806 807 807 // 808 // Check to see if any address associated with this transfer exceeds the maximum 808 // Check to see if any address associated with this transfer exceeds the maximum 809 809 // allowed address. The maximum address implied by the parameters passed in is 810 810 // Address + Size * Count. If the following condition is met, then the transfer … … 813 813 // Address + Size * Count > Limit + 1 814 814 // 815 // Since Limit can be the maximum integer value supported by the CPU and Count 815 // Since Limit can be the maximum integer value supported by the CPU and Count 816 816 // can also be the maximum integer value supported by the CPU, this range 817 817 // check must be adjusted to avoid all oveflow conditions. 818 // 819 // The following form of the range check is equivalent but assumes that 818 // 819 // The following form of the range check is equivalent but assumes that 820 820 // Limit is of the form (2^n - 1). 821 821 // … … 853 853 return EFI_UNSUPPORTED; 854 854 } 855 } else { 855 } else { 856 856 MaxCount = RShiftU64 (Limit, Width); 857 857 if (MaxCount < (Count - 1)) { … … 877 877 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For 878 878 write operations, the source buffer to write data from. 879 879 880 880 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 881 881 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 955 955 } 956 956 } 957 return EFI_SUCCESS; 957 return EFI_SUCCESS; 958 958 } 959 959 … … 969 969 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For 970 970 write operations, the source buffer to write data from. 971 971 972 972 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 973 973 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1087 1087 @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For 1088 1088 write operations, the source buffer to write data from. 1089 1089 1090 1090 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1091 1091 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1177 1177 1178 1178 /** 1179 Polls an address in memory mapped I/O space until an exit condition is met, or 1180 a timeout occurs. 1179 Polls an address in memory mapped I/O space until an exit condition is met, or 1180 a timeout occurs. 1181 1181 1182 1182 This function provides a standard way to poll a PCI memory location. A PCI memory read … … 1197 1197 be of poorer granularity. 1198 1198 @param[out] Result Pointer to the last value read from the memory location. 1199 1199 1200 1200 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 1201 1201 @retval EFI_INVALID_PARAMETER Width is invalid. … … 1207 1207 EFI_STATUS 1208 1208 EFIAPI 1209 RootBridgeIoPollMem ( 1209 RootBridgeIoPollMem ( 1210 1210 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 1211 1211 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, … … 1235 1235 if (EFI_ERROR (Status)) { 1236 1236 return Status; 1237 } 1237 } 1238 1238 if ((*Result & Mask) == Value) { 1239 1239 return EFI_SUCCESS; … … 1242 1242 if (Delay == 0) { 1243 1243 return EFI_SUCCESS; 1244 1244 1245 1245 } else { 1246 1246 … … 1259 1259 } 1260 1260 NumberOfTicks += 1; 1261 1261 1262 1262 while (NumberOfTicks != 0) { 1263 1263 1264 1264 mMetronome->WaitForTick (mMetronome, 1); 1265 1265 1266 1266 Status = This->Mem.Read (This, Width, Address, 1, Result); 1267 1267 if (EFI_ERROR (Status)) { 1268 1268 return Status; 1269 1269 } 1270 1270 1271 1271 if ((*Result & Mask) == Value) { 1272 1272 return EFI_SUCCESS; … … 1278 1278 return EFI_TIMEOUT; 1279 1279 } 1280 1280 1281 1281 /** 1282 1282 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is … … 1300 1300 be of poorer granularity. 1301 1301 @param[out] Result Pointer to the last value read from the memory location. 1302 1302 1303 1303 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 1304 1304 @retval EFI_INVALID_PARAMETER Width is invalid. … … 1310 1310 EFI_STATUS 1311 1311 EFIAPI 1312 RootBridgeIoPollIo ( 1312 RootBridgeIoPollIo ( 1313 1313 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, 1314 1314 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, … … 1335 1335 return EFI_INVALID_PARAMETER; 1336 1336 } 1337 1337 1338 1338 Status = This->Io.Read (This, Width, Address, 1, Result); 1339 1339 if (EFI_ERROR (Status)) { 1340 1340 return Status; 1341 } 1341 } 1342 1342 if ((*Result & Mask) == Value) { 1343 1343 return EFI_SUCCESS; … … 1346 1346 if (Delay == 0) { 1347 1347 return EFI_SUCCESS; 1348 1348 1349 1349 } else { 1350 1350 … … 1360 1360 } 1361 1361 NumberOfTicks += 1; 1362 1362 1363 1363 while (NumberOfTicks != 0) { 1364 1364 1365 1365 mMetronome->WaitForTick (mMetronome, 1); 1366 1366 1367 1367 Status = This->Io.Read (This, Width, Address, 1, Result); 1368 1368 if (EFI_ERROR (Status)) { 1369 1369 return Status; 1370 1370 } 1371 1371 1372 1372 if ((*Result & Mask) == Value) { 1373 1373 return EFI_SUCCESS; … … 1396 1396 @param[out] Buffer For read operations, the destination buffer to store the results. For 1397 1397 write operations, the source buffer to write data from. 1398 1398 1399 1399 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1400 1400 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1432 1432 @param[in] Buffer For read operations, the destination buffer to store the results. For 1433 1433 write operations, the source buffer to write data from. 1434 1434 1435 1435 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1436 1436 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1448 1448 ) 1449 1449 { 1450 return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); 1450 return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); 1451 1451 } 1452 1452 … … 1462 1462 @param[out] Buffer For read operations, the destination buffer to store the results. For 1463 1463 write operations, the source buffer to write data from. 1464 1464 1465 1465 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1466 1466 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1479 1479 ) 1480 1480 { 1481 return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); 1481 return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); 1482 1482 } 1483 1483 … … 1493 1493 @param[in] Buffer For read operations, the destination buffer to store the results. For 1494 1494 write operations, the source buffer to write data from. 1495 1495 1496 1496 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1497 1497 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1510 1510 ) 1511 1511 { 1512 return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); 1512 return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); 1513 1513 } 1514 1514 … … 1531 1531 @param[in] Count The number of memory operations to perform. Bytes moved is 1532 1532 Width size * Count, starting at DestAddress and SrcAddress. 1533 1533 1534 1534 @retval EFI_SUCCESS The data was copied from one memory region to another memory region. 1535 1535 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1555 1555 if ((UINT32)Width > EfiPciWidthUint64) { 1556 1556 return EFI_INVALID_PARAMETER; 1557 } 1557 } 1558 1558 1559 1559 if (DestAddress == SrcAddress) { … … 1618 1618 @param[out] Buffer For read operations, the destination buffer to store the results. For 1619 1619 write operations, the source buffer to write data from. 1620 1620 1621 1621 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1622 1622 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1654 1654 @param[in] Buffer For read operations, the destination buffer to store the results. For 1655 1655 write operations, the source buffer to write data from. 1656 1656 1657 1657 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. 1658 1658 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. … … 1688 1688 to access the system memory's HostAddress. 1689 1689 @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete. 1690 1690 1691 1691 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 1692 1692 @retval EFI_INVALID_PARAMETER Operation is invalid. … … 1718 1718 return EFI_INVALID_PARAMETER; 1719 1719 } 1720 1720 1721 1721 // 1722 1722 // Initialize the return values to their defaults … … 1741 1741 // 1742 1742 // Common Buffer operations can not be remapped. If the common buffer 1743 // if above 4GB, then it is not possible to generate a mapping, so return 1743 // if above 4GB, then it is not possible to generate a mapping, so return 1744 1744 // an error. 1745 1745 // … … 1753 1753 // 1754 1754 Status = gBS->AllocatePool ( 1755 EfiBootServicesData, 1756 sizeof(MAP_INFO), 1755 EfiBootServicesData, 1756 sizeof(MAP_INFO), 1757 1757 (VOID **)&MapInfo 1758 1758 ); … … 1780 1780 // 1781 1781 Status = gBS->AllocatePages ( 1782 AllocateMaxAddress, 1783 EfiBootServicesData, 1782 AllocateMaxAddress, 1783 EfiBootServicesData, 1784 1784 MapInfo->NumberOfPages, 1785 1785 &MapInfo->MappedHostAddress … … 1798 1798 if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) { 1799 1799 CopyMem ( 1800 (VOID *)(UINTN)MapInfo->MappedHostAddress, 1800 (VOID *)(UINTN)MapInfo->MappedHostAddress, 1801 1801 (VOID *)(UINTN)MapInfo->HostAddress, 1802 1802 MapInfo->NumberOfBytes … … 1824 1824 If the operation was an EfiPciOperationBusMasterWrite or 1825 1825 EfiPciOperationBusMasterWrite64, the data is committed to the target system memory. 1826 Any resources used for the mapping are freed. 1826 Any resources used for the mapping are freed. 1827 1827 1828 1828 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 1829 1829 @param[in] Mapping The mapping value returned from Map(). 1830 1830 1831 1831 @retval EFI_SUCCESS The range was unmapped. 1832 1832 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map(). … … 1860 1860 if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) { 1861 1861 CopyMem ( 1862 (VOID *)(UINTN)MapInfo->HostAddress, 1862 (VOID *)(UINTN)MapInfo->HostAddress, 1863 1863 (VOID *)(UINTN)MapInfo->MappedHostAddress, 1864 1864 MapInfo->NumberOfBytes … … 1878 1878 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or 1879 1879 EfiPciOperationBusMasterCommonBuffer64 mapping. 1880 1880 1881 1881 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 1882 1882 @param Type This parameter is not used and must be ignored. … … 1885 1885 @param HostAddress A pointer to store the base system memory address of the allocated range. 1886 1886 @param Attributes The requested bit mask of attributes for the allocated range. Only 1887 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, 1887 the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, 1888 1888 and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function. 1889 1889 1890 1890 @retval EFI_SUCCESS The requested memory pages were allocated. 1891 1891 @retval EFI_INVALID_PARAMETER MemoryType is invalid. … … 1923 1923 return EFI_INVALID_PARAMETER; 1924 1924 } 1925 1925 1926 1926 // 1927 1927 // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData … … 1954 1954 @param Pages The number of pages to free. 1955 1955 @param HostAddress The base system memory address of the allocated range. 1956 1956 1957 1957 @retval EFI_SUCCESS The requested memory pages were freed. 1958 1958 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages … … 1983 1983 1984 1984 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. 1985 1985 1986 1986 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host 1987 1987 bridge to system memory. … … 2004 2004 /** 2005 2005 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the 2006 attributes that a PCI root bridge is currently using. 2006 attributes that a PCI root bridge is currently using. 2007 2007 2008 2008 The GetAttributes() function returns the mask of attributes that this PCI root bridge supports … … 2014 2014 @param Attributes A pointer to the mask of attributes that this PCI root bridge is 2015 2015 currently using. 2016 2016 2017 2017 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root 2018 2018 bridge supports is returned in Supports. If Attributes is … … 2042 2042 // 2043 2043 if (Supported != NULL) { 2044 *Supported = PrivateData->Supports; 2044 *Supported = PrivateData->Supports; 2045 2045 } 2046 2046 … … 2048 2048 *Attributes = PrivateData->Attributes; 2049 2049 } 2050 2050 2051 2051 return EFI_SUCCESS; 2052 2052 } … … 2076 2076 @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the 2077 2077 attributes specified by Attributes. 2078 2078 2079 2079 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. 2080 2080 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. … … 2088 2088 IN UINT64 Attributes, 2089 2089 IN OUT UINT64 *ResourceBase, 2090 IN OUT UINT64 *ResourceLength 2090 IN OUT UINT64 *ResourceLength 2091 2091 ) 2092 2092 { 2093 2093 PCI_ROOT_BRIDGE_INSTANCE *PrivateData; 2094 2094 2095 2095 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); 2096 2096 2097 2097 if (Attributes != 0) { 2098 2098 if ((Attributes & (~(PrivateData->Supports))) != 0) { … … 2100 2100 } 2101 2101 } 2102 2102 2103 2103 // 2104 2104 // This is a generic driver for a PC-AT class system. It does not have any 2105 // chipset specific knowlegde, so none of the attributes can be set or 2106 // cleared. Any attempt to set attribute that are already set will succeed, 2105 // chipset specific knowlegde, so none of the attributes can be set or 2106 // cleared. Any attempt to set attribute that are already set will succeed, 2107 2107 // and any attempt to set an attribute that is not supported will fail. 2108 2108 // … … 2131 2131 caller must treat the return buffer as read-only data, and the buffer 2132 2132 must not be freed by the caller. 2133 2133 2134 2134 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. 2135 2135 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. … … 2148 2148 2149 2149 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); 2150 2150 2151 2151 for (Index = 0; Index < TypeMax; Index++) { 2152 2152 if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { … … 2154 2154 Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; 2155 2155 Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; 2156 } 2157 } 2158 2159 *Resources = &Configuration; 2156 } 2157 } 2158 2159 *Resources = &Configuration; 2160 2160 return EFI_SUCCESS; 2161 2161 }
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