VirtualBox

Ignore:
Timestamp:
Oct 29, 2015 4:30:44 AM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
103777
Message:

EFI/Firmware: Merged in the svn:eol-style, svn:mime-type and trailing whitespace cleanup that was done after the initial UDK2014.SP1 import: svn merge /vendor/edk2/UDK2014.SP1 /vendor/edk2/current .

Location:
trunk/src/VBox/Devices/EFI/Firmware
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/Devices/EFI/Firmware

  • trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Library/IoApicLib.h

    r48674 r58466  
    2222
    2323  If Index is >= 0x100, then ASSERT().
    24  
     24
    2525  @param  Index  Specifies the I/O APIC register to read.
    2626
     
    3737
    3838  If Index is >= 0x100, then ASSERT().
    39  
     39
    4040  @param  Index  Specifies the I/O APIC register to write.
    4141  @param  Value  Specifies the value to write to the I/O APIC register specified by Index.
     
    5353  Set the interrupt mask of an I/O APIC interrupt.
    5454
    55   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 
    56  
     55  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
     56
    5757  @param  Irq     Specifies the I/O APIC interrupt to enable or disable.
    5858  @param  Enable  If TRUE, then enable the I/O APIC interrupt specified by Irq.
     
    6868/**
    6969  Configures an I/O APIC interrupt.
    70  
     70
    7171  Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
    72   mode to the Local APIC of the currntly executing CPU.  The default state of the 
     72  mode to the Local APIC of the currntly executing CPU.  The default state of the
    7373  entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must
    7474  be used to enable(unmask) the I/O APIC Interrupt.
    7575
    76   If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). 
     76  If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
    7777  If Vector >= 0x100, then ASSERT().
    7878  If DeliveryMode is not supported, then ASSERT().
  • trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Register/Hpet.h

    r48674 r58466  
    11/** @file
    2   HPET register definitions from the IA-PC HPET (High Precision Event Timers) 
     2  HPET register definitions from the IA-PC HPET (High Precision Event Timers)
    33  Specification, Revision 1.0a, October 2004.
    44
  • trunk/src/VBox/Devices/EFI/Firmware/PcAtChipsetPkg/Include/Register/IoApic.h

    r48674 r58466  
    11/** @file
    2   I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt 
     2  I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt
    33  Controller (IOAPIC), 1996.
    4  
     4
    55  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
    66  This program and the accompanying materials
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