VirtualBox

Ignore:
Timestamp:
Oct 29, 2015 4:30:44 AM (9 years ago)
Author:
vboxsync
Message:

EFI/Firmware: Merged in the svn:eol-style, svn:mime-type and trailing whitespace cleanup that was done after the initial UDK2014.SP1 import: svn merge /vendor/edk2/UDK2014.SP1 /vendor/edk2/current .

Location:
trunk/src/VBox/Devices/EFI/Firmware
Files:
52 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/Firmware

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/Ia32/CpuAsm.S

    r58459 r58466  
    2929ASM_PFX(SetCodeSelector):
    3030    movl    4(%esp), %ecx
    31     subl    $0x10, %esp 
    32     leal    setCodeSelectorLongJump, %eax 
     31    subl    $0x10, %esp
     32    leal    setCodeSelectorLongJump, %eax
    3333    movl    %eax, (%esp)
    3434    movw    %cx, 4(%esp)
    35     .byte   0xFF, 0x2C, 0x24   # jmp *(%esp)  note:(FWORD jmp) 
     35    .byte   0xFF, 0x2C, 0x24   # jmp *(%esp)  note:(FWORD jmp)
    3636setCodeSelectorLongJump:
    37     addl    $0x10, %esp 
     37    addl    $0x10, %esp
    3838    ret
    3939

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/X64/CpuAsm.S

    r58459 r58466  
    1 #      TITLE   CpuAsm.S: 
     1#      TITLE   CpuAsm.S:
    22
    33#------------------------------------------------------------------------------
    … …  
    3030ASM_GLOBAL ASM_PFX(SetCodeSelector)
    3131ASM_PFX(SetCodeSelector):
    32     subq    $0x10, %rsp 
    33     leaq    L_setCodeSelectorLongJump(%rip), %rax 
    34     movq    %rax, (%rsp) 
     32    subq    $0x10, %rsp
     33    leaq    L_setCodeSelectorLongJump(%rip), %rax
     34    movq    %rax, (%rsp)
    3535    movw    %cx, 4(%rsp)
    3636    .byte   0xFF, 0x2C, 0x24     # jmp (%rsp) note:fword jmp

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuDxe/X64/CpuAsm.asm

    r58459 r58466  
    1       TITLE   CpuAsm.asm: 
     1      TITLE   CpuAsm.asm:
    22;------------------------------------------------------------------------------
    33;*
    44;*   Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
    5 ;*   This program and the accompanying materials                         
    6 ;*   are licensed and made available under the terms and conditions of the BSD License         
    7 ;*   which accompanies this distribution.  The full text of the license may be found at       
    8 ;*   http://opensource.org/licenses/bsd-license.php                                           
    9 ;*                                                                                             
    10 ;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 ;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
    12 ;*   
     5;*   This program and the accompanying materials
     6;*   are licensed and made available under the terms and conditions of the BSD License
     7;*   which accompanies this distribution.  The full text of the license may be found at
     8;*   http://opensource.org/licenses/bsd-license.php
     9;*
     10;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     12;*
    1313;*    CpuAsm.asm
    14 ;* 
     14;*
    1515;*   Abstract:
    1616;*

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c

    r58459 r58466  
    33
    44Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    7373  Check parameters to a CPU I/O 2 Protocol service request.
    7474
    75   The I/O operations are carried out exactly as requested. The caller is responsible 
    76   for satisfying any alignment and I/O width restrictions that a PI System on a 
    77   platform might require. For example on some platforms, width requests of 
    78   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
     75  The I/O operations are carried out exactly as requested. The caller is responsible
     76  for satisfying any alignment and I/O width restrictions that a PI System on a
     77  platform might require. For example on some platforms, width requests of
     78  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
    7979  be handled by the driver.
    80  
     80
    8181  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.
    8282  @param[in] Width          Signifies the width of the I/O or Memory operation.
    83   @param[in] Address        The base address of the I/O operation. 
    84   @param[in] Count          The number of I/O operations to perform. The number of 
     83  @param[in] Address        The base address of the I/O operation.
     84  @param[in] Count          The number of I/O operations to perform. The number of
    8585                            bytes moved is Width size * Count, starting at Address.
    8686  @param[in] Buffer         For read operations, the destination buffer to store the results.
    … …  
    9191  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    9292  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    93   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     93  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    9494                                 and Count is not valid for this PI system.
    9595
    … …  
    136136    return EFI_INVALID_PARAMETER;
    137137  }
    138  
     138
    139139  //
    140140  // Check to see if Address is aligned
    … …  
    145145
    146146  //
    147   // Check to see if any address associated with this transfer exceeds the maximum 
     147  // Check to see if any address associated with this transfer exceeds the maximum
    148148  // allowed address.  The maximum address implied by the parameters passed in is
    149149  // Address + Size * Count.  If the following condition is met, then the transfer
    … …  
    152152  //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
    153153  //
    154   // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count 
     154  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
    155155  // can also be the maximum integer value supported by the CPU, this range
    156156  // check must be adjusted to avoid all oveflow conditions.
    157   //   
    158   // The following form of the range check is equivalent but assumes that 
     157  //
     158  // The following form of the range check is equivalent but assumes that
    159159  // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
    160160  //
    … …  
    164164      return EFI_UNSUPPORTED;
    165165    }
    166   } else { 
     166  } else {
    167167    MaxCount = RShiftU64 (Limit, Width);
    168168    if (MaxCount < (Count - 1)) {
    … …  
    188188  Reads memory-mapped registers.
    189189
    190   The I/O operations are carried out exactly as requested. The caller is responsible 
    191   for satisfying any alignment and I/O width restrictions that a PI System on a 
    192   platform might require. For example on some platforms, width requests of 
    193   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
     190  The I/O operations are carried out exactly as requested. The caller is responsible
     191  for satisfying any alignment and I/O width restrictions that a PI System on a
     192  platform might require. For example on some platforms, width requests of
     193  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
    194194  be handled by the driver.
    195  
    196   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    197   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
     195
     196  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     197  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
    198198  each of the Count operations that is performed.
    199  
    200   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    201   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    202   incremented for each of the Count operations that is performed. The read or 
     199
     200  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     201  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     202  incremented for each of the Count operations that is performed. The read or
    203203  write operation is performed Count times on the same Address.
    204  
    205   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    206   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    207   incremented for each of the Count operations that is performed. The read or 
     204
     205  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     206  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     207  incremented for each of the Count operations that is performed. The read or
    208208  write operation is performed Count times from the first element of Buffer.
    209  
     209
    210210  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    211211  @param[in]  Width    Signifies the width of the I/O or Memory operation.
    212   @param[in]  Address  The base address of the I/O operation. 
    213   @param[in]  Count    The number of I/O operations to perform. The number of 
     212  @param[in]  Address  The base address of the I/O operation.
     213  @param[in]  Count    The number of I/O operations to perform. The number of
    214214                       bytes moved is Width size * Count, starting at Address.
    215215  @param[out] Buffer   For read operations, the destination buffer to store the results.
    … …  
    220220  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    221221  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    222   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     222  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    223223                                 and Count is not valid for this PI system.
    224224
    … …  
    268268  Writes memory-mapped registers.
    269269
    270   The I/O operations are carried out exactly as requested. The caller is responsible 
    271   for satisfying any alignment and I/O width restrictions that a PI System on a 
    272   platform might require. For example on some platforms, width requests of 
    273   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
     270  The I/O operations are carried out exactly as requested. The caller is responsible
     271  for satisfying any alignment and I/O width restrictions that a PI System on a
     272  platform might require. For example on some platforms, width requests of
     273  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
    274274  be handled by the driver.
    275  
    276   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    277   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
     275
     276  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     277  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
    278278  each of the Count operations that is performed.
    279  
    280   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    281   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    282   incremented for each of the Count operations that is performed. The read or 
     279
     280  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     281  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     282  incremented for each of the Count operations that is performed. The read or
    283283  write operation is performed Count times on the same Address.
    284  
    285   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    286   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    287   incremented for each of the Count operations that is performed. The read or 
     284
     285  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     286  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     287  incremented for each of the Count operations that is performed. The read or
    288288  write operation is performed Count times from the first element of Buffer.
    289  
     289
    290290  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    291291  @param[in]  Width    Signifies the width of the I/O or Memory operation.
    292   @param[in]  Address  The base address of the I/O operation. 
    293   @param[in]  Count    The number of I/O operations to perform. The number of 
     292  @param[in]  Address  The base address of the I/O operation.
     293  @param[in]  Count    The number of I/O operations to perform. The number of
    294294                       bytes moved is Width size * Count, starting at Address.
    295295  @param[in]  Buffer   For read operations, the destination buffer to store the results.
    … …  
    300300  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    301301  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    302   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     302  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    303303                                 and Count is not valid for this PI system.
    304304
    … …  
    348348  Reads I/O registers.
    349349
    350   The I/O operations are carried out exactly as requested. The caller is responsible 
    351   for satisfying any alignment and I/O width restrictions that a PI System on a 
    352   platform might require. For example on some platforms, width requests of 
    353   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
     350  The I/O operations are carried out exactly as requested. The caller is responsible
     351  for satisfying any alignment and I/O width restrictions that a PI System on a
     352  platform might require. For example on some platforms, width requests of
     353  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
    354354  be handled by the driver.
    355  
    356   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    357   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
     355
     356  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     357  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
    358358  each of the Count operations that is performed.
    359  
    360   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    361   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    362   incremented for each of the Count operations that is performed. The read or 
     359
     360  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     361  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     362  incremented for each of the Count operations that is performed. The read or
    363363  write operation is performed Count times on the same Address.
    364  
    365   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    366   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    367   incremented for each of the Count operations that is performed. The read or 
     364
     365  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     366  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     367  incremented for each of the Count operations that is performed. The read or
    368368  write operation is performed Count times from the first element of Buffer.
    369  
     369
    370370  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    371371  @param[in]  Width    Signifies the width of the I/O or Memory operation.
    372   @param[in]  Address  The base address of the I/O operation. 
    373   @param[in]  Count    The number of I/O operations to perform. The number of 
     372  @param[in]  Address  The base address of the I/O operation.
     373  @param[in]  Count    The number of I/O operations to perform. The number of
    374374                       bytes moved is Width size * Count, starting at Address.
    375375  @param[out] Buffer   For read operations, the destination buffer to store the results.
    … …  
    380380  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    381381  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    382   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     382  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    383383                                 and Count is not valid for this PI system.
    384384
    … …  
    427427  Write I/O registers.
    428428
    429   The I/O operations are carried out exactly as requested. The caller is responsible 
    430   for satisfying any alignment and I/O width restrictions that a PI System on a 
    431   platform might require. For example on some platforms, width requests of 
    432   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
     429  The I/O operations are carried out exactly as requested. The caller is responsible
     430  for satisfying any alignment and I/O width restrictions that a PI System on a
     431  platform might require. For example on some platforms, width requests of
     432  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
    433433  be handled by the driver.
    434  
    435   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    436   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
     434
     435  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     436  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
    437437  each of the Count operations that is performed.
    438  
    439   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    440   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    441   incremented for each of the Count operations that is performed. The read or 
     438
     439  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     440  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     441  incremented for each of the Count operations that is performed. The read or
    442442  write operation is performed Count times on the same Address.
    443  
    444   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    445   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    446   incremented for each of the Count operations that is performed. The read or 
     443
     444  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     445  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     446  incremented for each of the Count operations that is performed. The read or
    447447  write operation is performed Count times from the first element of Buffer.
    448  
     448
    449449  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    450450  @param[in]  Width    Signifies the width of the I/O or Memory operation.
    451   @param[in]  Address  The base address of the I/O operation. 
    452   @param[in]  Count    The number of I/O operations to perform. The number of 
     451  @param[in]  Address  The base address of the I/O operation.
     452  @param[in]  Count    The number of I/O operations to perform. The number of
    453453                       bytes moved is Width size * Count, starting at Address.
    454454  @param[in]  Buffer   For read operations, the destination buffer to store the results.
    … …  
    459459  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    460460  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    461   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     461  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    462462                                 and Count is not valid for this PI system.
    463                                  
     463
    464464**/
    465465EFI_STATUS
    … …  
    502502    }
    503503  }
    504  
     504
    505505  return EFI_SUCCESS;
    506506}
    … …  
    509509  The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
    510510
    511   @param[in] ImageHandle    The firmware allocated handle for the EFI image. 
     511  @param[in] ImageHandle    The firmware allocated handle for the EFI image.
    512512  @param[in] SystemTable    A pointer to the EFI System Table.
    513  
     513
    514514  @retval EFI_SUCCESS       The entry point is executed successfully.
    515515  @retval other             Some error occurs when executing this entry point.

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h

    r48674 r58466  
    33
    44Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    3030  Reads memory-mapped registers.
    3131
    32   The I/O operations are carried out exactly as requested. The caller is responsible 
    33   for satisfying any alignment and I/O width restrictions that a PI System on a 
    34   platform might require. For example on some platforms, width requests of 
    35   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
    36   be handled by the driver.
    37  
    38   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    39   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
    40   each of the Count operations that is performed.
    41  
    42   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    43   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    44   incremented for each of the Count operations that is performed. The read or 
    45   write operation is performed Count times on the same Address.
    46  
    47   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    48   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    49   incremented for each of the Count operations that is performed. The read or 
    50   write operation is performed Count times from the first element of Buffer.
    51  
    52   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    53   @param[in]  Width    Signifies the width of the I/O or Memory operation.
    54   @param[in]  Address  The base address of the I/O operation. 
    55   @param[in]  Count    The number of I/O operations to perform. The number of 
     32  The I/O operations are carried out exactly as requested. The caller is responsible
     33  for satisfying any alignment and I/O width restrictions that a PI System on a
     34  platform might require. For example on some platforms, width requests of
     35  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
     36  be handled by the driver.
     37
     38  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     39  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
     40  each of the Count operations that is performed.
     41
     42  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     43  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     44  incremented for each of the Count operations that is performed. The read or
     45  write operation is performed Count times on the same Address.
     46
     47  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     48  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     49  incremented for each of the Count operations that is performed. The read or
     50  write operation is performed Count times from the first element of Buffer.
     51
     52  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
     53  @param[in]  Width    Signifies the width of the I/O or Memory operation.
     54  @param[in]  Address  The base address of the I/O operation.
     55  @param[in]  Count    The number of I/O operations to perform. The number of
    5656                       bytes moved is Width size * Count, starting at Address.
    5757  @param[out] Buffer   For read operations, the destination buffer to store the results.
    … …  
    6262  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    6363  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    64   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     64  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    6565                                 and Count is not valid for this PI system.
    6666
    … …  
    7979  Writes memory-mapped registers.
    8080
    81   The I/O operations are carried out exactly as requested. The caller is responsible 
    82   for satisfying any alignment and I/O width restrictions that a PI System on a 
    83   platform might require. For example on some platforms, width requests of 
    84   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
    85   be handled by the driver.
    86  
    87   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    88   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
    89   each of the Count operations that is performed.
    90  
    91   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    92   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    93   incremented for each of the Count operations that is performed. The read or 
    94   write operation is performed Count times on the same Address.
    95  
    96   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    97   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    98   incremented for each of the Count operations that is performed. The read or 
    99   write operation is performed Count times from the first element of Buffer.
    100  
    101   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    102   @param[in]  Width    Signifies the width of the I/O or Memory operation.
    103   @param[in]  Address  The base address of the I/O operation. 
    104   @param[in]  Count    The number of I/O operations to perform. The number of 
     81  The I/O operations are carried out exactly as requested. The caller is responsible
     82  for satisfying any alignment and I/O width restrictions that a PI System on a
     83  platform might require. For example on some platforms, width requests of
     84  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
     85  be handled by the driver.
     86
     87  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     88  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
     89  each of the Count operations that is performed.
     90
     91  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     92  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     93  incremented for each of the Count operations that is performed. The read or
     94  write operation is performed Count times on the same Address.
     95
     96  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     97  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     98  incremented for each of the Count operations that is performed. The read or
     99  write operation is performed Count times from the first element of Buffer.
     100
     101  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
     102  @param[in]  Width    Signifies the width of the I/O or Memory operation.
     103  @param[in]  Address  The base address of the I/O operation.
     104  @param[in]  Count    The number of I/O operations to perform. The number of
    105105                       bytes moved is Width size * Count, starting at Address.
    106106  @param[in]  Buffer   For read operations, the destination buffer to store the results.
    … …  
    111111  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    112112  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    113   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     113  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    114114                                 and Count is not valid for this PI system.
    115115
    … …  
    128128  Reads I/O registers.
    129129
    130   The I/O operations are carried out exactly as requested. The caller is responsible 
    131   for satisfying any alignment and I/O width restrictions that a PI System on a 
    132   platform might require. For example on some platforms, width requests of 
    133   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
    134   be handled by the driver.
    135  
    136   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    137   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
    138   each of the Count operations that is performed.
    139  
    140   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    141   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    142   incremented for each of the Count operations that is performed. The read or 
    143   write operation is performed Count times on the same Address.
    144  
    145   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    146   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    147   incremented for each of the Count operations that is performed. The read or 
    148   write operation is performed Count times from the first element of Buffer.
    149  
    150   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    151   @param[in]  Width    Signifies the width of the I/O or Memory operation.
    152   @param[in]  Address  The base address of the I/O operation. 
    153   @param[in]  Count    The number of I/O operations to perform. The number of 
     130  The I/O operations are carried out exactly as requested. The caller is responsible
     131  for satisfying any alignment and I/O width restrictions that a PI System on a
     132  platform might require. For example on some platforms, width requests of
     133  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
     134  be handled by the driver.
     135
     136  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     137  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
     138  each of the Count operations that is performed.
     139
     140  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     141  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     142  incremented for each of the Count operations that is performed. The read or
     143  write operation is performed Count times on the same Address.
     144
     145  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     146  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     147  incremented for each of the Count operations that is performed. The read or
     148  write operation is performed Count times from the first element of Buffer.
     149
     150  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
     151  @param[in]  Width    Signifies the width of the I/O or Memory operation.
     152  @param[in]  Address  The base address of the I/O operation.
     153  @param[in]  Count    The number of I/O operations to perform. The number of
    154154                       bytes moved is Width size * Count, starting at Address.
    155155  @param[out] Buffer   For read operations, the destination buffer to store the results.
    … …  
    160160  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    161161  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    162   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     162  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    163163                                 and Count is not valid for this PI system.
    164164
    … …  
    177177  Write I/O registers.
    178178
    179   The I/O operations are carried out exactly as requested. The caller is responsible 
    180   for satisfying any alignment and I/O width restrictions that a PI System on a 
    181   platform might require. For example on some platforms, width requests of 
    182   EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
    183   be handled by the driver.
    184  
    185   If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
    186   or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
    187   each of the Count operations that is performed.
    188  
    189   If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
    190   EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
    191   incremented for each of the Count operations that is performed. The read or 
    192   write operation is performed Count times on the same Address.
    193  
    194   If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
    195   EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
    196   incremented for each of the Count operations that is performed. The read or 
    197   write operation is performed Count times from the first element of Buffer.
    198  
    199   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
    200   @param[in]  Width    Signifies the width of the I/O or Memory operation.
    201   @param[in]  Address  The base address of the I/O operation. 
    202   @param[in]  Count    The number of I/O operations to perform. The number of 
     179  The I/O operations are carried out exactly as requested. The caller is responsible
     180  for satisfying any alignment and I/O width restrictions that a PI System on a
     181  platform might require. For example on some platforms, width requests of
     182  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
     183  be handled by the driver.
     184
     185  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
     186  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
     187  each of the Count operations that is performed.
     188
     189  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
     190  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
     191  incremented for each of the Count operations that is performed. The read or
     192  write operation is performed Count times on the same Address.
     193
     194  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
     195  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
     196  incremented for each of the Count operations that is performed. The read or
     197  write operation is performed Count times from the first element of Buffer.
     198
     199  @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
     200  @param[in]  Width    Signifies the width of the I/O or Memory operation.
     201  @param[in]  Address  The base address of the I/O operation.
     202  @param[in]  Count    The number of I/O operations to perform. The number of
    203203                       bytes moved is Width size * Count, starting at Address.
    204204  @param[in]  Buffer   For read operations, the destination buffer to store the results.
    … …  
    209209  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    210210  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
    211   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
    212                                  and Count is not valid for this PI system.
    213                                  
     211  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
     212                                 and Count is not valid for this PI system.
     213
    214214**/
    215215EFI_STATUS

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf

    r58459 r58466  
    1919  FILE_GUID                      = A19B1FE7-C1BC-49F8-875F-54A5D542443F
    2020  MODULE_TYPE                    = DXE_DRIVER
    21   VERSION_STRING                 = 1.0 
     21  VERSION_STRING                 = 1.0
    2222  ENTRY_POINT                    = CpuIo2Initialize
    2323
    … …  
    3131  CpuIo2Dxe.c
    3232  CpuIo2Dxe.h
    33  
     33
    3434[Packages]
    3535  MdePkg/MdePkg.dec

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c

    r58459 r58466  
    33
    44Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    4949  @param[in]  MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.
    5050  @param[in]  Width          Signifies the width of the I/O operations.
    51   @param[in]  Address        The base address of the I/O operations.  The caller is 
    52                              responsible for aligning the Address if required. 
     51  @param[in]  Address        The base address of the I/O operations.  The caller is
     52                             responsible for aligning the Address if required.
    5353  @param[in]  Count          The number of I/O operations to perform.
    54   @param[in]  Buffer         For read operations, the destination buffer to store 
    55                              the results.  For write operations, the source buffer 
     54  @param[in]  Buffer         For read operations, the destination buffer to store
     55                             the results.  For write operations, the source buffer
    5656                             from which to write data.
    5757
    … …  
    5959  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    6060  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    61                                  
     61
    6262**/
    6363EFI_STATUS
    … …  
    9393    return EFI_INVALID_PARAMETER;
    9494  }
    95  
    96   //
    97   // Check to see if any address associated with this transfer exceeds the maximum 
     95
     96  //
     97  // Check to see if any address associated with this transfer exceeds the maximum
    9898  // allowed address.  The maximum address implied by the parameters passed in is
    9999  // Address + Size * Count.  If the following condition is met, then the transfer
    … …  
    102102  //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
    103103  //
    104   // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count 
     104  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
    105105  // can also be the maximum integer value supported by the CPU, this range
    106106  // check must be adjusted to avoid all overflow conditions.
    107   //   
    108   // The following form of the range check is equivalent but assumes that 
     107  //
     108  // The following form of the range check is equivalent but assumes that
    109109  // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
    110110  //
    … …  
    114114      return EFI_UNSUPPORTED;
    115115    }
    116   } else { 
     116  } else {
    117117    MaxCount = RShiftU64 (Limit, Width);
    118118    if (MaxCount < (Count - 1)) {
    … …  
    123123    }
    124124  }
    125  
     125
    126126  //
    127127  // Check to see if Address is aligned
    … …  
    137137  Reads memory-mapped registers.
    138138
    139   The I/O operations are carried out exactly as requested.  The caller is 
    140   responsible for any alignment and I/O width issues that the bus, device, 
     139  The I/O operations are carried out exactly as requested.  The caller is
     140  responsible for any alignment and I/O width issues that the bus, device,
    141141  platform, or type of I/O might require.
    142142
    143143  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    144144  @param[in]  Width    Signifies the width of the I/O operations.
    145   @param[in]  Address  The base address of the I/O operations.  The caller is 
    146                        responsible for aligning the Address if required. 
     145  @param[in]  Address  The base address of the I/O operations.  The caller is
     146                       responsible for aligning the Address if required.
    147147  @param[in]  Count    The number of I/O operations to perform.
    148   @param[out] Buffer   For read operations, the destination buffer to store 
    149                        the results.  For write operations, the source buffer 
     148  @param[out] Buffer   For read operations, the destination buffer to store
     149                       the results.  For write operations, the source buffer
    150150                       from which to write data.
    151151
    … …  
    153153  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    154154  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    155   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     155  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    156156                                 lack of resources
    157157
    … …  
    197197  Writes memory-mapped registers.
    198198
    199   The I/O operations are carried out exactly as requested.  The caller is 
    200   responsible for any alignment and I/O width issues that the bus, device, 
     199  The I/O operations are carried out exactly as requested.  The caller is
     200  responsible for any alignment and I/O width issues that the bus, device,
    201201  platform, or type of I/O might require.
    202202
    203203  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    204204  @param[in]  Width    Signifies the width of the I/O operations.
    205   @param[in]  Address  The base address of the I/O operations.  The caller is 
    206                        responsible for aligning the Address if required. 
     205  @param[in]  Address  The base address of the I/O operations.  The caller is
     206                       responsible for aligning the Address if required.
    207207  @param[in]  Count    The number of I/O operations to perform.
    208   @param[in]  Buffer   For read operations, the destination buffer to store 
    209                        the results.  For write operations, the source buffer 
     208  @param[in]  Buffer   For read operations, the destination buffer to store
     209                       the results.  For write operations, the source buffer
    210210                       from which to write data.
    211211
    … …  
    213213  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    214214  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    215   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     215  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    216216                                 lack of resources
    217217
    … …  
    257257  Reads I/O registers.
    258258
    259   The I/O operations are carried out exactly as requested.  The caller is 
    260   responsible for any alignment and I/O width issues that the bus, device, 
     259  The I/O operations are carried out exactly as requested.  The caller is
     260  responsible for any alignment and I/O width issues that the bus, device,
    261261  platform, or type of I/O might require.
    262262
    263263  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    264264  @param[in]  Width    Signifies the width of the I/O operations.
    265   @param[in]  Address  The base address of the I/O operations.  The caller is 
    266                        responsible for aligning the Address if required. 
     265  @param[in]  Address  The base address of the I/O operations.  The caller is
     266                       responsible for aligning the Address if required.
    267267  @param[in]  Count    The number of I/O operations to perform.
    268   @param[out] Buffer   For read operations, the destination buffer to store 
    269                        the results.  For write operations, the source buffer 
     268  @param[out] Buffer   For read operations, the destination buffer to store
     269                       the results.  For write operations, the source buffer
    270270                       from which to write data.
    271271
    … …  
    273273  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    274274  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    275   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     275  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    276276                                 lack of resources
    277277
    … …  
    316316  Write I/O registers.
    317317
    318   The I/O operations are carried out exactly as requested.  The caller is 
    319   responsible for any alignment and I/O width issues that the bus, device, 
     318  The I/O operations are carried out exactly as requested.  The caller is
     319  responsible for any alignment and I/O width issues that the bus, device,
    320320  platform, or type of I/O might require.
    321321
    322322  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    323323  @param[in]  Width    Signifies the width of the I/O operations.
    324   @param[in]  Address  The base address of the I/O operations.  The caller is 
    325                        responsible for aligning the Address if required. 
     324  @param[in]  Address  The base address of the I/O operations.  The caller is
     325                       responsible for aligning the Address if required.
    326326  @param[in]  Count    The number of I/O operations to perform.
    327   @param[in]  Buffer   For read operations, the destination buffer to store 
    328                        the results.  For write operations, the source buffer 
     327  @param[in]  Buffer   For read operations, the destination buffer to store
     328                       the results.  For write operations, the source buffer
    329329                       from which to write data.
    330330
    … …  
    332332  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    333333  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    334   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     334  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    335335                                 lack of resources
    336336
    … …  
    371371    }
    372372  }
    373  
     373
    374374  return EFI_SUCCESS;
    375375}
    … …  
    409409                    );
    410410  ASSERT_EFI_ERROR (Status);
    411  
     411
    412412  return Status;
    413413}

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.h

    r48674 r58466  
    33
    44Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    3131  Reads memory-mapped registers.
    3232
    33   The I/O operations are carried out exactly as requested.  The caller is 
    34   responsible for any alignment and I/O width issues that the bus, device, 
     33  The I/O operations are carried out exactly as requested.  The caller is
     34  responsible for any alignment and I/O width issues that the bus, device,
    3535  platform, or type of I/O might require.
    3636
    3737  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    3838  @param[in]  Width    Signifies the width of the I/O operations.
    39   @param[in]  Address  The base address of the I/O operations.  The caller is 
    40                        responsible for aligning the Address if required. 
     39  @param[in]  Address  The base address of the I/O operations.  The caller is
     40                       responsible for aligning the Address if required.
    4141  @param[in]  Count    The number of I/O operations to perform.
    42   @param[out] Buffer   For read operations, the destination buffer to store 
    43                        the results.  For write operations, the source buffer 
     42  @param[out] Buffer   For read operations, the destination buffer to store
     43                       the results.  For write operations, the source buffer
    4444                       from which to write data.
    4545
    … …  
    4747  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    4848  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    49   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     49  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    5050                                 lack of resources
    5151
    … …  
    6464  Writes memory-mapped registers.
    6565
    66   The I/O operations are carried out exactly as requested.  The caller is 
    67   responsible for any alignment and I/O width issues that the bus, device, 
     66  The I/O operations are carried out exactly as requested.  The caller is
     67  responsible for any alignment and I/O width issues that the bus, device,
    6868  platform, or type of I/O might require.
    6969
    7070  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    7171  @param[in]  Width    Signifies the width of the I/O operations.
    72   @param[in]  Address  The base address of the I/O operations.  The caller is 
    73                        responsible for aligning the Address if required. 
     72  @param[in]  Address  The base address of the I/O operations.  The caller is
     73                       responsible for aligning the Address if required.
    7474  @param[in]  Count    The number of I/O operations to perform.
    75   @param[in]  Buffer   For read operations, the destination buffer to store 
    76                        the results.  For write operations, the source buffer 
     75  @param[in]  Buffer   For read operations, the destination buffer to store
     76                       the results.  For write operations, the source buffer
    7777                       from which to write data.
    7878
    … …  
    8080  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    8181  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    82   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     82  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    8383                                 lack of resources
    8484
    … …  
    9797  Reads I/O registers.
    9898
    99   The I/O operations are carried out exactly as requested.  The caller is 
    100   responsible for any alignment and I/O width issues that the bus, device, 
     99  The I/O operations are carried out exactly as requested.  The caller is
     100  responsible for any alignment and I/O width issues that the bus, device,
    101101  platform, or type of I/O might require.
    102102
    103103  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    104104  @param[in]  Width    Signifies the width of the I/O operations.
    105   @param[in]  Address  The base address of the I/O operations.  The caller is 
    106                        responsible for aligning the Address if required. 
     105  @param[in]  Address  The base address of the I/O operations.  The caller is
     106                       responsible for aligning the Address if required.
    107107  @param[in]  Count    The number of I/O operations to perform.
    108   @param[out] Buffer   For read operations, the destination buffer to store 
    109                        the results.  For write operations, the source buffer 
     108  @param[out] Buffer   For read operations, the destination buffer to store
     109                       the results.  For write operations, the source buffer
    110110                       from which to write data.
    111111
    … …  
    113113  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    114114  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    115   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     115  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    116116                                 lack of resources
    117117
    … …  
    130130  Write I/O registers.
    131131
    132   The I/O operations are carried out exactly as requested.  The caller is 
    133   responsible for any alignment and I/O width issues that the bus, device, 
     132  The I/O operations are carried out exactly as requested.  The caller is
     133  responsible for any alignment and I/O width issues that the bus, device,
    134134  platform, or type of I/O might require.
    135135
    136136  @param[in]  This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
    137137  @param[in]  Width    Signifies the width of the I/O operations.
    138   @param[in]  Address  The base address of the I/O operations.  The caller is 
    139                        responsible for aligning the Address if required. 
     138  @param[in]  Address  The base address of the I/O operations.  The caller is
     139                       responsible for aligning the Address if required.
    140140  @param[in]  Count    The number of I/O operations to perform.
    141   @param[in]  Buffer   For read operations, the destination buffer to store 
    142                        the results.  For write operations, the source buffer 
     141  @param[in]  Buffer   For read operations, the destination buffer to store
     142                       the results.  For write operations, the source buffer
    143143                       from which to write data.
    144144
    … …  
    146146  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
    147147  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
    148   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a 
     148  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a
    149149                                 lack of resources
    150150

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf

    r58459 r58466  
    11## @file
    2 #  Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library. 
     2#  Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.
    33#
    44#  Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
    … …  
    2525# The following information is for reference only and not required by the build tools.
    2626#
    27 #  VALID_ARCHITECTURES           = IA32 X64 
     27#  VALID_ARCHITECTURES           = IA32 X64
    2828#
    2929
    … …  
    3131  CpuIo2Smm.c
    3232  CpuIo2Smm.h
    33  
     33
    3434[Packages]
    3535  MdePkg/MdePkg.dec
    … …  
    4242  SmmServicesTableLib
    4343  BaseMemoryLib
    44  
     44
    4545[Protocols]
    4646  gEfiSmmCpuIo2ProtocolGuid                   ## PRODUCES

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.c

    r58459 r58466  
    33
    44Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    5353  NULL
    5454};
    55  
     55
    5656//
    5757// Lookup table for increment values based on transfer widths
    … …  
    102102  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    103103  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    104   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     104  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    105105                                 and Count is not valid for this EFI system.
    106                                  
     106
    107107**/
    108108EFI_STATUS
    … …  
    147147    return EFI_INVALID_PARAMETER;
    148148  }
    149  
    150   //
    151   // Check to see if any address associated with this transfer exceeds the maximum 
     149
     150  //
     151  // Check to see if any address associated with this transfer exceeds the maximum
    152152  // allowed address.  The maximum address implied by the parameters passed in is
    153153  // Address + Size * Count.  If the following condition is met, then the transfer
    … …  
    156156  //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
    157157  //
    158   // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count 
     158  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
    159159  // can also be the maximum integer value supported by the CPU, this range
    160160  // check must be adjusted to avoid all overflow conditions.
    161   //   
    162   // The following form of the range check is equivalent but assumes that 
     161  //
     162  // The following form of the range check is equivalent but assumes that
    163163  // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
    164164  //
    … …  
    168168      return EFI_UNSUPPORTED;
    169169    }
    170   } else { 
     170  } else {
    171171    MaxCount = RShiftU64 (Limit, Width);
    172172    if (MaxCount < (Count - 1)) {
    … …  
    177177    }
    178178  }
    179  
     179
    180180  return EFI_SUCCESS;
    181181}
    … …  
    195195  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    196196  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    197   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     197  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    198198                                 and Count is not valid for this EFI system.
    199199
    … …  
    269269  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    270270  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    271   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     271  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    272272                                 and Count is not valid for this EFI system.
    273273
    … …  
    343343  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    344344  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    345   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     345  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    346346                                 and Count is not valid for this EFI system.
    347347
    … …  
    412412  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    413413  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    414   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     414  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    415415                                 and Count is not valid for this EFI system.
    416416
    … …  
    466466    }
    467467  }
    468  
     468
    469469  return EFI_SUCCESS;
    470470}
    … …  
    473473  8-bit I/O read operations.
    474474
    475   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     475  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    476476                          by the PEI Foundation.
    477477  @param[in] This         Pointer to local data for the interface.
    … …  
    494494  16-bit I/O read operations.
    495495
    496   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     496  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    497497                          by the PEI Foundation.
    498498  @param[in] This         Pointer to local data for the interface.
    … …  
    516516  32-bit I/O read operations.
    517517
    518   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     518  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    519519                          by the PEI Foundation.
    520520  @param[in] This         Pointer to local data for the interface.
    … …  
    538538  64-bit I/O read operations.
    539539
    540   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     540  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    541541                          by the PEI Foundation.
    542542  @param[in] This         Pointer to local data for the interface.
    … …  
    560560  8-bit I/O write operations.
    561561
    562   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     562  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    563563                          by the PEI Foundation.
    564564  @param[in] This         Pointer to local data for the interface.
    … …  
    582582  16-bit I/O write operations.
    583583
    584   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     584  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    585585                          by the PEI Foundation.
    586586  @param[in] This         Pointer to local data for the interface.
    … …  
    604604  32-bit I/O write operations.
    605605
    606   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     606  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    607607                          by the PEI Foundation.
    608608  @param[in] This         Pointer to local data for the interface.
    … …  
    626626  64-bit I/O write operations.
    627627
    628   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     628  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    629629                          by the PEI Foundation.
    630630  @param[in] This         Pointer to local data for the interface.
    … …  
    648648  8-bit memory read operations.
    649649
    650   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     650  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    651651                          by the PEI Foundation.
    652652  @param[in] This         Pointer to local data for the interface.
    … …  
    670670  16-bit memory read operations.
    671671
    672   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     672  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    673673                          by the PEI Foundation.
    674674  @param[in] This         Pointer to local data for the interface.
    … …  
    692692  32-bit memory read operations.
    693693
    694   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     694  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    695695                          by the PEI Foundation.
    696696  @param[in] This         Pointer to local data for the interface.
    … …  
    714714  64-bit memory read operations.
    715715
    716   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     716  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    717717                          by the PEI Foundation.
    718718  @param[in] This         Pointer to local data for the interface.
    … …  
    736736  8-bit memory write operations.
    737737
    738   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     738  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    739739                          by the PEI Foundation.
    740740  @param[in] This         Pointer to local data for the interface.
    … …  
    758758  16-bit memory write operations.
    759759
    760   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     760  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    761761                          by the PEI Foundation.
    762762  @param[in] This         Pointer to local data for the interface.
    … …  
    780780  32-bit memory write operations.
    781781
    782   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     782  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    783783                          by the PEI Foundation.
    784784  @param[in] This         Pointer to local data for the interface.
    … …  
    802802  64-bit memory write operations.
    803803
    804   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     804  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    805805                          by the PEI Foundation.
    806806  @param[in] This         Pointer to local data for the interface.
    … …  
    827827
    828828  @param[in]  FileHandle   Pointer to image file handle.
    829   @param[in]  PeiServices  Pointer to PEI Services Table   
     829  @param[in]  PeiServices  Pointer to PEI Services Table
    830830
    831831  @retval EFI_SUCCESS  CPU I/O PPI successfully installed
    … …  
    845845  //
    846846  Status = PeiServicesRegisterForShadow (FileHandle);
    847  
     847
    848848  //
    849849  // Make CpuIo pointer in PeiService table point to gCpuIoPpi
    850850  //
    851851  (*((EFI_PEI_SERVICES **)PeiServices))->CpuIo = &gCpuIoPpi;
    852  
     852
    853853  if (Status == EFI_ALREADY_STARTED) {
    854854    //
    … …  
    860860    ASSERT_EFI_ERROR (Status);
    861861  }
    862  
     862
    863863  return EFI_SUCCESS;
    864864}

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.h

    r48674 r58466  
    33
    44Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
    5 This program and the accompanying materials                         
    6 are licensed and made available under the terms and conditions of the BSD License         
    7 which accompanies this distribution.  The full text of the license may be found at       
    8 http://opensource.org/licenses/bsd-license.php                                           
    9                                                                                          
    10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
    11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
     5This program and the accompanying materials
     6are licensed and made available under the terms and conditions of the BSD License
     7which accompanies this distribution.  The full text of the license may be found at
     8http://opensource.org/licenses/bsd-license.php
     9
     10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1212
    1313**/
    … …  
    4141  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    4242  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    43   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     43  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    4444                                 and Count is not valid for this EFI system.
    4545
    … …  
    7070  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    7171  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    72   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     72  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    7373                                 and Count is not valid for this EFI system.
    7474
    … …  
    9999  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    100100  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    101   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     101  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    102102                                 and Count is not valid for this EFI system.
    103103
    … …  
    128128  @retval EFI_INVALID_PARAMETER  Width is invalid for this EFI system.
    129129  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
    130   @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
     130  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
    131131                                 and Count is not valid for this EFI system.
    132132
    … …  
    146146  8-bit I/O read operations.
    147147
    148   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     148  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    149149                          by the PEI Foundation.
    150150  @param[in] This         Pointer to local data for the interface.
    … …  
    164164  16-bit I/O read operations.
    165165
    166   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     166  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    167167                          by the PEI Foundation.
    168168  @param[in] This         Pointer to local data for the interface.
    … …  
    183183  32-bit I/O read operations.
    184184
    185   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     185  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    186186                          by the PEI Foundation.
    187187  @param[in] This         Pointer to local data for the interface.
    … …  
    202202  64-bit I/O read operations.
    203203
    204   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     204  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    205205                          by the PEI Foundation.
    206206  @param[in] This         Pointer to local data for the interface.
    … …  
    221221  8-bit I/O write operations.
    222222
    223   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     223  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    224224                          by the PEI Foundation.
    225225  @param[in] This         Pointer to local data for the interface.
    … …  
    240240  16-bit I/O write operations.
    241241
    242   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     242  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    243243                          by the PEI Foundation.
    244244  @param[in] This         Pointer to local data for the interface.
    … …  
    259259  32-bit I/O write operations.
    260260
    261   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     261  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    262262                          by the PEI Foundation.
    263263  @param[in] This         Pointer to local data for the interface.
    … …  
    278278  64-bit I/O write operations.
    279279
    280   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     280  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    281281                          by the PEI Foundation.
    282282  @param[in] This         Pointer to local data for the interface.
    … …  
    297297  8-bit memory read operations.
    298298
    299   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     299  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    300300                          by the PEI Foundation.
    301301  @param[in] This         Pointer to local data for the interface.
    … …  
    316316  16-bit memory read operations.
    317317
    318   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     318  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    319319                          by the PEI Foundation.
    320320  @param[in] This         Pointer to local data for the interface.
    … …  
    335335  32-bit memory read operations.
    336336
    337   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     337  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    338338                          by the PEI Foundation.
    339339  @param[in] This         Pointer to local data for the interface.
    … …  
    354354  64-bit memory read operations.
    355355
    356   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     356  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    357357                          by the PEI Foundation.
    358358  @param[in] This         Pointer to local data for the interface.
    … …  
    373373  8-bit memory write operations.
    374374
    375   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     375  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    376376                          by the PEI Foundation.
    377377  @param[in] This         Pointer to local data for the interface.
    … …  
    392392  16-bit memory write operations.
    393393
    394   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     394  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    395395                          by the PEI Foundation.
    396396  @param[in] This         Pointer to local data for the interface.
    … …  
    411411  32-bit memory write operations.
    412412
    413   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     413  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    414414                          by the PEI Foundation.
    415415  @param[in] This         Pointer to local data for the interface.
    … …  
    430430  64-bit memory write operations.
    431431
    432   @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
     432  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
    433433                          by the PEI Foundation.
    434434  @param[in] This         Pointer to local data for the interface.
    … …  
    445445  IN  UINT64                      Data
    446446  );
    447  
     447
    448448#endif

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/CpuIoPei/CpuIoPei.inf

    r58459 r58466  
    1919  FILE_GUID                      = AE265864-CF5D-41a8-913D-71C155E76442
    2020  MODULE_TYPE                    = PEIM
    21   VERSION_STRING                 = 1.0 
     21  VERSION_STRING                 = 1.0
    2222  ENTRY_POINT                    = CpuIoInitialize
    2323
    … …  
    3131  CpuIoPei.c
    3232  CpuIoPei.h
    33  
     33
    3434[Packages]
    3535  MdePkg/MdePkg.dec

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Include/Library/LocalApicLib.h

    r58459 r58466  
    8383
    8484  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
    85   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 
     85  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
    8686  the 32-bit local APIC ID is returned as initial APIC ID.
    8787
    … …  
    119119  Send a Fixed IPI to a specified target processor.
    120120
    121   This function returns after the IPI has been accepted by the target processor. 
     121  This function returns after the IPI has been accepted by the target processor.
    122122
    123123  @param  ApicId   The local APIC ID of the target processor.
    … …  
    134134  Send a Fixed IPI to all processors excluding self.
    135135
    136   This function returns after the IPI has been accepted by the target processors. 
     136  This function returns after the IPI has been accepted by the target processors.
    137137
    138138  @param  Vector   The vector number of the interrupt being sent.
    … …  
    147147  Send a SMI IPI to a specified target processor.
    148148
    149   This function returns after the IPI has been accepted by the target processor. 
     149  This function returns after the IPI has been accepted by the target processor.
    150150
    151151  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    160160  Send a SMI IPI to all processors excluding self.
    161161
    162   This function returns after the IPI has been accepted by the target processors. 
     162  This function returns after the IPI has been accepted by the target processors.
    163163**/
    164164VOID
    … …  
    171171  Send an INIT IPI to a specified target processor.
    172172
    173   This function returns after the IPI has been accepted by the target processor. 
     173  This function returns after the IPI has been accepted by the target processor.
    174174
    175175  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    184184  Send an INIT IPI to all processors excluding self.
    185185
    186   This function returns after the IPI has been accepted by the target processors. 
     186  This function returns after the IPI has been accepted by the target processors.
    187187**/
    188188VOID
    … …  
    195195  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
    196196
    197   This function returns after the IPI has been accepted by the target processor. 
     197  This function returns after the IPI has been accepted by the target processor.
    198198
    199199  if StartupRoutine >= 1M, then ASSERT.
    … …  
    214214  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
    215215
    216   This function returns after the IPI has been accepted by the target processors. 
     216  This function returns after the IPI has been accepted by the target processors.
    217217
    218218  if StartupRoutine >= 1M, then ASSERT.
    … …  
    350350
    351351/**
    352   Get the 32-bit address that a device should use to send a Message Signaled 
     352  Get the 32-bit address that a device should use to send a Message Signaled
    353353  Interrupt (MSI) to the Local APIC of the currently executing processor.
    354354
    … …  
    356356**/
    357357UINT32
    358 EFIAPI   
     358EFIAPI
    359359GetApicMsiAddress (
    360360  VOID
    361361  );
    362    
    363 /**
    364   Get the 64-bit data value that a device should use to send a Message Signaled 
     362
     363/**
     364  Get the 64-bit data value that a device should use to send a Message Signaled
    365365  Interrupt (MSI) to the Local APIC of the currently executing processor.
    366366
    367367  If Vector is not in range 0x10..0xFE, then ASSERT().
    368368  If DeliveryMode is not supported, then ASSERT().
    369  
    370   @param  Vector          The 8-bit interrupt vector associated with the MSI. 
     369
     370  @param  Vector          The 8-bit interrupt vector associated with the MSI.
    371371                          Must be in the range 0x10..0xFE
    372   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI 
     372  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
    373373                          is handled.  The only supported values are:
    374374                            0: LOCAL_APIC_DELIVERY_MODE_FIXED
    … …  
    378378                            5: LOCAL_APIC_DELIVERY_MODE_INIT
    379379                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT
    380                          
    381   @param  LevelTriggered  TRUE specifies a level triggered interrupt. 
     380
     381  @param  LevelTriggered  TRUE specifies a level triggered interrupt.
    382382                          FALSE specifies an edge triggered interrupt.
    383383  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
    384                           TRUE specifies a level triggered interrupt that active 
     384                          TRUE specifies a level triggered interrupt that active
    385385                          when the interrupt line is asserted.
    386                           FALSE specifies a level triggered interrupt that active 
     386                          FALSE specifies a level triggered interrupt that active
    387387                          when the interrupt line is deasserted.
    388388
    … …  
    390390**/
    391391UINT64
    392 EFIAPI   
     392EFIAPI
    393393GetApicMsiValue (
    394394  IN UINT8    Vector,
    … …  
    397397  IN BOOLEAN  AssertionLevel
    398398  );
    399  
     399
    400400#endif
    401401

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf

    r58459 r58466  
    99#  which accompanies this distribution.  The full text of the license may be found at
    1010#  http://opensource.org/licenses/bsd-license.php
    11 # 
     11#
    1212#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1313#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    14 # 
     14#
    1515##
    1616
    … …  
    2222  MODULE_TYPE                    = BASE
    2323  VERSION_STRING                 = 1.0
    24   LIBRARY_CLASS                  = UefiCpuLib 
     24  LIBRARY_CLASS                  = UefiCpuLib
    2525
    2626#

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S

    r48674 r58466  
    1414
    1515#
    16 # Float control word initial value: 
     16# Float control word initial value:
    1717# all exceptions masked, double-precision, round-to-nearest
    1818#
    … …  
    4242    finit
    4343    fldcw   ASM_PFX(mFpuControlWord)
    44    
     44
    4545    #
    4646    # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
    … …  
    5151    btl     $25, %edx
    5252    jnc     Done
    53    
     53
    5454    #
    5555    # Set OSFXSR bit 9 in CR4
    5656    #
    57     movl    %cr4, %eax 
     57    movl    %cr4, %eax
    5858    or      $0x200, %eax
    5959    movl    %eax, %cr4
    60    
     60
    6161    #
    6262    # The processor should support SSE instruction and we can use

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm

    r48674 r58466  
    1010;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    1111;*
    12 ;*   
     12;*
    1313;------------------------------------------------------------------------------
    1414
    … …  
    1818    .const
    1919;
    20 ; Float control word initial value: 
     20; Float control word initial value:
    2121; all exceptions masked, double-precision, round-to-nearest
    2222;
    … …  
    2626; all exceptions masked, round-to-nearest, flush to zero for masked underflow
    2727;
    28 mMmxControlWord       DD      01F80h 
     28mMmxControlWord       DD      01F80h
    2929
    3030    .xmm
    … …  
    4848    finit
    4949    fldcw   mFpuControlWord
    50    
     50
    5151    ;
    5252    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
    … …  
    5757    bt      edx, 25
    5858    jnc     Done
    59    
     59
    6060    ;
    6161    ; Set OSFXSR bit 9 in CR4
    … …  
    6464    or      eax, BIT9
    6565    mov     cr4, eax
    66    
     66
    6767    ;
    6868    ; The processor should support SSE instruction and we can use

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.S

    r58459 r58466  
    2828    #
    2929    finit
    30    
     30
    3131    #
    32     # Float control word initial value: 
     32    # Float control word initial value:
    3333    # all exceptions masked, double-precision, round-to-nearest
    3434    #
    3535    pushq   $0x037F
    36     lea     (%rsp), %rax 
     36    lea     (%rsp), %rax
    3737    fldcw   (%rax)
    3838    popq    %rax
    39    
     39
    4040    #
    4141    # Set OSFXSR bit 9 in CR4
    4242    #
    43     movq    %cr4, %rax 
     43    movq    %cr4, %rax
    4444    or      $0x200, %rax
    4545    movq    %rax, %cr4
    … …  
    4848    # Multimedia-extensions control word:
    4949    # all exceptions masked, round-to-nearest, flush to zero for masked underflow
    50     #   
     50    #
    5151    pushq   $0x01F80
    5252    lea     (%rsp), %rax
    5353    ldmxcsr (%rax)
    5454    popq    %rax
    55    
     55
    5656    ret
    5757

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.asm

    r58459 r58466  
    1616.const
    1717;
    18 ; Float control word initial value: 
     18; Float control word initial value:
    1919; all exceptions masked, double-extended-precision, round-to-nearest
    2020;
    … …  
    2424; all exceptions masked, round-to-nearest, flush to zero for masked underflow
    2525;
    26 mMmxControlWord       DD      01F80h 
     26mMmxControlWord       DD      01F80h
    2727
    2828.code
    … …  
    4242    ; Initialize floating point units
    4343    ;
    44     ; The following opcodes stand for instruction 'finit' 
     44    ; The following opcodes stand for instruction 'finit'
    4545    ; to be supported by some 64-bit assemblers
    4646    ;
    4747    DB      9Bh, 0DBh, 0E3h
    4848    fldcw   mFpuControlWord
    49    
     49
    5050    ;
    5151    ; Set OSFXSR bit 9 in CR4
    … …  
    5656
    5757    ldmxcsr mMmxControlWord
    58    
     58
    5959    ret
    6060InitializeFloatingPointUnits ENDP

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

    r58459 r58466  
    4040{
    4141  MSR_IA32_APIC_BASE ApicBaseMsr;
    42  
     42
    4343  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
    44  
     44
    4545  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
    4646           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
    … …  
    128128  Send an IPI by writing to ICR.
    129129
    130   This function returns after the IPI has been accepted by the target processor. 
     130  This function returns after the IPI has been accepted by the target processor.
    131131
    132132  @param  IcrLow 32-bit value to be written to the low half of ICR.
    … …  
    241241
    242242  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
    243   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 
     243  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
    244244  the 32-bit local APIC ID is returned as initial APIC ID.
    245245
    … …  
    264264
    265265  //
    266   // If CPUID Leaf B is supported, 
     266  // If CPUID Leaf B is supported,
    267267  // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
    268268  // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
    … …  
    291291
    292292  ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
    293  
     293
    294294  if ((ApicId = GetInitialApicId ()) < 0x100) {
    295295    //
    … …  
    320320  Send a Fixed IPI to a specified target processor.
    321321
    322   This function returns after the IPI has been accepted by the target processor. 
     322  This function returns after the IPI has been accepted by the target processor.
    323323
    324324  @param  ApicId   The local APIC ID of the target processor.
    … …  
    344344  Send a Fixed IPI to all processors excluding self.
    345345
    346   This function returns after the IPI has been accepted by the target processors. 
     346  This function returns after the IPI has been accepted by the target processors.
    347347
    348348  @param  Vector   The vector number of the interrupt being sent.
    … …  
    367367  Send a SMI IPI to a specified target processor.
    368368
    369   This function returns after the IPI has been accepted by the target processor. 
     369  This function returns after the IPI has been accepted by the target processor.
    370370
    371371  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    388388  Send a SMI IPI to all processors excluding self.
    389389
    390   This function returns after the IPI has been accepted by the target processors. 
     390  This function returns after the IPI has been accepted by the target processors.
    391391**/
    392392VOID
    … …  
    408408  Send an INIT IPI to a specified target processor.
    409409
    410   This function returns after the IPI has been accepted by the target processor. 
     410  This function returns after the IPI has been accepted by the target processor.
    411411
    412412  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    429429  Send an INIT IPI to all processors excluding self.
    430430
    431   This function returns after the IPI has been accepted by the target processors. 
     431  This function returns after the IPI has been accepted by the target processors.
    432432**/
    433433VOID
    … …  
    449449  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
    450450
    451   This function returns after the IPI has been accepted by the target processor. 
     451  This function returns after the IPI has been accepted by the target processor.
    452452
    453453  if StartupRoutine >= 1M, then ASSERT.
    … …  
    484484  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
    485485
    486   This function returns after the IPI has been accepted by the target processors. 
     486  This function returns after the IPI has been accepted by the target processors.
    487487
    488488  if StartupRoutine >= 1M, then ASSERT.
    … …  
    656656    Dcr.Bits.DivideValue1 = (Divisor & 0x3);
    657657    Dcr.Bits.DivideValue2 = (Divisor >> 2);
    658     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); 
     658    WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
    659659  }
    660660
    … …  
    777777
    778778/**
    779   Get the 32-bit address that a device should use to send a Message Signaled 
     779  Get the 32-bit address that a device should use to send a Message Signaled
    780780  Interrupt (MSI) to the Local APIC of the currently executing processor.
    781781
    … …  
    783783**/
    784784UINT32
    785 EFIAPI   
     785EFIAPI
    786786GetApicMsiAddress (
    787787  VOID
    … …  
    791791
    792792  //
    793   // Return address for an MSI interrupt to be delivered only to the APIC ID 
     793  // Return address for an MSI interrupt to be delivered only to the APIC ID
    794794  // of the currently executing processor.
    795795  //
    … …  
    799799  return MsiAddress.Uint32;
    800800}
    801    
    802 /**
    803   Get the 64-bit data value that a device should use to send a Message Signaled 
     801
     802/**
     803  Get the 64-bit data value that a device should use to send a Message Signaled
    804804  Interrupt (MSI) to the Local APIC of the currently executing processor.
    805805
    806806  If Vector is not in range 0x10..0xFE, then ASSERT().
    807807  If DeliveryMode is not supported, then ASSERT().
    808  
    809   @param  Vector          The 8-bit interrupt vector associated with the MSI. 
     808
     809  @param  Vector          The 8-bit interrupt vector associated with the MSI.
    810810                          Must be in the range 0x10..0xFE
    811   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI 
     811  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
    812812                          is handled.  The only supported values are:
    813813                            0: LOCAL_APIC_DELIVERY_MODE_FIXED
    … …  
    817817                            5: LOCAL_APIC_DELIVERY_MODE_INIT
    818818                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT
    819                          
    820   @param  LevelTriggered  TRUE specifies a level triggered interrupt. 
     819
     820  @param  LevelTriggered  TRUE specifies a level triggered interrupt.
    821821                          FALSE specifies an edge triggered interrupt.
    822822  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
    823                           TRUE specifies a level triggered interrupt that active 
     823                          TRUE specifies a level triggered interrupt that active
    824824                          when the interrupt line is asserted.
    825                           FALSE specifies a level triggered interrupt that active 
     825                          FALSE specifies a level triggered interrupt that active
    826826                          when the interrupt line is deasserted.
    827827
    … …  
    829829**/
    830830UINT64
    831 EFIAPI   
     831EFIAPI
    832832GetApicMsiValue (
    833833  IN UINT8    Vector,
    … …  
    841841  ASSERT (Vector >= 0x10 && Vector <= 0xFE);
    842842  ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
    843  
     843
    844844  MsiData.Uint64            = 0;
    845845  MsiData.Bits.Vector       = Vector;

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf

    r58459 r58466  
    1010#  which accompanies this distribution.  The full text of the license may be found at
    1111#  http://opensource.org/licenses/bsd-license.php
    12 # 
     12#
    1313#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1414#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    15 # 
     15#
    1616##
    1717
    … …  
    2323  MODULE_TYPE                    = BASE
    2424  VERSION_STRING                 = 1.0
    25   LIBRARY_CLASS                  = LocalApicLib 
     25  LIBRARY_CLASS                  = LocalApicLib
    2626
    2727#

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c

    r58459 r58466  
    4141{
    4242  MSR_IA32_APIC_BASE ApicBaseMsr;
    43  
     43
    4444  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
    45  
     45
    4646  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
    4747           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
    … …  
    167167  Send an IPI by writing to ICR.
    168168
    169   This function returns after the IPI has been accepted by the target processor. 
     169  This function returns after the IPI has been accepted by the target processor.
    170170
    171171  @param  IcrLow 32-bit value to be written to the low half of ICR.
    … …  
    232232  } else {
    233233    //
    234     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an 
     234    // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
    235235    // interrupt in x2APIC mode.
    236236    //
    … …  
    331331
    332332  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
    333   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 
     333  In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
    334334  the 32-bit local APIC ID is returned as initial APIC ID.
    335335
    … …  
    352352    AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
    353353    //
    354     // If CPUID Leaf B is supported, 
     354    // If CPUID Leaf B is supported,
    355355    // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
    356356    // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
    … …  
    406406  Send a Fixed IPI to a specified target processor.
    407407
    408   This function returns after the IPI has been accepted by the target processor. 
     408  This function returns after the IPI has been accepted by the target processor.
    409409
    410410  @param  ApicId   The local APIC ID of the target processor.
    … …  
    430430  Send a Fixed IPI to all processors excluding self.
    431431
    432   This function returns after the IPI has been accepted by the target processors. 
     432  This function returns after the IPI has been accepted by the target processors.
    433433
    434434  @param  Vector   The vector number of the interrupt being sent.
    … …  
    453453  Send a SMI IPI to a specified target processor.
    454454
    455   This function returns after the IPI has been accepted by the target processor. 
     455  This function returns after the IPI has been accepted by the target processor.
    456456
    457457  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    474474  Send a SMI IPI to all processors excluding self.
    475475
    476   This function returns after the IPI has been accepted by the target processors. 
     476  This function returns after the IPI has been accepted by the target processors.
    477477**/
    478478VOID
    … …  
    494494  Send an INIT IPI to a specified target processor.
    495495
    496   This function returns after the IPI has been accepted by the target processor. 
     496  This function returns after the IPI has been accepted by the target processor.
    497497
    498498  @param  ApicId   Specify the local APIC ID of the target processor.
    … …  
    515515  Send an INIT IPI to all processors excluding self.
    516516
    517   This function returns after the IPI has been accepted by the target processors. 
     517  This function returns after the IPI has been accepted by the target processors.
    518518**/
    519519VOID
    … …  
    535535  Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
    536536
    537   This function returns after the IPI has been accepted by the target processor. 
     537  This function returns after the IPI has been accepted by the target processor.
    538538
    539539  if StartupRoutine >= 1M, then ASSERT.
    … …  
    570570  Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
    571571
    572   This function returns after the IPI has been accepted by the target processors. 
     572  This function returns after the IPI has been accepted by the target processors.
    573573
    574574  if StartupRoutine >= 1M, then ASSERT.
    … …  
    742742    Dcr.Bits.DivideValue1 = (Divisor & 0x3);
    743743    Dcr.Bits.DivideValue2 = (Divisor >> 2);
    744     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); 
     744    WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
    745745  }
    746746
    … …  
    863863
    864864/**
    865   Get the 32-bit address that a device should use to send a Message Signaled 
     865  Get the 32-bit address that a device should use to send a Message Signaled
    866866  Interrupt (MSI) to the Local APIC of the currently executing processor.
    867867
    … …  
    869869**/
    870870UINT32
    871 EFIAPI   
     871EFIAPI
    872872GetApicMsiAddress (
    873873  VOID
    … …  
    877877
    878878  //
    879   // Return address for an MSI interrupt to be delivered only to the APIC ID 
     879  // Return address for an MSI interrupt to be delivered only to the APIC ID
    880880  // of the currently executing processor.
    881881  //
    … …  
    885885  return MsiAddress.Uint32;
    886886}
    887    
    888 /**
    889   Get the 64-bit data value that a device should use to send a Message Signaled 
     887
     888/**
     889  Get the 64-bit data value that a device should use to send a Message Signaled
    890890  Interrupt (MSI) to the Local APIC of the currently executing processor.
    891891
    892892  If Vector is not in range 0x10..0xFE, then ASSERT().
    893893  If DeliveryMode is not supported, then ASSERT().
    894  
    895   @param  Vector          The 8-bit interrupt vector associated with the MSI. 
     894
     895  @param  Vector          The 8-bit interrupt vector associated with the MSI.
    896896                          Must be in the range 0x10..0xFE
    897   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI 
     897  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
    898898                          is handled.  The only supported values are:
    899899                            0: LOCAL_APIC_DELIVERY_MODE_FIXED
    … …  
    903903                            5: LOCAL_APIC_DELIVERY_MODE_INIT
    904904                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT
    905                          
    906   @param  LevelTriggered  TRUE specifies a level triggered interrupt. 
     905
     906  @param  LevelTriggered  TRUE specifies a level triggered interrupt.
    907907                          FALSE specifies an edge triggered interrupt.
    908908  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
    909                           TRUE specifies a level triggered interrupt that active 
     909                          TRUE specifies a level triggered interrupt that active
    910910                          when the interrupt line is asserted.
    911                           FALSE specifies a level triggered interrupt that active 
     911                          FALSE specifies a level triggered interrupt that active
    912912                          when the interrupt line is deasserted.
    913913
    … …  
    915915**/
    916916UINT64
    917 EFIAPI   
     917EFIAPI
    918918GetApicMsiValue (
    919919  IN UINT8    Vector,
    … …  
    927927  ASSERT (Vector >= 0x10 && Vector <= 0xFE);
    928928  ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
    929  
     929
    930930  MsiData.Uint64            = 0;
    931931  MsiData.Bits.Vector       = Vector;

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf

    r58459 r58466  
    1010#  which accompanies this distribution.  The full text of the license may be found at
    1111#  http://opensource.org/licenses/bsd-license.php
    12 # 
     12#
    1313#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1414#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    15 # 
     15#
    1616##
    1717
    … …  
    2323  MODULE_TYPE                    = BASE
    2424  VERSION_STRING                 = 1.0
    25   LIBRARY_CLASS                  = LocalApicLib 
     25  LIBRARY_CLASS                  = LocalApicLib
    2626
    2727#

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c

    r58464 r58466  
    2525
    2626//
    27 // Define the maximum message length 
     27// Define the maximum message length
    2828//
    2929#define MAX_DEBUG_MESSAGE_LENGTH  0x100
    … …  
    3333
    3434  @param  Format      Format string for the message to print.
    35   @param  ...         Variable argument list whose contents are accessed 
     35  @param  ...         Variable argument list whose contents are accessed
    3636                      based on the format string specified by Format.
    3737
    … …  
    5555
    5656  //
    57   // Send the print string to a Serial Port 
     57  // Send the print string to a Serial Port
    5858  //
    5959  SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
    … …  
    6262/**
    6363  Find and display image base address and return image base and its entry point.
    64  
     64
    6565  @param CurrentEip      Current instruction pointer.
    6666  @param EntryPoint      Return module entry point if module header is found.
    67  
     67
    6868  @return !0     Image base address.
    6969  @return 0      Image header cannot be found.
    7070**/
    71 UINTN 
     71UINTN
    7272FindModuleImageBase (
    7373  IN  UINTN              CurrentEip,
    … …  
    122122    //
    123123    // Not found the image base, check the previous aligned address
    124     // 
     124    //
    125125    Pe32Data -= mImageAlignSize;
    126126  }
    … …  
    142142/**
    143143  Read and save reserved vector information
    144  
     144
    145145  @param[in]  VectorInfo        Pointer to reserved vector list.
    146146  @param[out] ReservedVector    Pointer to reserved vector data buffer.
    147147  @param[in]  VectorCount       Vector number to be updated.
    148  
     148
    149149  @return EFI_SUCCESS           Read and save vector info successfully.
    150150  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h

    r58464 r58466  
    8787
    8888  @param  Format      Format string for the message to print.
    89   @param  ...         Variable argument list whose contents are accessed 
     89  @param  ...         Variable argument list whose contents are accessed
    9090                      based on the format string specified by Format.
    9191
    … …  
    100100/**
    101101  Find and display image base address and return image base and its entry point.
    102  
     102
    103103  @param CurrentEip      Current instruction pointer.
    104104  @param EntryPoint      Return module entry point if module header is found.
    105  
     105
    106106  @return !0     Image base address.
    107107  @return 0      Image header cannot be found.
    108108**/
    109 UINTN 
     109UINTN
    110110FindModuleImageBase (
    111111  IN  UINTN              CurrentEip,
    … …  
    129129
    130130  @param[in]  VectorInfo    Pointer to reserved vector list.
    131  
    132   @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
     131
     132  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
    133133                                with default exception handlers.
    134134  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    188188ArchSaveExceptionContext (
    189189  IN UINTN                ExceptionType,
    190   IN EFI_SYSTEM_CONTEXT   SystemContext 
     190  IN EFI_SYSTEM_CONTEXT   SystemContext
    191191  );
    192192
    … …  
    201201ArchRestoreExceptionContext (
    202202  IN UINTN                ExceptionType,
    203   IN EFI_SYSTEM_CONTEXT   SystemContext 
     203  IN EFI_SYSTEM_CONTEXT   SystemContext
    204204  );
    205205
    206206/**
    207207  Fix up the vector number and function address in the vector code.
    208  
     208
    209209  @param[in] NewVectorAddr   New vector handler address.
    210210  @param[in] VectorNum       Index of vector.
    … …  
    222222/**
    223223  Read and save reserved vector information
    224  
     224
    225225  @param[in]  VectorInfo        Pointer to reserved vector list.
    226226  @param[out] ReservedVector    Pointer to reserved vector data buffer.
    227227  @param[in]  VectorCount       Vector number to be updated.
    228  
     228
    229229  @return EFI_SUCCESS           Read and save vector info successfully.
    230230  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf

    r58464 r58466  
    77#  which accompanies this distribution.  The full text of the license may be found at
    88#  http://opensource.org/licenses/bsd-license.php
    9 # 
     9#
    1010#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1111#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    12 # 
     12#
    1313##
    1414
    … …  
    5757  SynchronizationLib
    5858  LocalApicLib
    59   PeCoffGetEntryPointLib 
     59  PeCoffGetEntryPointLib
    6060  MemoryAllocationLib
    6161  DebugLib

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c

    r58464 r58466  
    2525/**
    2626  Initializes all CPU exceptions entries and provides the default exception handlers.
    27  
     27
    2828  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    2929  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    30   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     30  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    3131  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    3232
    3333  @param[in]  VectorInfo    Pointer to reserved vector list.
    34  
    35   @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
     34
     35  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
    3636                                with default exception handlers.
    3737  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    5050/**
    5151  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
    52  
     52
    5353  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    5454  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    55   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     55  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    5656  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    5757
    5858  @param[in]  VectorInfo    Pointer to reserved vector list.
    59  
    60   @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
     59
     60  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized
    6161                                with default interrupt/exception handlers.
    6262  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    112112  InterruptEntryCode = AllocatePool (TemplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NUM);
    113113  ASSERT (InterruptEntryCode != NULL);
    114  
     114
    115115  InterruptEntry = (UINTN) InterruptEntryCode;
    116116  for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) {
    … …  
    140140  Registers a function to be called from the processor interrupt handler.
    141141
    142   This function registers and enables the handler specified by InterruptHandler for a processor 
    143   interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
    144   handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
     142  This function registers and enables the handler specified by InterruptHandler for a processor
     143  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
     144  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
    145145  The installed handler is called once for each processor interrupt or exception.
    146146  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeSmmCpuException.c

    r58464 r58466  
    4040EFIAPI
    4141CommonExceptionHandler (
    42   IN EFI_EXCEPTION_TYPE          ExceptionType, 
     42  IN EFI_EXCEPTION_TYPE          ExceptionType,
    4343  IN EFI_SYSTEM_CONTEXT          SystemContext
    4444  )
    … …  
    9898    break;
    9999  }
    100  
     100
    101101  if (mExternalInterruptHandler[ExceptionType] != NULL) {
    102102    (mExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
    … …  
    110110    //
    111111    // Display ExceptionType, CPU information and Image information
    112     // 
     112    //
    113113    DumpCpuContent (ExceptionType, SystemContext);
    114114    //
    … …  
    192192    }
    193193  }
    194  
     194
    195195  //
    196196  // Save Interrupt number to global variable used for RegisterCpuInterruptHandler ()
    … …  
    203203
    204204  @param[in]  VectorInfo    Pointer to reserved vector list.
    205  
    206   @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
     205
     206  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
    207207                                with default exception handlers.
    208208  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c

    r58464 r58466  
    5858ArchSaveExceptionContext (
    5959  IN UINTN                ExceptionType,
    60   IN EFI_SYSTEM_CONTEXT   SystemContext 
     60  IN EFI_SYSTEM_CONTEXT   SystemContext
    6161  )
    6262{
    … …  
    7373  //
    7474  Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
    75   Eflags.Bits.IF = 0; 
     75  Eflags.Bits.IF = 0;
    7676  SystemContext.SystemContextIa32->Eflags = Eflags.UintN;
    7777  //
    … …  
    9090ArchRestoreExceptionContext (
    9191  IN UINTN                ExceptionType,
    92   IN EFI_SYSTEM_CONTEXT   SystemContext 
     92  IN EFI_SYSTEM_CONTEXT   SystemContext
    9393  )
    9494{

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.S

    r58464 r58466  
    358358    # Put Vector Number on stack and restore ECX
    359359    #
    360     xchgl   (%esp), %ecx 
     360    xchgl   (%esp), %ecx
    361361
    362362ErrorCodeAndVectorOnStack:
    … …  
    385385    # is 16-byte aligned
    386386    #
    387     andl    $0x0fffffff0, %esp 
     387    andl    $0x0fffffff0, %esp
    388388    subl    $12, %esp
    389389
    … …  
    391391    pushl   $0         # check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
    392392    pushl   $0         # check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
    393        
     393
    394394#; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
    395395    pushl   %eax
    … …  
    406406    movl    %ss, %eax
    407407    pushl   %eax
    408     movzwl  16(%ebp), %eax 
     408    movzwl  16(%ebp), %eax
    409409    pushl   %eax
    410410    movl    %ds, %eax
    … …  
    426426    movl    2(%esp), %eax
    427427    xchgl   (%esp), %eax
    428     andl    $0x0FFFF, %eax 
     428    andl    $0x0FFFF, %eax
    429429    movl    %eax, 4(%esp)
    430430
    … …  
    433433    movl    2(%esp), %eax
    434434    xchgl   (%esp), %eax
    435     andl    $0x0FFFF, %eax 
     435    andl    $0x0FFFF, %eax
    436436    movl    %eax, 4(%esp)
    437437
    … …  
    588588# _AsmGetTemplateAddressMap             ;
    589589#---------------------------------------;
    590 # 
     590#
    591591# Protocol prototype
    592592#   AsmGetTemplateAddressMap (
    593593#     EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
    594594#   );
    595 #           
     595#
    596596# Routine Description:
    597 # 
     597#
    598598#  Return address map of interrupt handler template so that C code can generate
    599599#  interrupt table.
    600 # 
     600#
    601601# Arguments:
    602 # 
    603 # 
    604 # Returns: 
    605 # 
     602#
     603#
     604# Returns:
     605#
    606606#   Nothing
    607607#
    608 # 
     608#
    609609# Input:  [ebp][0]  = Original ebp
    610610#         [ebp][4]  = Return address
    611 #         
     611#
    612612# Output: Nothing
    613 #         
     613#
    614614# Destroys: Nothing
    615615#-----------------------------------------------------------------------------;

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.asm

    r58464 r58466  
    5454    db      6ah        ; push
    5555VectorNum:
    56     db      0          ; 0 will be fixed 
     56    db      0          ; 0 will be fixed
    5757    push    eax
    5858    mov     eax, HookAfterStubHeaderEnd
    … …  
    194194    push    0            ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
    195195    push    0            ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
    196        
     196
    197197;; UINT32  Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
    198198    push    eax
    … …  
    374374    jmp     dword ptr [esp - 12]
    375375
    376 DoReturn:   
     376DoReturn:
    377377    cmp     mDoFarReturnFlag, 0   ; Check if need to do far return instead of IRET
    378378    jz      DoIret
    … …  
    393393; _AsmGetTemplateAddressMap                  ;
    394394;----------------------------------------------------------------------------;
    395 ; 
     395;
    396396; Protocol prototype
    397397;   AsmGetTemplateAddressMap (
    398398;     EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
    399399;   );
    400 ;           
     400;
    401401; Routine Description:
    402 ; 
     402;
    403403;  Return address map of interrupt handler template so that C code can generate
    404404;  interrupt table.
    405 ; 
     405;
    406406; Arguments:
    407 ; 
    408 ; 
    409 ; Returns: 
    410 ; 
     407;
     408;
     409; Returns:
     410;
    411411;   Nothing
    412412;
    413 ; 
     413;
    414414; Input:  [ebp][0]  = Original ebp
    415415;         [ebp][4]  = Return address
    416 ;         
     416;
    417417; Output: Nothing
    418 ;           
     418;
    419419; Destroys: Nothing
    420420;-----------------------------------------------------------------------------;
    … …  
    428428    mov dword ptr [ebx + 4h], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
    429429    mov dword ptr [ebx + 8h], HookAfterStubBegin
    430  
     430
    431431    popad
    432432    pop     ebp

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c

    r58464 r58466  
    3131EFIAPI
    3232CommonExceptionHandler (
    33   IN EFI_EXCEPTION_TYPE   ExceptionType, 
     33  IN EFI_EXCEPTION_TYPE   ExceptionType,
    3434  IN EFI_SYSTEM_CONTEXT   SystemContext
    3535  )
    … …  
    3737  //
    3838  // Display ExceptionType, CPU information and Image information
    39   // 
     39  //
    4040  DumpCpuContent (ExceptionType, SystemContext);
    41  
     41
    4242  //
    4343  // Enter a dead loop.
    … …  
    4848/**
    4949  Initializes all CPU exceptions entries and provides the default exception handlers.
    50  
     50
    5151  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    5252  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    53   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     53  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    5454  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    55   Note: Before invoking this API, caller must allocate memory for IDT table and load 
     55  Note: Before invoking this API, caller must allocate memory for IDT table and load
    5656        IDTR by AsmWriteIdtr().
    5757
    5858  @param[in]  VectorInfo    Pointer to reserved vector list.
    59  
    60   @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
     59
     60  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
    6161                                with default exception handlers.
    6262  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    7070  )
    7171{
    72   EFI_STATUS                       Status; 
     72  EFI_STATUS                       Status;
    7373  RESERVED_VECTORS_DATA            ReservedVectorData[CPU_EXCEPTION_NUM];
    7474  IA32_DESCRIPTOR                  IdtDescriptor;
    … …  
    127127/**
    128128  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
    129  
     129
    130130  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    131131  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    132   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     132  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    133133  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    134134
    135135  @param[in]  VectorInfo    Pointer to reserved vector list.
    136  
    137   @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
     136
     137  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized
    138138                                with default interrupt/exception handlers.
    139139  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    153153  Registers a function to be called from the processor interrupt handler.
    154154
    155   This function registers and enables the handler specified by InterruptHandler for a processor 
    156   interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
    157   handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
     155  This function registers and enables the handler specified by InterruptHandler for a processor
     156  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
     157  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
    158158  The installed handler is called once for each processor interrupt or exception.
    159159  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf

    r58464 r58466  
    77#  which accompanies this distribution.  The full text of the license may be found at
    88#  http://opensource.org/licenses/bsd-license.php
    9 # 
     9#
    1010#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1111#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    12 # 
     12#
    1313##
    1414

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf

    r58464 r58466  
    77#  which accompanies this distribution.  The full text of the license may be found at
    88#  http://opensource.org/licenses/bsd-license.php
    9 # 
     9#
    1010#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1111#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    12 # 
     12#
    1313##
    1414

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c

    r58464 r58466  
    1616#include "CpuExceptionCommon.h"
    1717
    18 CONST UINTN   mDoFarReturnFlag   = 1; 
     18CONST UINTN   mDoFarReturnFlag   = 1;
    1919
    2020/**
    2121  Initializes all CPU exceptions entries and provides the default exception handlers.
    22  
     22
    2323  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    2424  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    25   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     25  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    2626  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    2727
    2828  @param[in]  VectorInfo    Pointer to reserved vector list.
    29  
    30   @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized 
     29
     30  @retval EFI_SUCCESS           CPU Exception Entries have been successfully initialized
    3131                                with default exception handlers.
    3232  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    4545/**
    4646  Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
    47  
     47
    4848  Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
    4949  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
    50   If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. 
     50  If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
    5151  If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
    5252
    5353  @param[in]  VectorInfo    Pointer to reserved vector list.
    54  
    55   @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized 
     54
     55  @retval EFI_SUCCESS           All CPU interrupt/exception entries have been successfully initialized
    5656                                with default interrupt/exception handlers.
    5757  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
    … …  
    7171  Registers a function to be called from the processor interrupt handler.
    7272
    73   This function registers and enables the handler specified by InterruptHandler for a processor 
    74   interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
    75   handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
     73  This function registers and enables the handler specified by InterruptHandler for a processor
     74  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
     75  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
    7676  The installed handler is called once for each processor interrupt or exception.
    7777  NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c

    r58464 r58466  
    3030  IdtEntry->Bits.OffsetLow   = (UINT16)(UINTN)InterruptHandler;
    3131  IdtEntry->Bits.OffsetHigh  = (UINT16)((UINTN)InterruptHandler >> 16);
    32   IdtEntry->Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32); 
     32  IdtEntry->Bits.OffsetUpper = (UINT32)((UINTN)InterruptHandler >> 32);
    3333  IdtEntry->Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;
    3434}
    … …  
    5858ArchSaveExceptionContext (
    5959  IN UINTN                ExceptionType,
    60   IN EFI_SYSTEM_CONTEXT   SystemContext 
     60  IN EFI_SYSTEM_CONTEXT   SystemContext
    6161  )
    6262{
    … …  
    7575  //
    7676  Eflags.UintN = SystemContext.SystemContextX64->Rflags;
    77   Eflags.Bits.IF = 0; 
     77  Eflags.Bits.IF = 0;
    7878  SystemContext.SystemContextX64->Rflags = Eflags.UintN;
    7979  //
    … …  
    9292ArchRestoreExceptionContext (
    9393  IN UINTN                ExceptionType,
    94   IN EFI_SYSTEM_CONTEXT   SystemContext 
     94  IN EFI_SYSTEM_CONTEXT   SystemContext
    9595  )
    9696{

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.S

    r58464 r58466  
    3030
    3131#ifdef __APPLE__
    32 # macros are different between GNU and Xcode as. 
    33 .macro IDT_MACRO 
     32# macros are different between GNU and Xcode as.
     33.macro IDT_MACRO
    3434  push     $0
    3535#else
    … …  
    7878    .byte   0x6a      # push
    7979PatchVectorNum:
    80     .byte   0         # 0 will be fixed 
     80    .byte   0         # 0 will be fixed
    8181    .byte   0xe9      # jmp     ASM_PFX(HookAfterStubHeaderEnd)
    8282PatchFuncAddress:
    … …  
    234234    pushq   %rax
    235235    movq    %cr4, %rax
    236     orq     $0x208, %rax 
    237     movq    %rax, %cr4 
    238     pushq   %rax
    239     mov     %cr3, %rax 
    240     pushq   %rax
    241     mov     %cr2, %rax 
     236    orq     $0x208, %rax
     237    movq    %rax, %cr4
     238    pushq   %rax
     239    mov     %cr3, %rax
     240    pushq   %rax
     241    mov     %cr2, %rax
    242242    pushq   %rax
    243243    xorq    %rax, %rax
    244244    pushq   %rax
    245     mov     %cr0, %rax 
     245    mov     %cr0, %rax
    246246    pushq   %rax
    247247
    … …  
    278278    # and make sure RSP is 16-byte aligned
    279279    #
    280     subq    $40, %rsp 
     280    subq    $40, %rsp
    281281    call    ASM_PFX(CommonExceptionHandler)
    282282    addq    $40, %rsp

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.asm

    r58464 r58466  
    4848    db      6ah        ; push
    4949@VectorNum:
    50     db      0          ; 0 will be fixed 
     50    db      0          ; 0 will be fixed
    5151    push    rax
    5252    mov     rax, HookAfterStubHeaderEnd
    … …  
    9090; +---------------------+ <-- RBP, 16-byte aligned
    9191; The follow algorithm is used for the common interrupt routine.
    92 CommonInterruptEntry PROC PUBLIC 
     92CommonInterruptEntry PROC PUBLIC
    9393    cli
    9494    pop     rax
    … …  
    112112    push    [rsp]
    113113    mov     qword ptr [rsp + 8], 0
    114 @@:       
     114@@:
    115115    push    rbp
    116116    mov     rbp, rsp
    … …  
    352352    push    rax
    353353    mov     rax, rsp          ; save old RSP to rax
    354     mov     rsp, [rsp + 20h]   
     354    mov     rsp, [rsp + 20h]
    355355    push    [rax + 10h]       ; save CS in new location
    356356    push    [rax + 8h]        ; save EIP in new location

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/MtrrLib/MtrrLib.c

    r58459 r58466  
    187187  //
    188188  MtrrContext->InterruptState = SaveAndDisableInterrupts();
    189  
     189
    190190  //
    191191  // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)
    … …  
    225225{
    226226  //
    227   // Flush all TLBs 
     227  // Flush all TLBs
    228228  //
    229229  CpuFlushTlb ();
    … …  
    238238  //
    239239  AsmWriteCr4 (MtrrContext->Cr4);
    240  
     240
    241241  //
    242242  // Restore original interrupt state
    … …  
    535535    if (Attributes == VariableMtrr[Index].Type) {
    536536      //
    537       // if the Mtrr range contain the request range, set a flag, then continue to 
     537      // if the Mtrr range contain the request range, set a flag, then continue to
    538538      // invalidate any MTRR of the same request range with higher priority cache type.
    539539      //
    … …  
    15681568    DEBUG((DEBUG_CACHE, "MTRR Settings\n"));
    15691569    DEBUG((DEBUG_CACHE, "=============\n"));
    1570    
     1570
    15711571    MtrrGetAllMtrrs (&MtrrSettings);
    15721572    DEBUG((DEBUG_CACHE, "MTRR Default Type: %016lx\n", MtrrSettings.MtrrDefType));
    … …  
    15951595        if (MemoryType > CacheWriteBack) {
    15961596          MemoryType = MTRR_CACHE_INVALID_TYPE;
    1597         }           
     1597        }
    15981598        if (MemoryType != PreviousMemoryType) {
    15991599          if (PreviousMemoryType != MTRR_CACHE_INVALID_TYPE) {
    … …  
    16311631        DEBUG((DEBUG_CACHE, "%a:%016lx-", mMtrrMemoryCacheTypeShortName[MemoryType], Base));
    16321632      }
    1633      
    1634       RangeBase    = BASE_1MB;       
     1633
     1634      RangeBase    = BASE_1MB;
    16351635      NoRangeBase  = BASE_1MB;
    16361636      RangeLimit   = Limit;
    16371637      NoRangeLimit = Limit;
    1638      
     1638
    16391639      for (Index = 0, Found = FALSE; Index < VariableMtrrCount; Index++) {
    16401640        if ((MtrrSettings.Variables.Mtrr[Index].Mask & BIT11) == 0) {
    … …  
    16501650          Found = TRUE;
    16511651        }
    1652        
     1652
    16531653        if (Base >= MtrrBase && MtrrBase > RangeBase) {
    16541654          RangeBase = MtrrBase;
    … …  
    16631663          RangeLimit = MtrrLimit;
    16641664        }
    1665        
     1665
    16661666        if (Base > MtrrLimit && NoRangeBase < MtrrLimit) {
    16671667          NoRangeBase = MtrrLimit + 1;
    … …  
    16711671        }
    16721672      }
    1673      
     1673
    16741674      if (Found) {
    16751675        Base = RangeLimit + 1;

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf

    r58459 r58466  
    77#  which accompanies this distribution.  The full text of the license may be found at
    88#  http://opensource.org/licenses/bsd-license.php
    9 # 
     9#
    1010#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1111#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    12 # 
     12#
    1313##
    1414
    … …  
    2020  MODULE_TYPE                    = BASE
    2121  VERSION_STRING                 = 1.0
    22   LIBRARY_CLASS                  = MtrrLib 
     22  LIBRARY_CLASS                  = MtrrLib
    2323
    2424

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf

    r58459 r58466  
    44# Timer Library that only uses CPU resources to provide calibrated delays
    55#  on IA-32, x64, and IPF.
    6 # Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib 
    7 #  in their initialization without any issues. They only have to be careful in 
    8 #  the implementation of runtime services and SMI handlers. 
     6# Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib
     7#  in their initialization without any issues. They only have to be careful in
     8#  the implementation of runtime services and SMI handlers.
    99#  Because CPU Local APIC and ITC could be programmed by OS, it cannot be
    1010#  used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c

    r58459 r58466  
    33
    44  This library uses the local APIC library so that it supports x2APIC mode.
    5  
     5
    66  Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
    77  This program and the accompanying materials

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.inf

    r58464 r58466  
    11## @file
    22#  Reset Vector
    3 # 
     3#
    44#  This VTF requires build time fixups in order to find the SEC entry point.
    55#

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/FixupVtf/Vtf.nasmb

    • Property svn:eol-style set to native

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb

    • Property svn:eol-style set to native

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkg.dec

    • Property svn:eol-style set to native
    r58459 r58466  
    3838  ##
    3939  LocalApicLib|Include/Library/LocalApicLib.h
    40  
     40
    4141[Guids]
    4242  gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/UefiCpuPkg.dsc

    r58459 r58466  
    88#  which accompanies this distribution. The full text of the license may be found at
    99#  http://opensource.org/licenses/bsd-license.php
    10 # 
     10#
    1111#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
    1212#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
    … …  
    5252  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
    5353  ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
    54   CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf 
     54  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
    5555
    5656[LibraryClasses.common.PEIM]
    … …  
    6464[LibraryClasses.IPF.PEIM]
    6565  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
    66  
     66
    6767[LibraryClasses.common.DXE_DRIVER]
    6868  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
    … …  
    7171  SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
    7272  MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
    73  
     73
    7474#
    7575# Drivers/Libraries within this package
    … …  
    9090  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
    9191  UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
    92   UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf 
     92  UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
    9393  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
    9494

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.S

    r58464 r58466  
    2121
    2222#------------------------------------------------------------------------------
    23 # 
     23#
    2424# VOID
    2525# EFIAPI
    … …  
    3535    movw    %ax, %es
    3636    movw    %ax, %fs
    37     movw    %ax, %gs 
     37    movw    %ax, %gs
    3838    ret

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.asm

    r58464 r58466  
    3939  mov     fs, ax
    4040  mov     gs, ax
    41   mov     ss, ax   
     41  mov     ss, ax
    4242  ret
    4343AsmSetDataSelectors   ENDP

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c

    r58459 r58466  
    113113    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
    114114    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
    115     UINT64  MustBe1:1;                // Must be 1 
     115    UINT64  MustBe1:1;                // Must be 1
    116116    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
    117117    UINT64  Available:3;              // Available for use by system software
    … …  
    137137    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
    138138    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
    139     UINT64  MustBe1:1;                // Must be 1 
     139    UINT64  MustBe1:1;                // Must be 1
    140140    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
    141141    UINT64  Available:3;              // Available for use by system software
    … …  
    156156/**
    157157  a ASM function to transfer control to OS.
    158  
     158
    159159  @param  S3WakingVector  The S3 waking up vector saved in ACPI Facs table
    160   @param  AcpiLowMemoryBase a buffer under 1M which could be used during the transfer             
     160  @param  AcpiLowMemoryBase a buffer under 1M which could be used during the transfer
    161161**/
    162162typedef
    … …  
    464464
    465465  //
    466   // NOTE: Because Debug Timer interrupt and system interrupts will be disabled 
     466  // NOTE: Because Debug Timer interrupt and system interrupts will be disabled
    467467  // in BootScriptExecuteDxe, the rest code in S3ResumeBootOs() cannot be halted
    468468  // by soft debugger.
    … …  
    581581/**
    582582  Restore S3 page table because we do not trust ACPINvs content.
    583   If BootScriptExector driver will not run in 64-bit mode, this function will do nothing. 
     583  If BootScriptExector driver will not run in 64-bit mode, this function will do nothing.
    584584
    585585  @param S3NvsPageTableAddress   PageTableAddress in ACPINvs
    … …  
    623623    PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;
    624624    S3NvsPageTableAddress += SIZE_4KB;
    625    
     625
    626626    Page1GSupport = FALSE;
    627627    if (PcdGetBool(PcdUse1GPageTable)) {
    … …  
    634634      }
    635635    }
    636    
     636
    637637    //
    638638    // Get physical address bits supported.
    … …  
    650650      }
    651651    }
    652    
     652
    653653    //
    654654    // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
    … …  
    677677      NumberOfPdpEntriesNeeded = 512;
    678678    }
    679    
     679
    680680    PageMapLevel4Entry = PageMap;
    681681    PageAddress        = 0;
    … …  
    687687      PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;
    688688      S3NvsPageTableAddress += SIZE_4KB;
    689    
     689
    690690      //
    691691      // Make a PML4 Entry
    … …  
    697697      if (Page1GSupport) {
    698698        PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
    699    
     699
    700700        for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
    701701          //
    … …  
    712712          // Each Directory Pointer entries points to a page of Page Directory entires.
    713713          // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
    714           //       
     714          //
    715715          PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;
    716716          S3NvsPageTableAddress += SIZE_4KB;
    717    
     717
    718718          //
    719719          // Fill in a Page Directory Pointer Entries
    … …  
    722722          PageDirectoryPointerEntry->Bits.ReadWrite = 1;
    723723          PageDirectoryPointerEntry->Bits.Present = 1;
    724    
     724
    725725          for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
    726726            //
    … …  
    782782    //
    783783    // Send SMI to APs
    784     //   
     784    //
    785785    SendSmiIpiAllExcludingSelf ();
    786786    //
    … …  
    797797    if (!EFI_ERROR (Status)) {
    798798      DEBUG ((EFI_D_ERROR, "Close all SMRAM regions before executing boot script\n"));
    799  
     799
    800800      for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {
    801801        Status = SmmAccess->Close ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);
    … …  
    803803
    804804      DEBUG ((EFI_D_ERROR, "Lock all SMRAM regions before executing boot script\n"));
    805  
     805
    806806      for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {
    807807        Status = SmmAccess->Lock ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);
    … …  
    817817    //
    818818    // On some platform, such as ECP, a dispatch node in boot script table may execute a 32-bit PEIM which may need PeiServices
    819     // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)). 
     819    // pointer. So PeiServices need preserve in (IDTBase- sizeof (UINTN)).
    820820    //
    821821    IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);
    822822    //
    823823    // Make sure the newly allcated IDT align with 16-bytes
    824     // 
     824    //
    825825    IdtBuffer = AllocatePages (EFI_SIZE_TO_PAGES((IdtDescriptor->Limit + 1) + 16));
    826826    ASSERT (IdtBuffer != NULL);
    … …  
    828828    // Additional 16 bytes allocated to save IA32 IDT descriptor and Pei Service Table Pointer
    829829    // IA32 IDT descriptor will be used to setup IA32 IDT table for 32-bit Framework Boot Script code
    830     // 
     830    //
    831831    ZeroMem (IdtBuffer, 16);
    832832    AsmReadIdtr ((IA32_DESCRIPTOR *)IdtBuffer);
    … …  
    863863  //
    864864  AsmReadIdtr (&PeiS3ResumeState->Idtr);
    865  
     865
    866866  //
    867867  // Report Status Code to indicate S3 boot script execution
    … …  
    10001000  DEBUG (( EFI_D_ERROR, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));
    10011001  DEBUG (( EFI_D_ERROR, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable));
    1002   DEBUG (( EFI_D_ERROR, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); 
     1002  DEBUG (( EFI_D_ERROR, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile));
    10031003  DEBUG (( EFI_D_ERROR, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress));
    10041004  DEBUG (( EFI_D_ERROR, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress));
    … …  
    10891089      //
    10901090      // update segment selectors per the new GDT.
    1091       //     
     1091      //
    10921092      AsmSetDataSelectors (DATA_SEGEMENT_SELECTOR);
    10931093      //
    … …  
    11231123
    11241124  This routine is to install EFI_PEI_S3_RESUME2_PPI.
    1125  
     1125
    11261126  @param  FileHandle              Handle of the file being invoked.
    11271127  @param  PeiServices             Pointer to PEI Services table.

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.S

    r58464 r58466  
    2121
    2222#------------------------------------------------------------------------------
    23 # 
     23#
    2424# VOID
    2525# EFIAPI
    … …  
    3434    movw    %cx, %es
    3535    movw    %cx, %fs
    36     movw    %cx, %gs 
     36    movw    %cx, %gs
    3737    ret

  • trunk/src/VBox/Devices/EFI/Firmware/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.asm

    r58464 r58466  
    3535  mov     fs, cx
    3636  mov     gs, cx
    37   mov     ss, cx   
     37  mov     ss, cx
    3838  ret
    3939AsmSetDataSelectors   ENDP
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