Changeset 58728 in vbox
- Timestamp:
- Nov 18, 2015 12:55:03 AM (9 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/include/iprt/formats/pecoff.h
r58654 r58728 62 62 * Used by IMAGE_FILE_HEADER::Machine and IMAGE_SEPARATE_DEBUG_HEADER::Machine. 63 63 * @{ */ 64 /** X86 compatible CPU, 32-bit instructions. */ 64 65 #define IMAGE_FILE_MACHINE_I386 UINT16_C(0x014c) 66 /** AMD64 compatible CPU, 64-bit instructions. */ 65 67 #define IMAGE_FILE_MACHINE_AMD64 UINT16_C(0x8664) 68 69 /** Unknown target CPU. */ 70 #define IMAGE_FILE_MACHINE_UNKNOWN UINT16_C(0x0000) 71 /** Matshushita AM33 CPU. */ 72 #define IMAGE_FILE_MACHINE_AM33 UINT16_C(0x01d3) 73 /** Little endian ARM CPU. */ 74 #define IMAGE_FILE_MACHINE_ARM UINT16_C(0x01c0) 75 /** ARM or Thumb stuff. */ 76 #define IMAGE_FILE_MACHINE_THUMB UINT16_C(0x01c2) 77 /** ARMv7 or higher CPU, Thumb mode. */ 78 #define IMAGE_FILE_MACHINE_ARMNT UINT16_C(0x01c4) 79 /** ARMv8 CPU, 64-bit mode. */ 80 #define IMAGE_FILE_MACHINE_ARM64 UINT16_C(0xaa64) 81 /** EFI byte code. */ 82 #define IMAGE_FILE_MACHINE_EBC UINT16_C(0x0ebc) 83 /** "Itanic" CPU. */ 84 #define IMAGE_FILE_MACHINE_IA64 UINT16_C(0x0200) 85 /** Mitsubishi M32R CPU, little endian. */ 86 #define IMAGE_FILE_MACHINE_M32R UINT16_C(0x9041) 87 /** MIPS CPU, compact 16-bit instructions only? */ 88 #define IMAGE_FILE_MACHINE_MIPS16 UINT16_C(0x0266) 89 /** MIPS CPU with FPU, full 32-bit instructions only? */ 90 #define IMAGE_FILE_MACHINE_MIPSFPU UINT16_C(0x0366) 91 /** MIPS CPU with FPU, compact 16-bit instructions? */ 92 #define IMAGE_FILE_MACHINE_MIPSFPU16 UINT16_C(0x0466) 93 /** MIPS CPU, little endian, Windows CE (?) v2 designation. */ 94 #define IMAGE_FILE_MACHINE_WCEMIPSV2 UINT16_C(0x0169) 95 /** Power PC CPU, little endian. */ 96 #define IMAGE_FILE_MACHINE_POWERPC UINT16_C(0x01f0) 97 /** Power PC CPU with FPU, also little endian? */ 98 #define IMAGE_FILE_MACHINE_POWERPCFP UINT16_C(0x01f1) 99 /** MIPS R4000 CPU, little endian. */ 100 #define IMAGE_FILE_MACHINE_R4000 UINT16_C(0x0166) 101 /** Hitachi SH3 CPU. */ 102 #define IMAGE_FILE_MACHINE_SH3 UINT16_C(0x01a2) 103 /** Hitachi SH3 DSP. */ 104 #define IMAGE_FILE_MACHINE_SH3DSP UINT16_C(0x01a3) 105 /** Hitachi SH4 CPU. */ 106 #define IMAGE_FILE_MACHINE_SH4 UINT16_C(0x01a6) 107 /** Hitachi SH5 CPU. */ 108 #define IMAGE_FILE_MACHINE_SH5 UINT16_C(0x01a8) 66 109 /** @} */ 67 110
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