VirtualBox

Changeset 60307 in vbox for trunk/src/VBox/Devices


Ignore:
Timestamp:
Apr 4, 2016 3:23:11 PM (9 years ago)
Author:
vboxsync
Message:

VMM: APIC rewrite. Initial commit, work in progress.

Location:
trunk/src/VBox/Devices
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Makefile.kmk

    r59775 r60307  
    10181018  VBoxDD2_DEFS          += VBOX_WITH_PXE_ROM
    10191019 endif
     1020 ifdef VBOX_WITH_NEW_APIC
     1021  VBoxDD2_DEFS          += VBOX_WITH_NEW_APIC
     1022 endif
    10201023
    10211024 $(call VBOX_SET_VER_INFO_DLL,VBoxDD2,VirtualBox VMM Devices and Drivers 2) # (last!)

  • trunk/src/VBox/Devices/PC/DevAPIC.cpp

    r57358 r60307  
    5252#include <VBox/vmm/stam.h>
    5353#include <VBox/vmm/vmcpuset.h>
     54#include <VBox/vmm/vm.h>
    5455#include <iprt/asm.h>
    5556#include <iprt/assert.h>
    … …  
    378379    RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
    379380
    380     /** APIC specification version in this virtual hardware configuration. */
    381     PDMAPICVERSION          enmVersion;
     381    /** APIC specification mode in this virtual hardware configuration. */
     382    PDMAPICMODE             enmMode;
    382383
    383384    /** Number of attempts made to optimize TPR accesses. */
    … …  
    471472    Log2(("apic: send SIPI vector=%d\n", vector));
    472473
    473     pDev->pApicHlpR3->pfnSendSipi(pDev->pDevInsR3,
    474                                   getCpuFromLapic(pDev, pApic),
    475                                   vector);
     474    pDev->pApicHlpR3->pfnSendStartupIpi(pDev->pDevInsR3, getCpuFromLapic(pDev, pApic), vector);
    476475}
    477476
    … …  
    488487DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo *pDev)
    489488{
    490     switch (pDev->enmVersion)
    491     {
    492         case PDMAPICVERSION_NONE:
     489    switch (pDev->enmMode)
     490    {
     491        case PDMAPICMODE_NONE:
    493492            return 0;
    494         case PDMAPICVERSION_APIC:
     493        case PDMAPICMODE_APIC:
    495494            return MSR_IA32_APICBASE_ENABLE;
    496         case PDMAPICVERSION_X2APIC:
     495        case PDMAPICMODE_X2APIC:
    497496            return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE;
    498497        default:
    499             AssertMsgFailed(("Unsupported APIC version %d\n", pDev->enmVersion));
     498            AssertMsgFailed(("Unsupported APIC mode %d\n", pDev->enmMode));
    500499            return 0;
    501500    }
    502501}
    503502
    504 DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
     503DECLINLINE(PDMAPICMODE) getApicMode(APICState *apic)
    505504{
    506505    switch (((apic->apicbase) >> 10) & 0x3)
    507506    {
    508507        case 0:
    509             return PDMAPICVERSION_NONE;
     508            return PDMAPICMODE_NONE;
    510509        case 1:
    511510        default:
    512511            /* Invalid */
    513             return PDMAPICVERSION_NONE;
     512            return PDMAPICMODE_NONE;
    514513        case 2:
    515             return PDMAPICVERSION_APIC;
     514            return PDMAPICMODE_APIC;
    516515        case 3:
    517             return PDMAPICVERSION_X2APIC;
     516            return PDMAPICMODE_X2APIC;
    518517    }
    519518}
    … …  
    583582
    584583
    585 PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t val)
     584PDMBOTHCBDECL(VBOXSTRICTRC) apicSetBase(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t val)
    586585{
    587586    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    588587    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    589     APICState *pApic = apicGetStateById(pDev, idCpu);
     588    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    590589    Log(("apicSetBase: %016RX64\n", val));
    591590
    … …  
    594593    /** @todo If this change is valid immediately, then we should change the MMIO registration! */
    595594    /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
    596     PDMAPICVERSION oldMode = getApicMode(pApic);
     595    PDMAPICMODE oldMode = getApicMode(pApic);
    597596    pApic->apicbase = (val & 0xfffff000)                        /* base */
    598597                    | (val & getApicEnableBits(pDev))           /* mode */
    599598                    | (pApic->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
    600     PDMAPICVERSION newMode = getApicMode(pApic);
     599    PDMAPICMODE newMode = getApicMode(pApic);
    601600
    602601    if (oldMode != newMode)
    … …  
    604603        switch (newMode)
    605604        {
    606             case PDMAPICVERSION_NONE:
     605            case PDMAPICMODE_NONE:
    607606            {
    608607                pApic->spurious_vec &= ~APIC_SV_ENABLE;
    … …  
    614613                 * APIC (see Section 10.4.2, 'Presence of the Local APIC') is also set to 0."
    615614                 */
    616                 pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
     615                pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICMODE_NONE);
    617616                break;
    618617            }
    619             case PDMAPICVERSION_APIC:
     618            case PDMAPICMODE_APIC:
    620619                /** @todo map MMIO ranges, if needed */
    621620                break;
    622             case PDMAPICVERSION_X2APIC:
     621            case PDMAPICMODE_X2APIC:
    623622                /** @todo unmap MMIO ranges of this APIC, according to the spec.  This is how
    624623                 *       real hw works! (Remember the problem disabling NMI watchdog timers in
    … …  
    630629    }
    631630    /* APIC_UNLOCK(pDev); */
    632 }
    633 
    634 PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns, VMCPUID idCpu)
     631    return VINF_SUCCESS;
     632}
     633
     634PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns, PVMCPU pVCpu)
    635635{
    636636    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    637637    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    638     APICState *pApic = apicGetStateById(pDev, idCpu);
     638    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    639639    LogFlow(("apicGetBase: %016llx\n", (uint64_t)pApic->apicbase));
    640640    return pApic->apicbase;
    641641}
    642642
    643 PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
     643PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t val)
    644644{
    645645    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    646646    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    647     APICState *pApic = apicGetStateById(pDev, idCpu);
     647    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    648648    LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, pApic->tpr, val));
    649649    apic_update_tpr(pDev, pApic, val);
    650650}
    651651
    652 PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
     652PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, PVMCPU pVCpu)
    653653{
    654654    /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
    655655    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    656     APICState *pApic = apicGetStateById(pDev, idCpu);
     656    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    657657    Log2(("apicGetTPR: returns %#x\n", pApic->tpr));
    658658    return pApic->tpr;
    … …  
    10511051 * @interface_method_impl{PDMAPICREG,pfnWriteMSRR3}
    10521052 */
    1053 PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
     1053PDMBOTHCBDECL(VBOXSTRICTRC) apicWriteMSR(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
    10541054{
    10551055    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    1056     if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
     1056    if (pDev->enmMode < PDMAPICMODE_X2APIC)
    10571057        return VERR_EM_INTERPRETER; /** @todo tell the caller to raise hell (\#GP(0)).  */
    10581058
    1059     APICState      *pApic = apicGetStateById(pDev, idCpu);
     1059    APICState      *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    10601060    uint32_t        iReg = (u32Reg - MSR_IA32_X2APIC_START) & 0xff;
    10611061    return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
    … …  
    10661066 * @interface_method_impl{PDMAPICREG,pfnReadMSRR3}
    10671067 */
    1068 PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
     1068PDMBOTHCBDECL(VBOXSTRICTRC) apicReadMSR(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
    10691069{
    10701070    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    10711071
    1072     if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
     1072    if (pDev->enmMode < PDMAPICMODE_X2APIC)
    10731073        return VERR_EM_INTERPRETER;
    10741074
    1075     APICState      *pApic = apicGetStateById(pDev, idCpu);
     1075    APICState      *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    10761076    uint32_t        iReg = (u32Reg - MSR_IA32_X2APIC_START) & 0xff;
    10771077    return apicReadRegister(pDev, pApic, iReg, pu64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
    … …  
    10991099 * Normally used for 8259A PIC and NMI.
    11001100 */
    1101 PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
     1101PDMBOTHCBDECL(VBOXSTRICTRC) apicLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
    11021102{
    11031103    APICDeviceInfo  *pDev  = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    1104     APICState       *pApic = apicGetStateById(pDev, 0);
     1104    NOREF(rcRZ);
     1105
     1106    /* NB: We currently only deliver local interrupts to the first CPU. In theory they
     1107     * should be delivered to all CPUs and it is the guest's responsibility to ensure
     1108     * no more than one CPU has the interrupt unmasked.
     1109     */
     1110    APICState       *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    11051111
    11061112    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    … …  
    11241130    AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
    11251131
    1126     /* NB: We currently only deliver local interrupts to the first CPU. In theory they
    1127      * should be delivered to all CPUs and it is the guest's responsibility to ensure
    1128      * no more than one CPU has the interrupt unmasked.
    1129      */
    11301132    uint32_t u32Lvec;
    11311133
    … …  
    11331135    /* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
    11341136    if (!(u32Lvec & APIC_LVT_MASKED))
    1135     {   uint8_t     u8Delivery;
     1137    {
     1138        uint8_t     u8Delivery;
    11361139        PDMAPICIRQ  enmType;
    11371140
    … …  
    12291232
    12301233/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
    1231 PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t *pu8PendingIrq)
     1234PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8PendingIrq)
    12321235{
    12331236    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    … …  
    12371240    /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
    12381241
    1239     APICState *pApic = apicGetStateById(pDev, idCpu);
     1242    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    12401243
    12411244    /*
    … …  
    14441447
    14451448
    1446 PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)
     1449PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t *puTagSrc)
    14471450{
    14481451    APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
    … …  
    14561459    Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
    14571460
    1458     APICState *pApic = apicGetStateById(pDev, idCpu);
     1461    APICState *pApic = apicGetStateById(pDev, pVCpu->idCpu);
    14591462
    14601463    if (!(pApic->spurious_vec & APIC_SV_ENABLE))
    … …  
    20742077    SSMR3PutU32( pSSM, pDev->cCpus);
    20752078    SSMR3PutBool(pSSM, pDev->fIoApic);
    2076     SSMR3PutU32( pSSM, pDev->enmVersion);
    2077     AssertCompile(PDMAPICVERSION_APIC == 2);
     2079    SSMR3PutU32( pSSM, pDev->enmMode);
     2080    AssertCompile(PDMAPICMODE_APIC == 2);
    20782081
    20792082    return VINF_SSM_DONT_CALL_AGAIN;
    … …  
    21242127            return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pDev->fIoApic);
    21252128
    2126         uint32_t uApicVersion;
    2127         rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
    2128         if (uApicVersion != (uint32_t)pDev->enmVersion)
    2129             return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pDev->enmVersion);
     2129        uint32_t uApicMode;
     2130        rc = SSMR3GetU32(pSSM, &uApicMode); AssertRCReturn(rc, rc);
     2131        if (uApicMode != (uint32_t)pDev->enmMode)
     2132            return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%#x config=%#x"), uApicMode, pDev->enmMode);
    21302133    }
    21312134
    … …  
    21792182
    21802183    LogRel(("APIC: Re-activating Local APIC\n"));
    2181     pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmVersion);
     2184    pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmMode);
    21822185
    21832186    APIC_UNLOCK(pDev);
    … …  
    22752278    pDev->fIoApic    = fIoApic;
    22762279    /** @todo Finish X2APIC implementation.  Must, among other things, set
    2277      *        PDMAPICVERSION_X2APIC here when X2APIC is configured. */
    2278     pDev->enmVersion = PDMAPICVERSION_APIC;
     2280     *        PDMAPICMODE_X2APIC here when X2APIC is configured. */
     2281    pDev->enmMode    = PDMAPICMODE_APIC;
    22792282
    22802283    /* Disable locking in this device. */
    … …  
    23032306    ApicReg.pfnGetInterruptR3       = apicGetInterrupt;
    23042307    ApicReg.pfnHasPendingIrqR3      = apicHasPendingIrq;
    2305     ApicReg.pfnSetBaseR3            = apicSetBase;
    2306     ApicReg.pfnGetBaseR3            = apicGetBase;
    2307     ApicReg.pfnSetTPRR3             = apicSetTPR;
    2308     ApicReg.pfnGetTPRR3             = apicGetTPR;
    2309     ApicReg.pfnWriteMSRR3           = apicWriteMSR;
    2310     ApicReg.pfnReadMSRR3            = apicReadMSR;
     2308    ApicReg.pfnSetBaseMsrR3         = apicSetBase;
     2309    ApicReg.pfnGetBaseMsrR3         = apicGetBase;
     2310    ApicReg.pfnSetTprR3             = apicSetTPR;
     2311    ApicReg.pfnGetTprR3             = apicGetTPR;
     2312    ApicReg.pfnWriteMsrR3           = apicWriteMSR;
     2313    ApicReg.pfnReadMsrR3            = apicReadMSR;
    23112314    ApicReg.pfnBusDeliverR3         = apicBusDeliverCallback;
    23122315    ApicReg.pfnLocalInterruptR3     = apicLocalInterrupt;
    … …  
    23162319        ApicReg.pszGetInterruptRC   = "apicGetInterrupt";
    23172320        ApicReg.pszHasPendingIrqRC  = "apicHasPendingIrq";
    2318         ApicReg.pszSetBaseRC        = "apicSetBase";
    2319         ApicReg.pszGetBaseRC        = "apicGetBase";
    2320         ApicReg.pszSetTPRRC         = "apicSetTPR";
    2321         ApicReg.pszGetTPRRC         = "apicGetTPR";
    2322         ApicReg.pszWriteMSRRC       = "apicWriteMSR";
    2323         ApicReg.pszReadMSRRC        = "apicReadMSR";
     2321        ApicReg.pszSetBaseMsrRC     = "apicSetBase";
     2322        ApicReg.pszGetBaseMsrRC     = "apicGetBase";
     2323        ApicReg.pszSetTprRC         = "apicSetTPR";
     2324        ApicReg.pszGetTprRC         = "apicGetTPR";
     2325        ApicReg.pszWriteMsrRC       = "apicWriteMSR";
     2326        ApicReg.pszReadMsrRC        = "apicReadMSR";
    23242327        ApicReg.pszBusDeliverRC     = "apicBusDeliverCallback";
    23252328        ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
    … …  
    23282331        ApicReg.pszGetInterruptR0   = "apicGetInterrupt";
    23292332        ApicReg.pszHasPendingIrqR0  = "apicHasPendingIrq";
    2330         ApicReg.pszSetBaseR0        = "apicSetBase";
    2331         ApicReg.pszGetBaseR0        = "apicGetBase";
    2332         ApicReg.pszSetTPRR0         = "apicSetTPR";
    2333         ApicReg.pszGetTPRR0         = "apicGetTPR";
    2334         ApicReg.pszWriteMSRR0       = "apicWriteMSR";
    2335         ApicReg.pszReadMSRR0        = "apicReadMSR";
     2333        ApicReg.pszSetBaseMsrR0     = "apicSetBase";
     2334        ApicReg.pszGetBaseMsrR0     = "apicGetBase";
     2335        ApicReg.pszSetTprR0         = "apicSetTPR";
     2336        ApicReg.pszGetTprR0         = "apicGetTPR";
     2337        ApicReg.pszWriteMsrR0       = "apicWriteMSR";
     2338        ApicReg.pszReadMsrR0        = "apicReadMSR";
    23362339        ApicReg.pszBusDeliverR0     = "apicBusDeliverCallback";
    23372340        ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
    … …  
    23422345        ApicReg.pszGetInterruptRC   = NULL;
    23432346        ApicReg.pszHasPendingIrqRC  = NULL;
    2344         ApicReg.pszSetBaseRC        = NULL;
    2345         ApicReg.pszGetBaseRC        = NULL;
    2346         ApicReg.pszSetTPRRC         = NULL;
    2347         ApicReg.pszGetTPRRC         = NULL;
    2348         ApicReg.pszWriteMSRRC       = NULL;
    2349         ApicReg.pszReadMSRRC        = NULL;
     2347        ApicReg.pszSetBaseMsrRC     = NULL;
     2348        ApicReg.pszGetBaseMsrRC     = NULL;
     2349        ApicReg.pszSetTprRC         = NULL;
     2350        ApicReg.pszGetTprRC         = NULL;
     2351        ApicReg.pszWriteMsrRC       = NULL;
     2352        ApicReg.pszReadMsrRC        = NULL;
    23502353        ApicReg.pszBusDeliverRC     = NULL;
    23512354        ApicReg.pszLocalInterruptRC = NULL;
    … …  
    23542357        ApicReg.pszGetInterruptR0   = NULL;
    23552358        ApicReg.pszHasPendingIrqR0  = NULL;
    2356         ApicReg.pszSetBaseR0        = NULL;
    2357         ApicReg.pszGetBaseR0        = NULL;
    2358         ApicReg.pszSetTPRR0         = NULL;
    2359         ApicReg.pszGetTPRR0         = NULL;
    2360         ApicReg.pszWriteMSRR0       = NULL;
    2361         ApicReg.pszReadMSRR0        = NULL;
     2359        ApicReg.pszSetBaseMsrR0     = NULL;
     2360        ApicReg.pszGetBaseMsrR0     = NULL;
     2361        ApicReg.pszSetTprR0         = NULL;
     2362        ApicReg.pszGetTprR0         = NULL;
     2363        ApicReg.pszWriteMsrR0       = NULL;
     2364        ApicReg.pszReadMsrR0        = NULL;
    23622365        ApicReg.pszBusDeliverR0     = NULL;
    23632366        ApicReg.pszLocalInterruptR0 = NULL;
    … …  
    23732376     */
    23742377    LogRel(("APIC: Activating Local APIC\n"));
    2375     pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmVersion);
     2378    pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmMode);
    23762379
    23772380    /*

  • trunk/src/VBox/Devices/build/VBoxDD2.cpp

    r57358 r60307  
    5959    int rc;
    6060
     61#ifndef VBOX_WITH_NEW_APIC
    6162    rc = pCallbacks->pfnRegister(pCallbacks, &g_DeviceAPIC);
    6263    if (RT_FAILURE(rc))
    6364        return rc;
     65#endif
    6466    rc = pCallbacks->pfnRegister(pCallbacks, &g_DeviceIOAPIC);
    6567    if (RT_FAILURE(rc))

  • trunk/src/VBox/Devices/build/VBoxDD2.h

    r56292 r60307  
    4444# endif
    4545#endif /* !IN_VBOXDD2 */
     46
     47#ifndef VBOX_WITH_NEW_APIC
    4648extern const PDMDEVREG g_DeviceAPIC;
     49#endif
    4750extern const PDMDEVREG g_DeviceIOAPIC;
    4851extern const PDMDEVREG g_DeviceLPC;

  • trunk/src/VBox/Devices/testcase/Makefile.kmk

    r59804 r60307  
    2323#
    2424VBOX_PATH_DEVICES_SRC ?= $(PATH_ROOT)/src/VBox/Devices
     25VBOX_PATH_VMM_DEVICES_SRC ?= $(PATH_ROOT)/src/VBox/VMM/include
    2526VBOX_DEVICES_TEST_OUT_DIR := $(PATH_TARGET)/Devices/testcase
    2627BLDDIRS += $(VBOX_DEVICES_TEST_OUT_DIR)
    … …  
    3435        $(if $(VBOX_WITH_HGSMI),VBOX_WITH_HGSMI,) \
    3536        $(if $(VBOX_WITH_LSILOGIC),VBOX_WITH_LSILOGIC,) \
     37        $(if $(VBOX_WITH_NEW_APIC),VBOX_WITH_NEW_APIC,) \
    3638        $(if $(VBOX_WITH_NEW_PS2M),VBOX_WITH_NEW_PS2M,) \
    3739        $(if $(VBOX_WITH_NVME_IMPL),VBOX_WITH_NVME_IMPL,) \
    … …  
    7476        $(VBOX_PATH_DEVICES_SRC)/Bus \
    7577        $(VBOX_DEVICES_TEST_OUT_DIR)
     78 ifdef VBOX_WITH_NEW_APIC
     79 tstDeviceStructSizeRC_INCS     += $(VBOX_PATH_VMM_DEVICES_SRC)
     80 endif
    7681endif # VBOX_WITH_RAW_MODE
    7782
    … …  
    9297ifdef VBOX_WITH_RAW_MODE
    9398 tstDeviceStructSize.cpp_DEPS = $(VBOX_DEVICES_TEST_OUT_DIR)/tstDeviceStructSizeRC.h
     99endif
     100ifdef VBOX_WITH_NEW_APIC
     101 tstDeviceStructSize_INCS     += $(VBOX_PATH_VMM_DEVICES_SRC)
    94102endif
    95103

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSize.cpp

    r58112 r60307  
    5858#undef LOG_GROUP
    5959#include "../PC/DevRTC.cpp"
    60 #undef LOG_GROUP
    61 #include "../PC/DevAPIC.cpp"
     60# undef LOG_GROUP
     61#ifdef VBOX_WITH_NEW_APIC
     62# include "../../VMM/VMMR3/APIC.cpp"
     63#else
     64# include "../PC/DevAPIC.cpp"
     65#endif
    6266#undef LOG_GROUP
    6367#include "../PC/DevIoApic.cpp"
    … …  
    281285    CHECK_MEMBER_ALIGNMENT(AHCI, lock, 8);
    282286    CHECK_MEMBER_ALIGNMENT(AHCIPort, StatDMA, 8);
    283 #ifdef VBOX_WITH_STATISTICS
     287#ifdef VBOX_WITH_NEW_APIC
     288    CHECK_MEMBER_ALIGNMENT(APICDEV, pDevInsR0, 8);
     289    CHECK_MEMBER_ALIGNMENT(APICDEV, pDevInsRC, 8);
     290#else
     291# ifdef VBOX_WITH_STATISTICS
    284292    CHECK_MEMBER_ALIGNMENT(APICDeviceInfo, StatMMIOReadGC, 8);
     293# endif
    285294#endif
    286295    CHECK_MEMBER_ALIGNMENT(ATADevState, cTotalSectors, 8);

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r60026 r60307  
    6060#undef LOG_GROUP
    6161#include "../PC/DevRTC.cpp"
    62 #undef LOG_GROUP
    63 #include "../PC/DevAPIC.cpp"
     62# undef LOG_GROUP
     63#ifdef VBOX_WITH_NEW_APIC
     64# include "../../VMM/VMMR3/APIC.cpp"
     65#else
     66# include "../PC/DevAPIC.cpp"
     67#endif
    6468#undef LOG_GROUP
    6569#include "../PC/DevIoApic.cpp"
    … …  
    740744    GEN_CHECK_OFF(RTCSTATE, CurHintPeriod);
    741745
     746#ifdef VBOX_WITH_NEW_APIC
     747    GEN_CHECK_SIZE(APIC);
     748    GEN_CHECK_OFF(APIC, pApicDevR0);
     749    GEN_CHECK_OFF(APIC, pApicDevR3);
     750    GEN_CHECK_OFF(APIC, pApicDevRC);
     751    GEN_CHECK_OFF(APIC, HCPhysApicPib);
     752    GEN_CHECK_OFF(APIC, pvApicPibR0);
     753    GEN_CHECK_OFF(APIC, pvApicPibR3);
     754    GEN_CHECK_OFF(APIC, pvApicPibRC);
     755    GEN_CHECK_OFF(APIC, cbApicPib);
     756    GEN_CHECK_OFF(APIC, fVirtApicRegsEnabled);
     757    GEN_CHECK_OFF(APIC, fPostedIntrsEnabled);
     758    GEN_CHECK_OFF(APIC, fSupportsTscDeadline);
     759    GEN_CHECK_OFF(APIC, fIoApicPresent);
     760    GEN_CHECK_OFF(APIC, fRZEnabled);
     761    GEN_CHECK_OFF(APIC, enmOriginalMode);
     762
     763    GEN_CHECK_SIZE(APICCPU);
     764    GEN_CHECK_OFF(APICCPU, pvApicPageR0);
     765    GEN_CHECK_OFF(APICCPU, pvApicPageR3);
     766    GEN_CHECK_OFF(APICCPU, pvApicPageRC);
     767    GEN_CHECK_OFF(APICCPU, cbApicPage);
     768    GEN_CHECK_OFF(APICCPU, uEsrInternal);
     769    GEN_CHECK_OFF(APICCPU, uApicBaseMsr);
     770    GEN_CHECK_OFF(APICCPU, HCPhysApicPib);
     771    GEN_CHECK_OFF(APICCPU, pvApicPibR0);
     772    GEN_CHECK_OFF(APICCPU, pvApicPibR3);
     773    GEN_CHECK_OFF(APICCPU, pvApicPibRC);
     774    GEN_CHECK_OFF(APICCPU, ApicPibLevel);
     775    GEN_CHECK_OFF(APICCPU, pTimerR0);
     776    GEN_CHECK_OFF(APICCPU, pTimerR3);
     777    GEN_CHECK_OFF(APICCPU, pTimerRC);
     778    GEN_CHECK_OFF(APICCPU, TimerCritSect);
     779    GEN_CHECK_OFF(APICCPU, u64TimerInitial);
     780    GEN_CHECK_OFF(APICCPU, uHintedTimerInitialCount);
     781    GEN_CHECK_OFF(APICCPU, uHintedTimerShift);
     782    GEN_CHECK_OFF(APICCPU, StatMmioReadGC);
     783#else
    742784    /* PC/DevAPIC.cpp */
    743785    GEN_CHECK_SIZE(APICState);
    … …  
    773815    GEN_CHECK_OFF(APICState, uHintedCountShift);
    774816    GEN_CHECK_OFF(APICState, pszDesc);
    775 #ifdef VBOX_WITH_STATISTICS
     817# ifdef VBOX_WITH_STATISTICS
    776818    GEN_CHECK_OFF(APICState, StatTimerSetInitialCount);
    777819    GEN_CHECK_OFF(APICState, StatTimerSetLvtNoRelevantChange);
    778 #endif
     820# endif
    779821
    780822    GEN_CHECK_SIZE(APICDeviceInfo);
    … …  
    791833    GEN_CHECK_OFF(APICDeviceInfo, paLapicsRC);
    792834    GEN_CHECK_OFF(APICDeviceInfo, pCritSectRC);
    793     GEN_CHECK_OFF(APICDeviceInfo, enmVersion);
     835    GEN_CHECK_OFF(APICDeviceInfo, enmMode);
    794836    GEN_CHECK_OFF(APICDeviceInfo, cTPRPatchAttempts);
    795837    GEN_CHECK_OFF(APICDeviceInfo, cCpus);
    796 #ifdef VBOX_WITH_STATISTICS
     838# ifdef VBOX_WITH_STATISTICS
    797839    GEN_CHECK_OFF(APICDeviceInfo, StatMMIOReadGC);
    798840    GEN_CHECK_OFF(APICDeviceInfo, StatMMIOWriteHC);
    799 #endif
     841# endif
     842#endif  /* VBOX_WITH_NEW_APIC */
    800843
    801844    /* PC/DevIoApic.cpp */
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