Changeset 60321 in vbox for trunk

Timestamp:

Apr 5, 2016 12:33:14 AM (9 years ago)

Author:

vboxsync

Message:

bs3kit: 386 fixes.

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-basic-2-template.c (modified) (4 diffs)
• bs3kit/bs3-cmn-PagingInitRootForPP.c (modified) (3 diffs)
• bs3kit/bs3-cmn-PagingProtect.c (modified) (2 diffs)
• bs3kit/bs3-mode-SwitchToPP16.asm (modified) (1 diff)
• bs3kit/bs3-rm-InitMemory.c (modified) (4 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c

@@ -970 +970 @@
                 ASMSetIDTR(&Idtr);
                 Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
-                bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /*uErrCd*/, uCr2Expected);
+                if (f486Plus)
+                    bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /*uErrCd*/, uCr2Expected);
+                else
+                    bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /*uErrCd*/, uCr2Expected + 4 - RT_MIN(j, 4));
                 g_usBs3TestStep++;
 
@@ -982 +985 @@
                     ASMSetIDTR(&Idtr);
                     Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
-                    bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /*uErrCd*/, uCr2Expected);
+                    if (f486Plus)
+                        bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /*uErrCd*/, uCr2Expected);
+                    else
+                        bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, X86_TRAP_PF_RW /*uErrCd*/, uCr2Expected + 4 - RT_MIN(j, 4));
                     g_usBs3TestStep++;
 
@@ -1119 +1125 @@
         {
             Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
-            bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, 0 /*uErrCd*/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00);
+            if (f486Plus)
+                bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, 0 /*uErrCd*/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00);
+            else
+                bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00 + 4);
             g_usBs3TestStep++;
 
@@ -1127 +1136 @@
             Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
 
-            bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, 0 /*uErrCd*/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03);
+            if (f486Plus)
+                bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, 0 /*uErrCd*/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03);
+            else
+                bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, X86_TRAP_PF_RW, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03 + 4);
             g_usBs3TestStep++;
 

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-PagingInitRootForPP.c

@@ -45 +45 @@
 {
     uint32_t uCurPhys = (uint32_t)iFirst << X86_PD_SHIFT;
+
     while (cEntries--)
     {
@@ -125 +126 @@
                     cTop = RT_MIN(16, cMax / 4);
                 }
-                Bs3Printf("Bs3PagingInitRootForPP: Warning! insufficient memory for mapping all 4GB!\n"
-                          "    Will only map 0x00000000-%#010RX32 and %#010RX32-0xffffffff.\n",
-                          (uint32_t)(cMax - cTop) << PAGE_SHIFT, UINT32_MAX - ((uint32_t)cTop << PAGE_SHIFT) + 1);
+                Bs3TestPrintf("Bs3PagingInitRootForPP: Warning! insufficient memory for mapping all 4GB!\n"
+                              "    Will only map 0x00000000-%#010RX32 and %#010RX32-0xffffffff.\n",
+                              (uint32_t)(cMax - cTop) << PAGE_SHIFT, UINT32_MAX - ((uint32_t)cTop << PAGE_SHIFT) + 1);
                 rc = Bs3PagingInitPageTablesForPgDir(pPgDir, 0, cMax - cTop);
                 if (RT_SUCCESS(rc))
@@ -139 +140 @@
     }
 
+    Bs3Printf("Bs3PagingInitRootForPP: No memory!\n");
     BS3_ASSERT(false);
     return VERR_NO_MEMORY;

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-cmn-PagingProtect.c

@@ -215 +215 @@
 {
     RTCCUINTXREG const  cr3        = ASMGetCR3();
-    RTCCUINTXREG const  cr4        = ASMGetCR4();
+    RTCCUINTXREG const  cr4        = g_uBs3CpuDetected & BS3CPU_F_CPUID ? ASMGetCR4() : 0;
     bool const          fLegacyPTs = !(cr4 & X86_CR4_PAE);
     bool const          fUseInvlPg = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486
@@ -222 +222 @@
     unsigned            cEntries;
     int                 rc;
-
-    BS3PAGING_DPRINTF(("Bs3PagingProtect: reloading cr3=%RX32\n", (uint32_t)cr3));
-    ASMSetCR3(cr3);
 
     /*

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-mode-SwitchToPP16.asm

@@ -68 +68 @@
 
 %else
+
         ;
         ; Switch to 16-bit text segment and prepare for returning in 16-bit mode.

trunk/src/VBox/ValidationKit/bootsectors/bs3kit/bs3-rm-InitMemory.c

@@ -95 +95 @@
     modify exact [ax bx cx dx di es];
 
+/**
+ * Performs a int 15h function 0x88 call.
+ *
+ * @returns UINT32_MAX on failure, number of KBs above 1MB otherwise.
+ */
+BS3_DECL(uint32_t) Bs3BiosInt15h88(void);
+#pragma aux Bs3BiosInt15h88 = \
+    ".286" \
+    "clc" \
+    "mov    ax, 08800h" \
+    "int    15h" \
+    "jc     failed" \
+    "xor    dx, dx" \
+    "jmp    done" \
+    "failed:" \
+    "xor    ax, ax" \
+    "dec    ax" \
+    "mov    dx, ax" \
+    "done:" \
+    value [ax dx] \
+    modify exact [ax bx cx dx es];
+
 
 /*********************************************************************************************************************************
@@ -152 +174 @@
 
 
+/**
+ * Adds a range of memory to the tiled slabs.
+ *
+ * @param   uRange      Start of range.
+ * @param   cbRange     Size of range.
+ */
+static void bs3InitMemoryAddRange(uint32_t uRange, uint32_t cbRange)
+{
+    if (uRange < BS3_SEL_TILED_AREA_SIZE)
+    {
+        uint32_t uRangeEnd = uRange + cbRange;
+        if (   uRange >= _1M
+            || uRangeEnd > _1M)
+        {
+            uint16_t cPages;
+
+            /* Adjust the start of the range such that it's at or above 1MB and page aligned.  */
+            if (uRange < _1M)
+            {
+                cbRange -= _1M - uRange;
+                uRange   = _1M;
+            }
+            else if (uRange & (_4K - 1U))
+            {
+                cbRange -= uRange & (_4K - 1U);
+                uRange   = RT_ALIGN_32(uRange, _4K);
+            }
+
+            /* Adjust the end/size of the range such that it's page aligned and not beyond the tiled area. */
+            if (uRangeEnd > BS3_SEL_TILED_AREA_SIZE)
+            {
+                cbRange  -= uRangeEnd - BS3_SEL_TILED_AREA_SIZE;
+                uRangeEnd = BS3_SEL_TILED_AREA_SIZE;
+            }
+            else if (uRangeEnd & (_4K - 1U))
+            {
+                cbRange   -= uRangeEnd & (_4K - 1U);
+                uRangeEnd &= ~(uint32_t)(_4K - 1U);
+            }
+
+            /* If there is still something, enable it.
+               (We're a bit paranoid here don't trust the BIOS to only report a page once.)  */
+            cPages = cbRange >> 12; /*div 4K*/
+            if (cPages)
+            {
+                unsigned i;
+                uRange -= _1M;
+                i = uRange >> 12; /*div _4K*/
+                while (cPages-- > 0)
+                {
+                    uint16_t uLineToLong = ASMBitTestAndClear(g_Bs3Mem4KUpperTiled.Core.bmAllocated, i);
+                    g_Bs3Mem4KUpperTiled.Core.cFreeChunks += uLineToLong;
+                    i++;
+                }
+            }
+        }
+    }
+}
+
 
 BS3_DECL(void) Bs3InitMemory_rm(void)
@@ -157 +238 @@
     uint16_t        i;
     uint16_t        cPages;
+    uint32_t        u32;
     INT15E820ENTRY  Entry;
 
@@ -226 +308 @@
                && i++ < 2048)
         {
-            if (Entry.uType == INT15E820_TYPE_USABLE)
-            {
-                if (Entry.uBaseAddr < BS3_SEL_TILED_AREA_SIZE)
-                {
-                    /* Entry concerning tiled memory. Convert from 64-bit to 32-bit
-                       values and check whether it's concerning anything at or above 1MB  */
-                    uint32_t uRange    = (uint32_t)Entry.uBaseAddr;
-                    uint32_t cbRange   = Entry.cbRange >= BS3_SEL_TILED_AREA_SIZE
-                                       ? BS3_SEL_TILED_AREA_SIZE : (uint32_t)Entry.cbRange;
-                    uint32_t uRangeEnd = uRange + cbRange;
-                    AssertCompile(BS3_SEL_TILED_AREA_SIZE <= _512M /* the range of 16-bit cPages. */ );
-                    if (   uRange >= _1M
-                        || uRangeEnd > _1M)
-                    {
-                        /* Adjust the start of the range such that it's at or above 1MB and page aligned.  */
-                        if (uRange < _1M)
-                        {
-                            cbRange -= _1M - uRange;
-                            uRange   = _1M;
-                        }
-                        else if (uRange & (_4K - 1U))
-                        {
-                            cbRange -= uRange & (_4K - 1U);
-                            uRange   = RT_ALIGN_32(uRange, _4K);
-                        }
-
-                        /* Adjust the end/size of the range such that it's page aligned and not beyond the tiled area. */
-                        if (uRangeEnd > BS3_SEL_TILED_AREA_SIZE)
-                        {
-                            cbRange  -= uRangeEnd - BS3_SEL_TILED_AREA_SIZE;
-                            uRangeEnd = BS3_SEL_TILED_AREA_SIZE;
-                        }
-                        else if (uRangeEnd & (_4K - 1U))
-                        {
-                            cbRange   -= uRangeEnd & (_4K - 1U);
-                            uRangeEnd &= ~(uint32_t)(_4K - 1U);
-                        }
-
-                        /* If there is still something, enable it.
-                           (We're a bit paranoid here don't trust the BIOS to only report a page once.)  */
-                        cPages = cbRange >> 12; /*div 4K*/
-                        if (cPages)
-                        {
-                            uRange -= _1M;
-                            i = uRange >> 12; /*div _4K*/
-                            while (cPages-- > 0)
-                            {
-                                uint16_t uLineToLong = ASMBitTestAndClear(g_Bs3Mem4KUpperTiled.Core.bmAllocated, i);
-                                g_Bs3Mem4KUpperTiled.Core.cFreeChunks += uLineToLong;
-                                i++;
-                            }
-                        }
-                    }
-                }
+            if (   Entry.uType == INT15E820_TYPE_USABLE
+                && Entry.uBaseAddr < BS3_SEL_TILED_AREA_SIZE)
+            {
+                /* Entry concerning tiled memory. Convert from 64-bit to 32-bit
+                   values and check whether it's concerning anything at or above 1MB  */
+                uint32_t uRange    = (uint32_t)Entry.uBaseAddr;
+                uint32_t cbRange   = Entry.cbRange >= BS3_SEL_TILED_AREA_SIZE
+                                   ? BS3_SEL_TILED_AREA_SIZE : (uint32_t)Entry.cbRange;
+                AssertCompile(BS3_SEL_TILED_AREA_SIZE <= _512M /* the range of 16-bit cPages. */ );
+                bs3InitMemoryAddRange(uRange, cbRange);
             }
         }
     }
+    /* Try the 286+ API for getting memory above 1MB and (usually) below 16MB. */
+    else if (   (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386
+             && (u32 = Bs3BiosInt15h88()) != UINT32_MAX
+             && u32 > 0)
+        bs3InitMemoryAddRange(_1M, u32 * _1K);
 
     /*