Changeset 60340 in vbox for trunk

Timestamp:

Apr 5, 2016 3:33:11 PM (9 years ago)

Author:

vboxsync

Message:

VMM/APIC: Bits.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (5 diffs)
• VMMR3/PDMDevMiscHlp.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -646 +646 @@
         {
             PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
-            if (   apicIsEnabled(pVCpuDest)                               /* PAV */
-                && apicIsLogicalDest(pVCpuDest, fDestMask))
+            if (apicIsLogicalDest(pVCpuDest, fDestMask))
             {
                 PCXAPICPAGE   pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpuDest);
@@ -1961 +1960 @@
 
     /* If the APIC is enabled, the interrupt is subject to LVT programming. */
-    if (   apicIsEnabled(pVCpu)
-        && pXApicPage->svr.u.fApicSoftwareEnable)
+    if (apicIsEnabled(pVCpu))
     {
         /* Pick the LVT entry corresponding to the interrupt pin. */
@@ -1974 +1972 @@
         uint32_t const uLvt   = apicReadRaw32(pXApicPage, offLvt);
 
-        /* If software hasn't masked the interrupt in the LVT entry, proceed with interrupt processing. */
+        /* If software hasn't masked the interrupt in the LVT entry, proceed interrupt processing. */
         if (!XAPIC_LVT_IS_MASKED(uLvt))
         {
@@ -2021 +2019 @@
     else
     {
-        /* If the APIC is disabled, pass it through the CPU. */
+        /* The APIC is disabled, pass it through the CPU. */
         if (u8Level)
             APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
@@ -2380 +2378 @@
  * Gets the highest priority pending interrupt.
  *
- * @returns true if any interrupt is pending, false otehrwise.
+ * @returns true if any interrupt is pending, false otherwise.
  * @param   pVCpu               The cross context virtual CPU structure.
  * @param   pu8PendingIntr      Where to store the interrupt vector if the

trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp

@@ -53 +53 @@
     PVM pVM = pDevIns->Internal.s.pVMR3;
     PVMCPU pVCpu = &pVM->aCpus[0];  /* for PIC we always deliver to CPU 0, MP use APIC */
-    /** @todo r=ramshankar: Should we raise the interrupt to all CPUs in the
-     *        guest, does real hardware do this? */
 
     if (pVM->pdm.s.Apic.pfnLocalInterruptR3)
     {
-        /** @todo r=ramshankar: Wouldn't we have to check here for APIC base MSR
-         *        disabling the APIC? */
         LogFlow(("pdmR3PicHlp_SetInterruptFF: caller='%s'/%d: Setting local interrupt on LAPIC\n",
                  pDevIns->pReg->szName, pDevIns->iInstance));