Index: /trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60429)
+++ /trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 60430)
@@ -440,9 +440,8 @@
  *                              performed in the current context.
  */
-static VBOXSTRICTRC apicSendIntr(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
+static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
                                  XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
 {
     VBOXSTRICTRC  rcStrict = VINF_SUCCESS;
-    PVM           pVM      = pVCpu->CTX_SUFF(pVM);
     VMCPUID const cCpus    = pVM->cCpus;
     switch (enmDeliveryMode)
@@ -816,5 +815,5 @@
     }
 
-    return apicSendIntr(pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
+    return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
 }
 
@@ -1195,5 +1194,5 @@
               || offLvt == XAPIC_OFF_LVT_LINT1
               || offLvt == XAPIC_OFF_LVT_ERROR,
-             ("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#x, uLvt=%#x\n", pVCpu->idCpu, offLvt, uLvt));
+             ("APIC%u: apicSetLvtEntry: invalid offset, offLvt=%#RX16, uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
 
     /*
@@ -1248,4 +1247,5 @@
         apicSetError(pVCpu, XAPIC_ESR_SEND_ILLEGAL_VECTOR);
 
+    Log4(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
     apicWriteRaw32(pXApicPage, offLvt, uLvt);
     return VINF_SUCCESS;
@@ -1268,5 +1268,5 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
-    AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#x\n", pVCpu->idCpu, offLvt));
+    AssertMsg(offLvt == XAPIC_OFF_CMCI, ("APIC%u: apicSetLvt1Entry: invalid offset %#RX16\n", pVCpu->idCpu, offLvt));
 
     /** @todo support CMCI. */
@@ -1390,5 +1390,5 @@
         {
             Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
-            rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "offReg=%#x Id=%u\n", offReg, pVCpu->idCpu);
+            rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, offReg);
             apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
             break;
@@ -1503,9 +1503,12 @@
         }
 
+        /* Read-only, write ignored: */
+        case XAPIC_OFF_VERSION:
+        case XAPIC_OFF_ID:
+            break;
+
         /* Unavailable/reserved in xAPIC mode: */
         case X2APIC_OFF_SELF_IPI:
         /* Read-only registers: */
-        case XAPIC_OFF_ID:
-        case XAPIC_OFF_VERSION:
         case XAPIC_OFF_PPR:
         case XAPIC_OFF_ISR0:    case XAPIC_OFF_ISR1:    case XAPIC_OFF_ISR2:    case XAPIC_OFF_ISR3:
@@ -1518,5 +1521,6 @@
         default:
         {
-            rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#x\n", pVCpu->idCpu, offReg);
+            rcStrict = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "APIC%u: offReg=%#RX16\n", pVCpu->idCpu,
+                                         offReg);
             apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS);
             break;
@@ -1947,5 +1951,6 @@
     VMCPUSET DestCpuSet;
     apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
-    VBOXSTRICTRC rcStrict = apicSendIntr(NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, VINF_SUCCESS);
+    VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
+                                         VINF_SUCCESS /* rcRZ */);
     return VBOXSTRICTRC_VAL(rcStrict);
 }
@@ -2002,5 +2007,4 @@
                 case XAPICDELIVERYMODE_NMI:
                 case XAPICDELIVERYMODE_INIT:    /** @todo won't work in R0/RC because callers don't care about rcRZ. */
-                case XAPICDELIVERYMODE_EXTINT:
                 {
                     VMCPUSET DestCpuSet;
@@ -2008,9 +2012,16 @@
                     VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
                     uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
-
-                    Log4(("APIC%u: APICLocalInterrupt: Sending interrupt. enmDeliveryMode=%u u8Pin=%u uVector=%u\n",
-                          pVCpu->idCpu, enmDeliveryMode, u8Pin, uVector));
-
-                    rcStrict = apicSendIntr(pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
+                    rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
+                                            rcRZ);
+                    break;
+                }
+
+                case XAPICDELIVERYMODE_EXTINT:
+                {
+                    Log4(("APIC%u: APICLocalInterrupt: External interrupt. u8Pin=%u u8Level=%u\n", pVCpu->idCpu, u8Pin, u8Level));
+                    if (u8Level)
+                        APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
+                    else
+                        APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
                     break;
                 }
@@ -2148,5 +2159,5 @@
 #endif
 
-    LogRel(("APIC%u: APICWriteMmio: offReg=%#RX16\n", pVCpu->idCpu, offReg));
+    LogRel(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
 
     int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
