Changeset 60444 in vbox

Timestamp:

Apr 12, 2016 7:57:12 AM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

106531

Message:

bs3-cpu-basic-2: two 286 adjustments while at it.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c (modified) (6 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c

@@ -349 +349 @@
 # if TMPL_BITS == 16
     bool const      f386Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386;
+    bool const      f286     = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286;
 # else
+    bool const      f286     = false;
     bool const      f386Plus = true;
     int             rc;
@@ -662 +664 @@
                     g_usBs3TestStep++;
 
-                    /* Modify the gate DPL to check that this is checked before SS.DPL and SS.PRESENT. */
+                    /* +1: Modify the gate DPL to check that this is checked before SS.DPL and SS.PRESENT. */
                     paIdt[0x83 << cIdteShift].Gate.u2Dpl = 2;
                     Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
@@ -669 +671 @@
                     g_usBs3TestStep++;
 
-                    /* Check the the CS.DPL check is done before the SS ones. Restoring the ring-0 INT 83
-                       context triggers the CS.DPL < CPL check. */
+                    /* +2: Check the the CS.DPL check is done before the SS ones. Restoring the
+                           ring-0 INT 83 context triggers the CS.DPL < CPL check. */
                     Bs3TrapSetJmpAndRestore(&Ctx83, &TrapCtx);
                     bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx83, BS3_SEL_TEST_PAGE_02);
                     g_usBs3TestStep++;
 
-                    /* Now mark the CS selector not present and check that that also triggers before SS stuff. */
+                    /* +3: Now mark the CS selector not present and check that that also triggers before SS stuff. */
                     Bs3GdteTestPage02.Gen.u1Present = 0;
                     Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
@@ -682 +684 @@
                     g_usBs3TestStep++;
 
-                    /* Make the CS selector some invalid type and check it triggers before SS stuff. */
+                    /* +4: Make the CS selector some invalid type and check it triggers before SS stuff. */
                     Bs3GdteTestPage02.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
                     Bs3GdteTestPage02.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
@@ -691 +693 @@
                     g_usBs3TestStep++;
 
-                    /* Now, make the CS selector limit too small and that it triggers after SS trouble. */
+                    /* +5: Now, make the CS selector limit too small and that it triggers after SS trouble.
+                           The 286 had a simpler approach to these GP(0). */
                     Bs3GdteTestPage02.Gen.u16LimitLow = 0;
                     Bs3GdteTestPage02.Gen.u4LimitHigh = 0;
                     Bs3GdteTestPage02.Gen.u1Granularity = 0;
                     Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
-                    if (iRpl != 2 || iRpl != iDpl || k >= 4)
+                    if (f286)
+                        bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, 0 /*uErrCd*/);
+                    else if (iRpl != 2 || iRpl != iDpl || k >= 4)
                         bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
                     else if (k != 0)
@@ -907 +912 @@
 
     /*
-     * IDT limit check.
+     * IDT limit check.  The 286 does not access X86DESCGATE::u16OffsetHigh.
      */
     g_usBs3TestStep = 5000;
     i = (0x80 << (cIdteShift + 3)) - 1;
-    j = (0x82 << (cIdteShift + 3)) - 1;
+    j = (0x82 << (cIdteShift + 3)) - (!f286 ? 1 : 3);
     k = (0x83 << (cIdteShift + 3)) - 1;
     for (; i <= k; i++, g_usBs3TestStep++)