Changeset 60459 in vbox

Timestamp:

Apr 12, 2016 2:31:58 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

106548

Message:

VMM/APIC: Don't forget to update level-triggered interrupts from the LevelPib to IRR and update TMR
for both level and edge-triggered interrupts.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (6 diffs)
• VMMR3/APIC.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -158 +158 @@
  * @param   idxFragment     The index of the 32-bit fragment in @a
  *                          pApicReg.
- * @param   u32Fragment     The 32-bit vector fragment.
+ * @param   u32Fragment     The 32-bit vector fragment to OR.
  */
 DECLINLINE(void) apicOrVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
@@ -164 +164 @@
     Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
     ASMAtomicOrU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
+}
+
+
+/**
+ * Atomically AND's a fragment (32 vectors) into an APIC
+ * 256-bit sparse register.
+ *
+ * @param   pApicReg        The APIC 256-bit spare register.
+ * @param   idxFragment     The index of the 32-bit fragment in @a
+ *                          pApicReg.
+ * @param   u32Fragment     The 32-bit vector fragment to AND.
+ */
+DECLINLINE(void) apicAndVectorsToReg(volatile XAPIC256BITREG *pApicReg, size_t idxFragment, uint32_t u32Fragment)
+{
+    Assert(idxFragment < RT_ELEMENTS(pApicReg->u));
+    ASMAtomicAndU32(&pApicReg->u[idxFragment].u32Reg, u32Fragment);
 }
 
@@ -1290 +1306 @@
 {
     Assert(pApicCpu);
-    Assert(TMTimerIsLockOwner(CTX_SUFF(pApicCpu->pTimer)));
+    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
 
     if (   pApicCpu->uHintedTimerInitialCount != uInitialCount
@@ -2397 +2413 @@
 
 /**
- * Updates pending interrupts from the pending interrupt bitmap to the IRR.
+ * Updates pending interrupts from the pending-interrupt bitmaps to the IRR.
  *
  * @param   pVCpu               The cross context virtual CPU structure.
@@ -2407 +2423 @@
     PAPICCPU   pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
+
+    /* Update edge-triggered pending interrupts. */
     for (;;)
     {
@@ -2418 +2436 @@
             uint32_t const uFragment = ASMAtomicXchgU32(&pPib->aVectorBitmap[i], 0);
             if (uFragment)
+            {
+                apicOrVectorsToReg(&pXApicPage->irr,  i,  uFragment);
+                apicAndVectorsToReg(&pXApicPage->tmr, i, ~uFragment);
+            }
+        }
+    }
+
+    /* Update level-triggered pending interrupts. */
+    for (;;)
+    {
+        bool const fAlreadySet = apicClearNotificationBitInPib(&pApicCpu->ApicPibLevel);
+        if (!fAlreadySet)
+            break;
+
+        PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
+        for (size_t i = 0; i < RT_ELEMENTS(pPib->aVectorBitmap); i++)
+        {
+            uint32_t const uFragment = ASMAtomicXchgU32(&pPib->aVectorBitmap[i], 0);
+            if (uFragment)
+            {
                 apicOrVectorsToReg(&pXApicPage->irr, i, uFragment);
+                apicOrVectorsToReg(&pXApicPage->tmr, i, uFragment);
+            }
         }
     }

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -384 +384 @@
     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
 
+    LogFlow(("APIC%u: APICR3Reset\n", pVCpu->idCpu));
+
 #ifdef RT_STRICT
     /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
@@ -429 +431 @@
 {
     VMCPU_ASSERT_EMT(pVCpu);
+    LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
     apicR3InitIpi(pVCpu);
 }