VirtualBox

Changeset 60464 in vbox


Ignore:
Timestamp:
Apr 12, 2016 4:56:07 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
106556
Message:

VMM/APIC: more logging

Location:
trunk/src/VBox
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • TabularUnified trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r60353 r60464  
    780780    GEN_CHECK_OFF(APICCPU, uHintedTimerInitialCount);
    781781    GEN_CHECK_OFF(APICCPU, uHintedTimerShift);
    782     GEN_CHECK_OFF(APICCPU, StatMmioReadGC);
     782    GEN_CHECK_OFF(APICCPU, StatMmioReadR0);
     783    GEN_CHECK_OFF(APICCPU, StatMmioReadR3);
     784    GEN_CHECK_OFF(APICCPU, StatMmioReadRC);
     785    GEN_CHECK_OFF(APICCPU, StatMmioWriteR0);
     786    GEN_CHECK_OFF(APICCPU, StatMmioWriteR3);
     787    GEN_CHECK_OFF(APICCPU, StatMmioWriteRC);
     788    GEN_CHECK_OFF(APICCPU, StatMsrReadR0);
     789    GEN_CHECK_OFF(APICCPU, StatMsrReadR3);
     790    GEN_CHECK_OFF(APICCPU, StatMsrReadRC);
     791    GEN_CHECK_OFF(APICCPU, StatMsrWriteR0);
     792    GEN_CHECK_OFF(APICCPU, StatMsrWriteR3);
     793    GEN_CHECK_OFF(APICCPU, StatMsrWriteRC);
    783794#else
    784795    /* PC/DevAPIC.cpp */

  • TabularUnified trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r60459 r60464  
    852852    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    853853    pXApicPage->icr_hi.all.u32IcrHi = uIcrHi & XAPIC_ICR_HI_DEST;
     854    Log4(("APIC%u: apicSetIcrHi: uIcrHi=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
     855
    854856    return VINF_SUCCESS;
    855857}
    … …  
    871873    PXAPICPAGE pXApicPage  = VMCPU_TO_XAPICPAGE(pVCpu);
    872874    pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR;
     875    Log4(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
    873876
    874877    apicSendIpi(pVCpu, rcRZ);
    … …  
    909912 * @returns Strict VBox status code.
    910913 * @param   pVCpu           The cross context virtual CPU structure.
    911  * @param   uValue          The ESR value.
    912  */
    913 static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uValue)
    914 {
    915     VMCPU_ASSERT_EMT(pVCpu);
     914 * @param   uEsr            The ESR value.
     915 */
     916static VBOXSTRICTRC apicSetEsr(PVMCPU pVCpu, uint32_t uEsr)
     917{
     918    VMCPU_ASSERT_EMT(pVCpu);
     919
     920    Log4(("APIC%u: apicSetEr: uEsr=%#RX32\n", pVCpu->idCpu, uEsr));
     921
    916922    if (   XAPIC_IN_X2APIC_MODE(pVCpu)
    917         && (uValue & ~XAPIC_ESR_WO))
     923        && (uEsr & ~XAPIC_ESR_WO))
    918924        return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
    919925
    … …  
    10061012    VMCPU_ASSERT_EMT(pVCpu);
    10071013
     1014    Log4(("APIC%u: apicSetEoi: uEoi=%#RX32\n", pVCpu->idCpu, uEoi));
     1015
    10081016    if (   XAPIC_IN_X2APIC_MODE(pVCpu)
    10091017        && (uEoi & ~XAPIC_EOI_WO))
    … …  
    10521060    Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
    10531061
     1062    Log4(("APIC%u: apicSetLdr: uLdr=%#RX32\n", pVCpu->idCpu, uLdr));
     1063
    10541064    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    10551065    apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR);
    … …  
    10721082    Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
    10731083
     1084    Log4(("APIC%u: apicSetDfr: uDfr=%#RX32\n", pVCpu->idCpu, uDfr));
     1085
    10741086    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    10751087    apicWriteRaw32(pXApicPage, XAPIC_OFF_DFR, uDfr & XAPIC_DFR);
    … …  
    10911103        && (uTimerDcr & ~XAPIC_TIMER_DCR))
    10921104        return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
     1105
     1106    Log4(("APIC%u: apicSetTimerDcr: uTimerDcr=%#RX32\n", pVCpu->idCpu, uTimerDcr));
    10931107
    10941108    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    … …  
    11741188        && pXApicPage->lvt_timer.u.u2TimerMode == XAPIC_TIMER_MODE_TSC_DEADLINE)
    11751189        return VINF_SUCCESS;
     1190
     1191    Log4(("APIC%u: apicSetTimerIcr: uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
    11761192
    11771193    /*
    … …  
    12671283
    12681284    Log4(("APIC%u: apicSetLvtEntry: offLvt=%#RX16 uLvt=%#RX32\n", pVCpu->idCpu, offLvt, uLvt));
     1285
    12691286    apicWriteRaw32(pXApicPage, offLvt, uLvt);
    12701287    return VINF_SUCCESS;
    … …  
    15691586        return VINF_CPUM_R3_MSR_READ;
    15701587
    1571     STAM_COUNTER_INC(&VMCPU_TO_APICCPU(pVCpu)->StatMsrRead);
     1588    STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrRead));
    15721589
    15731590    VBOXSTRICTRC rcStrict = VINF_SUCCESS;
    … …  
    16711688        return VINF_CPUM_R3_MSR_WRITE;
    16721689
    1673     STAM_COUNTER_INC(&VMCPU_TO_APICCPU(pVCpu)->StatMsrWrite);
     1690    STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMsrWrite));
    16741691
    16751692    /*
    … …  
    18461863                APICR3Reset(pVCpu);
    18471864                uBaseMsr &= ~(MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT);
     1865                Log4(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
    18481866#else
    18491867                return VINF_CPUM_R3_MSR_WRITE;
    … …  
    18601878                }
    18611879                uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
     1880                Log4(("APIC%u: Switched mode to xApic\n", pVCpu->idCpu));
    18621881                break;
    18631882            }
    … …  
    18841903                pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
    18851904                                                  | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
     1905                Log4(("APIC%u: Switched mode to x2Apic\n", pVCpu->idCpu));
    18861906                break;
    18871907            }
    … …  
    21082128            if (uTpr > 0 && uVector <= uTpr)
    21092129            {
    2110                 Log4(("APIC%u: APICGetInterrupt: Returns spurious vector %#x\n", pVCpu->idCpu,
     2130                Log4(("APIC%u: APICGetInterrupt: Spurious interrupt. uVector=%#x\n", pVCpu->idCpu,
    21112131                      pXApicPage->svr.u.u8SpuriousVector));
    21122132                return pXApicPage->svr.u.u8SpuriousVector;
    … …  
    21222142                apicSignalNextPendingIntr(pVCpu);
    21232143
    2124                 Log4(("APIC%u: APICGetInterrupt: Returns vector %#x\n", pVCpu->idCpu, uVector));
     2144                Log4(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
    21252145                return uVector;
    21262146            }
    … …  
    21462166    uint32_t uValue   = 0;
    21472167
    2148 #ifdef VBOX_WITH_STATISTICS
    2149     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    2150     STAM_COUNTER_INC(&CTXSUFF(pApicCpu->StatMmioRead));
    2151 #endif
     2168    STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead));
    21522169
    21532170    Log4(("APIC%u: ApicReadMmio: offReg=%#RX16\n", pVCpu->idCpu, offReg));
    … …  
    21732190    uint32_t uValue   = *(uint32_t *)pv;
    21742191
    2175 #ifdef VBOX_WITH_STATISTICS
    2176     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    2177     STAM_COUNTER_INC(&CTXSUFF(pApicCpu->StatMmioWrite));
    2178 #endif
     2192    STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
    21792193
    21802194    LogRel(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    … …  
    23342348
    23352349        case APICMODE_XAPIC:
     2350            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
     2351            break;
     2352
    23362353        case APICMODE_X2APIC:
    23372354            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);

  • TabularUnified trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r60459 r60464  
    891891    Assert(TMTimerIsLockOwner(pTimer));
    892892    Assert(pVCpu);
     893    LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
    893894
    894895    PXAPICPAGE     pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    … …  
    897898    {
    898899        uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
     900        Log4(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
    899901        APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
    900902    }
    … …  
    11901192    LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
    11911193            pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
     1194
     1195#ifdef VBOX_WITH_STATISTICS
     1196    /*
     1197     * Statistics.
     1198     */
     1199    /** @todo Figure out why doing this from apicR3Construct() it doesn't work. See @bugref{8245#c48} */
     1200#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
     1201    rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu)
     1202
     1203    bool const fHasRC = !HMIsEnabled(pVM);
     1204    for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
     1205    {
     1206        PVMCPU   pVCpu     = &pVM->aCpus[idCpu];
     1207        PAPICCPU pApicCpu  = VMCPU_TO_APICCPU(pVCpu);
     1208
     1209        APIC_REG_COUNTER(&pApicCpu->StatMmioReadR0,  "Number of APIC MMIO reads in R0.",  "/Devices/APIC/%u/R0/MmioRead");
     1210        APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR0, "Number of APIC MMIO writes in R0.", "/Devices/APIC/%u/R0/MmioWrite");
     1211        APIC_REG_COUNTER(&pApicCpu->StatMsrReadR0,   "Number of APIC MSR reads in R0.",   "/Devices/APIC/%u/R0/MsrRead");
     1212        APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR0,  "Number of APIC MSR writes in R0.",  "/Devices/APIC/%u/R0/MsrWrite");
     1213
     1214        APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3,  "Number of APIC MMIO reads in R3.",  "/Devices/APIC/%u/R3/MmioReadR3");
     1215        APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
     1216        APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3,   "Number of APIC MSR reads in R3.",   "/Devices/APIC/%u/R3/MsrReadR3");
     1217        APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3,  "Number of APIC MSR writes in R3.",  "/Devices/APIC/%u/R3/MsrWriteR3");
     1218
     1219        if (fHasRC)
     1220        {
     1221            APIC_REG_COUNTER(&pApicCpu->StatMmioReadRC,  "Number of APIC MMIO reads in RC.",  "/Devices/APIC/%u/RC/MmioRead");
     1222            APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRC, "Number of APIC MMIO writes in RC.", "/Devices/APIC/%u/RC/MmioWrite");
     1223            APIC_REG_COUNTER(&pApicCpu->StatMsrReadRC,   "Number of APIC MSR reads in RC.",   "/Devices/APIC/%u/RC/MsrRead");
     1224            APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC,  "Number of APIC MSR writes in RC.",  "/Devices/APIC/%u/RC/MsrWrite");
     1225        }
     1226    }
     1227# undef APIC_REG_ACCESS_COUNTER
     1228#endif
     1229
    11921230    return VINF_SUCCESS;
    11931231}
    … …  
    13601398            pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
    13611399
     1400#if 0
    13621401            rc = PDMR3CritSectInit(pVM, &pApicCpu->TimerCritSect, RT_SRC_POS, pApicCpu->szTimerDesc);
    13631402            if (RT_SUCCESS(rc))
    … …  
    13651404            else
    13661405                return rc;
     1406#else
     1407            return VINF_SUCCESS;
     1408#endif
    13671409        }
    13681410        else
    … …  
    13841426                              "Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", apicR3DbgInfo);
    13851427
    1386 #ifdef VBOX_WITH_STATISTICS
    1387     /*
    1388      * Statistics.
    1389      */
    1390     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
    1391     {
    1392         PVMCPU   pVCpu    = &pVM->aCpus[idCpu];
    1393         PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    1394         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMmioReadGC,  STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1395                                "Number of APIC MMIO reads in GC.",  "/Devices/APIC/%u/MmioReadGC",  idCpu);
    1396         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMmioReadHC,  STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1397                                "Number of APIC MMIO reads in HC.",  "/Devices/APIC/%u/MmioReadHC",  idCpu);
    1398 
    1399         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMmioWriteGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1400                                "Number of APIC MMIO writes in GC.", "/Devices/APIC/%u/MmioWriteGC", idCpu);
    1401         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMmioWriteHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1402                                "Number of APIC MMIO writes in HC.", "/Devices/APIC/%u/MmioWriteHC", idCpu);
    1403 
    1404         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMsrWrite,    STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1405                                "Number of APIC MSR writes.", "/Devices/APIC/%u/MsrWrite", idCpu);
    1406         PDMDevHlpSTAMRegisterF(pDevIns, &pApicCpu->StatMsrRead,     STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
    1407                                "Number of APIC MSR reads.",  "/Devices/APIC/%u/MsrRead",  idCpu);
    1408     }
    1409 #endif
    14101428    return VINF_SUCCESS;
    14111429}

  • TabularUnified trunk/src/VBox/VMM/include/APICInternal.h

    r60307 r60464  
    558558    /** @name APIC statistics.
    559559     * @{ */
    560     /** Number of MMIO reads in GC. */
    561     STAMCOUNTER                 StatMmioReadGC;
    562     /** Number of MMIO reads in GC. */
    563     STAMCOUNTER                 StatMmioReadHC;
    564     /** Number of MMIO writes in GC. */
    565     STAMCOUNTER                 StatMmioWriteGC;
    566     /** Number of MMIO writes in HC. */
    567     STAMCOUNTER                 StatMmioWriteHC;
    568     /** Number of MSR writes. */
    569     STAMCOUNTER                 StatMsrWrite;
    570     /** Number of MSR reads. */
    571     STAMCOUNTER                 StatMsrRead;
     560    /** Number of MMIO reads in R0. */
     561    STAMCOUNTER                 StatMmioReadR0;
     562    /** Number of MMIO reads in R3. */
     563    STAMCOUNTER                 StatMmioReadR3;
     564    /** Number of MMIO reads in RC. */
     565    STAMCOUNTER                 StatMmioReadRC;
     566
     567    /** Number of MMIO writes in R0. */
     568    STAMCOUNTER                 StatMmioWriteR0;
     569    /** Number of MMIO writes in R3. */
     570    STAMCOUNTER                 StatMmioWriteR3;
     571    /** Number of MMIO writes in RC. */
     572    STAMCOUNTER                 StatMmioWriteRC;
     573
     574    /** Number of MSR reads in R0. */
     575    STAMCOUNTER                 StatMsrReadR0;
     576    /** Number of MSR reads in R3. */
     577    STAMCOUNTER                 StatMsrReadR3;
     578    /** Number of MSR reads in RC. */
     579    STAMCOUNTER                 StatMsrReadRC;
     580
     581    /** Number of MSR writes in R0. */
     582    STAMCOUNTER                 StatMsrWriteR0;
     583    /** Number of MSR writes in R3. */
     584    STAMCOUNTER                 StatMsrWriteR3;
     585    /** Number of MSR writes in RC. */
     586    STAMCOUNTER                 StatMsrWriteRC;
    572587    /** @} */
    573588#endif
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