Changeset 60593 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Apr 20, 2016 11:02:38 AM (9 years ago)

Author:

vboxsync

Message:

VMM/APIC: Profiling and reduce 8 atomic ops to 4.

File:

• trunk/src/VBox/VMM/VMMR3/APIC.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -1184 +1184 @@
     ApicReg.pfnLocalInterruptR3     = APICLocalInterrupt;
     ApicReg.pfnGetTimerFreqR3       = APICGetTimerFreq;
-    if (pApic->fRZEnabled)
+
+    /*
+     * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
+     * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
+     * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
+     */
     {
         ApicReg.pszGetInterruptRC   = "APICGetInterrupt";
@@ -1264 +1269 @@
             pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
             pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
-#if 0
-            rc = PDMR3CritSectInit(pVM, &pApicCpu->TimerCritSect, RT_SRC_POS, pApicCpu->szTimerDesc);
-            AssertRCReturn(rc, rc);
-            TMR3TimerSetCritSect(pApicCpu->pTimerR3, &pApicCpu->TimerCritSect);
-#endif
         }
         else
@@ -1332 +1332 @@
         APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
                           "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
-        APIC_PROF_COUNTER(&pApicCpu->StatPostInterrupt, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
-    }
+        APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
+
+        APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending,  "Number of times an interrupt is already pending.",
+                         "/Devices/APIC/%u/PostInterruptAlreadyPending");
+    }
+# undef APIC_PROF_COUNTER
 # undef APIC_REG_ACCESS_COUNTER
 #endif