Changeset 60646 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Apr 22, 2016 12:59:40 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

106813

Message:

VMM/APIC: Go back to ring-3 for all base MSR writes for now. Logging and a couple of Windows build fixes with size_t and '==' instead of '=' (thanks Michal).

File:

• trunk/src/VBox/VMM/VMMR3/APIC.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -253 +253 @@
  * reset.
  *
- * @param   pVCpu           The cross context virtual CPU structure.
- */
-VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu)
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   fResetApicBaseMsr   Whether to reset the APIC base MSR.
+ */
+VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu, bool fResetApicBaseMsr)
 {
     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
@@ -291 +292 @@
     /** @todo It isn't clear in the spec. where exactly the default base address
      *        is (re)initialized, atm we do it here in Reset. */
-    apicR3ResetBaseMsr(pVCpu);
+    if (fResetApicBaseMsr)
+        apicR3ResetBaseMsr(pVCpu);
 
     /*
@@ -373 +375 @@
     PCXAPICPAGE  pXApicPage  = VMCPU_TO_CXAPICPAGE(pVCpu);
     PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
+
+    uint64_t const uBaseMsr  = pApicCpu->uApicBaseMsr;
+    APICMODE const enmMode   = apicGetMode(uBaseMsr);
     bool const   fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
 
-    pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC at %#RGp\n", pVCpu->idCpu, MSR_APICBASE_GET_PHYSADDR(pApicCpu->uApicBaseMsr));
-    pHlp->pfnPrintf(pHlp, "  Mode                          = %s\n", fX2ApicMode ? "x2Apic" : "xApic");
+    pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC:\n", pVCpu->idCpu);
+    pHlp->pfnPrintf(pHlp, "  APIC Base MSR                 = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
+                    MSR_APICBASE_GET_PHYSADDR(uBaseMsr));
+    pHlp->pfnPrintf(pHlp, "  Mode                          = %#x (%s)\n", enmMode, apicGetModeName(enmMode));
     if (fX2ApicMode)
     {
@@ -386 +393 @@
     pHlp->pfnPrintf(pHlp, "  Version                       = %#x\n",      pXApicPage->version.all.u32Version);
     pHlp->pfnPrintf(pHlp, "    APIC Version                = %#x\n",      pXApicPage->version.u.u8Version);
-    pHlp->pfnPrintf(pHlp, "    Max LVT entries             = %u\n",       pXApicPage->version.u.u8MaxLvtEntry);
+    pHlp->pfnPrintf(pHlp, "    Max LVT entry index (0..N)  = %u\n",       pXApicPage->version.u.u8MaxLvtEntry);
     pHlp->pfnPrintf(pHlp, "    EOI Broadcast supression    = %RTbool\n",  pXApicPage->version.u.fEoiBroadcastSupression);
     if (!fX2ApicMode)
@@ -929 +936 @@
             TMTimerStop(pApicCpu->pTimerR3);
 
-        APICR3Reset(pVCpuDest);
+        APICR3Reset(pVCpuDest, true /* fResetApicBaseMsr */);
 
         /* Clear the interrupt pending force flag. */
@@ -1070 +1077 @@
         if (fNeedsGCMapping)
         {
-            pApic->pvApicPibRC == NIL_RTRCPTR;
+            pApic->pvApicPibRC = NIL_RTRCPTR;
             int rc = MMR3HyperMapHCPhys(pVM, (void *)pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
                                         "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
@@ -1127 +1134 @@
 
                 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
-                size_t const offApicPib    = idCpu * sizeof(APICPIB);
+                uint32_t const offApicPib  = idCpu * sizeof(APICPIB);
                 pApicCpu->pvApicPibR0      = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
                 pApicCpu->pvApicPibR3      = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
@@ -1135 +1142 @@
                 /* Initialize the virtual-APIC state. */
                 memset((void *)pApicCpu->pvApicPageR3, 0, pApicCpu->cbApicPage);
-                APICR3Reset(pVCpu);
+                APICR3Reset(pVCpu, true /* fResetApicBaseMsr */);
 
 #ifdef DEBUG_ramshankar