VirtualBox

Changeset 60664 in vbox


Ignore:
Timestamp:
Apr 22, 2016 11:35:07 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
106832
Message:

VMM,ConsoleImpl2: Added 386 profile, adding IEM code for some obvious 386isms (EFLAGS and CR0/MSW).

Location:
trunk/src/VBox
Files:
5 edited
1 copied

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp

    r60509 r60664  
    989989         * dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
    990990         */
    991         if (   bstr.equals("Intel 80286")
     991        if (   bstr.equals("Intel 80386") /* just for now */
     992            || bstr.equals("Intel 80286")
    992993            || bstr.equals("Intel 80186")
    993994            || bstr.equals("Nec V20")

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r60377 r60664  
    715715        PGMCr0WpEnabled(pVCpu);
    716716
    717     pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
     717    /* The ET flag is settable on a 386 and hardwired on 486+. */
     718    if (   !(cr0 & X86_CR0_ET)
     719        && pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386)
     720        cr0 |= X86_CR0_ET;
     721
     722    pVCpu->cpum.s.Guest.cr0 = cr0;
    718723    return VINF_SUCCESS;
    719724}

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

    r60415 r60664  
    625625            }
    626626
    627             fEflNew &=   X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
    628             fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
     627            const uint32_t fPopfBits = IEMCPU_TO_VM(pIemCpu)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
     628                                     ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
     629            fEflNew &=   fPopfBits & ~(X86_EFL_IOPL);
     630            fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
    629631        }
    630632        /*
    … …  
    711713
    712714        /* Merge them with the current flags. */
     715        const uint32_t fPopfBits = IEMCPU_TO_VM(pIemCpu)->cpum.ro.GuestFeatures.enmMicroarch != kCpumMicroarch_Intel_80386
     716                                 ? X86_EFL_POPF_BITS : X86_EFL_POPF_BITS_386;
    713717        if (   (fEflNew & (X86_EFL_IOPL | X86_EFL_IF)) == (fEflOld & (X86_EFL_IOPL | X86_EFL_IF))
    714718            || pIemCpu->uCpl == 0)
    715719        {
    716             fEflNew &=  X86_EFL_POPF_BITS;
    717             fEflNew |= ~X86_EFL_POPF_BITS & fEflOld;
     720            fEflNew &=  fPopfBits;
     721            fEflNew |= ~fPopfBits & fEflOld;
    718722        }
    719723        else if (pIemCpu->uCpl <= X86_EFL_GET_IOPL(fEflOld))
    720724        {
    721             fEflNew &=   X86_EFL_POPF_BITS & ~(X86_EFL_IOPL);
    722             fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL)) & fEflOld;
     725            fEflNew &=   fPopfBits & ~(X86_EFL_IOPL);
     726            fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL)) & fEflOld;
    723727        }
    724728        else
    725729        {
    726             fEflNew &=   X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF);
    727             fEflNew |= ~(X86_EFL_POPF_BITS & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
     730            fEflNew &=   fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF);
     731            fEflNew |= ~(fPopfBits & ~(X86_EFL_IOPL | X86_EFL_IF)) & fEflOld;
    728732        }
    729733    }
    … …  
    27722776                   | X86_EFL_RF /*| X86_EFL_VM*/ | X86_EFL_AC /*|X86_EFL_VIF*/ /*|X86_EFL_VIP*/
    27732777                   | X86_EFL_ID;
     2778#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     2779        if (pIemCpu->uTargetCpu <= IEMTARGETCPU_386)
     2780            uNewFlags &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
     2781#endif
    27742782        uNewFlags |= Efl.u & (X86_EFL_VM | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_1);
    27752783    }
    … …  
    32553263        else if (pIemCpu->uCpl <= pCtx->eflags.Bits.u2IOPL)
    32563264            fEFlagsMask |= X86_EFL_IF;
     3265#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     3266        if (pIemCpu->uTargetCpu <= IEMTARGETCPU_386)
     3267            fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
     3268#endif
    32573269        uint32_t fEFlagsNew = IEMMISC_GET_EFL(pIemCpu, pCtx);
    32583270        fEFlagsNew         &= ~fEFlagsMask;
    … …  
    33273339        else if (pIemCpu->uCpl <= NewEfl.Bits.u2IOPL)
    33283340            fEFlagsMask |= X86_EFL_IF;
     3341#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     3342        if (pIemCpu->uTargetCpu <= IEMTARGETCPU_386)
     3343            fEFlagsMask &= ~(X86_EFL_AC | X86_EFL_ID | X86_EFL_VIF | X86_EFL_VIP);
     3344#endif
    33293345        NewEfl.u           &= ~fEFlagsMask;
    33303346        NewEfl.u           |= fEFlagsMask & uNewFlags;
    … …  
    47904806    switch (iCrReg)
    47914807    {
    4792         case 0: crX = pCtx->cr0; break;
     4808        case 0:
     4809            crX = pCtx->cr0;
     4810#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     4811            if (pIemCpu->uTargetCpu <= IEMTARGETCPU_386)
     4812                crX |= UINT32_C(0x7fffffe0); /* All reserved CR0 flags are set on a 386, just like MSW on 286. */
     4813#endif
     4814            break;
    47934815        case 2: crX = pCtx->cr2; break;
    47944816        case 3: crX = pCtx->cr3; break;
    … …  
    48434865             */
    48444866            uint64_t const uOldCrX = pCtx->cr0;
    4845             uNewCrX |= X86_CR0_ET; /* hardcoded */
     4867
     4868            /* ET is hardcoded on 486 and later. */
     4869#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     4870            if (pIemCpu->uTargetCpu >= IEMTARGETCPU_486)
     4871#endif
     4872                uNewCrX |= X86_CR0_ET; /* hardcoded on 486+ */
     4873#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
     4874            /* The 386 didn't #GP(0) on attempting to set reserved CR0 bits. ET was settable. */
     4875            else
     4876                uNewCrX &= X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG | X86_CR0_ET;
     4877#endif
    48464878
    48474879            /* Check for reserved bits. */

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstructions.cpp.h

    r60659 r60664  
    977977                IEM_MC_FETCH_CR0_U16(u16Tmp);
    978978#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
    979                 if (pIemCpu->uTargetCpu == IEMTARGETCPU_286)
    980                     IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0); /* Reserved bits observed all set on real hw. */
     979                if (pIemCpu->uTargetCpu > IEMTARGETCPU_386)
     980                { /* likely */ }
     981                else if (pIemCpu->uTargetCpu >= IEMTARGETCPU_386)
     982                    IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
     983                else
     984                    IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
    981985#endif
    982986                IEM_MC_STORE_GREG_U16((bRm & X86_MODRM_RM_MASK) | pIemCpu->uRexB, u16Tmp);
    … …  
    10151019        IEM_MC_FETCH_CR0_U16(u16Tmp);
    10161020#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
    1017         if (pIemCpu->uTargetCpu == IEMTARGETCPU_286)
    1018             IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0); /* Reserved bits observed all set on real hw. */
     1021        if (pIemCpu->uTargetCpu > IEMTARGETCPU_386)
     1022        { /* likely */ }
     1023        else if (pIemCpu->uTargetCpu >= IEMTARGETCPU_386)
     1024            IEM_MC_OR_LOCAL_U16(u16Tmp, 0xffe0);
     1025        else
     1026            IEM_MC_OR_LOCAL_U16(u16Tmp, 0xfff0);
    10191027#endif
    10201028        IEM_MC_STORE_MEM_U16(pIemCpu->iEffSeg, GCPtrEffDst, u16Tmp);

  • trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

    r60411 r60664  
    193193#include "cpus/Intel_Pentium_4_3_00GHz.h"
    194194#include "cpus/Intel_Atom_330_1_60GHz.h"
     195#include "cpus/Intel_80386.h"
    195196#include "cpus/Intel_80286.h"
    196197#include "cpus/Intel_80186.h"

  • trunk/src/VBox/VMM/VMMR3/cpus/Intel_80386.h

    r60585 r60664  
    11/* $Id$ */
    22/** @file
    3  * CPU database entry "Intel 80286".
     3 * CPU database entry "Intel 80386".
    44 * Handcrafted.
    55 */
    … …  
    1717 */
    1818
    19 #ifndef VBOX_CPUDB_Intel_80286
    20 #define VBOX_CPUDB_Intel_80286
     19#ifndef VBOX_CPUDB_Intel_80386
     20#define VBOX_CPUDB_Intel_80386
    2121
    2222#ifndef CPUM_DB_STANDALONE
    2323/**
    24  * Fake CPUID leaves for Intel(R) 80286.
     24 * Fake CPUID leaves for Intel(R) 80386.
    2525 *
    2626 * We fake these to keep the CPUM ignorant of CPUs wihtout CPUID leaves
    … …  
    2828 * CPUMDBENTRY.
    2929 */
    30 static CPUMCPUIDLEAF const g_aCpuIdLeaves_Intel_80286[] =
     30static CPUMCPUIDLEAF const g_aCpuIdLeaves_Intel_80386[] =
    3131{
    3232    { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x756e6547, 0x6c65746e, 0x49656e69, 0 },
    33     { 0x00000001, 0x00000000, 0x00000000, 0x00000200, 0x00000100, 0x00000000, 0x00000000, 0 },
     33    { 0x00000001, 0x00000000, 0x00000000, 0x00000300, 0x00000100, 0x00000000, 0x00000000, 0 },
    3434    { 0x80000000, 0x00000000, 0x00000000, 0x80000008, 0x00000000, 0x00000000, 0x00000000, 0 },
    3535    { 0x80000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0 },
    36     { 0x80000002, 0x00000000, 0x00000000, 0x65746e49, 0x2952286c, 0x32303820, 0x20203638, 0 },
     36    { 0x80000002, 0x00000000, 0x00000000, 0x65746e49, 0x2952286c, 0x33303820, 0x20203638, 0 },
    3737    { 0x80000003, 0x00000000, 0x00000000, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0 },
    3838    { 0x80000004, 0x00000000, 0x00000000, 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0 },
    … …  
    4545
    4646/**
    47  * Database entry for Intel(R) 80286.
     47 * Database entry for Intel(R) 80386.
    4848 */
    49 static CPUMDBENTRY const g_Entry_Intel_80286 =
     49static CPUMDBENTRY const g_Entry_Intel_80386 =
    5050{
    51     /*.pszName          = */ "Intel 80286",
    52     /*.pszFullName      = */ "Intel(R) 80286",
     51    /*.pszName          = */ "Intel 80386",
     52    /*.pszFullName      = */ "Intel(R) 80386",
    5353    /*.enmVendor        = */ CPUMCPUVENDOR_INTEL,
    54     /*.uFamily          = */ 2,
     54    /*.uFamily          = */ 3,
    5555    /*.uModel           = */ 0,
    5656    /*.uStepping        = */ 0,
    57     /*.enmMicroarch     = */ kCpumMicroarch_Intel_80286,
     57    /*.enmMicroarch     = */ kCpumMicroarch_Intel_80386,
    5858    /*.uScalableBusFreq = */ CPUM_SBUSFREQ_UNKNOWN,
    5959    /*.fFlags           = */ CPUDB_F_EXECUTE_ALL_IN_IEM,
    6060    /*.cMaxPhysAddrWidth= */ 24,
    61     /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_80286),
    62     /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_80286)),
     61    /*.paCpuIdLeaves    = */ NULL_ALONE(g_aCpuIdLeaves_Intel_80386),
     62    /*.cCpuIdLeaves     = */ ZERO_ALONE(RT_ELEMENTS(g_aCpuIdLeaves_Intel_80386)),
    6363    /*.enmUnknownCpuId  = */ CPUMUNKNOWNCPUID_DEFAULTS,
    6464    /*.DefUnknownCpuId  = */ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
    … …  
    6868};
    6969
    70 #endif /* !VBOX_CPUDB_Intel_80286 */
     70#endif /* !VBOX_CPUDB_Intel_80386 */
    7171
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