Changeset 60720 in vbox

Timestamp:

Apr 27, 2016 3:32:57 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

106907

Message:

VMM/APIC: Fixes for getting x2APIC mode working.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (5 diffs)
• VMMR3/APIC.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -1975 +1975 @@
     }
 
+    /* Don't allow enabling xAPIC/x2APIC if the VM is configured with the APIC disabled. */
+    if (pApic->enmOriginalMode == APICMODE_DISABLED)
+    {
+        LogRel(("APIC%u: Disallowing APIC base MSR write as the VM config is configured with APIC disabled!\n"));
+        return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
+    }
+
     /*
      * Act on state transition.
@@ -1999 +2006 @@
                 APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
                 uBaseMsr &= ~(MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT);
-
-                APICUpdateCpuIdForMode(pVCpu->CTX_SUFF(pVM), APICMODE_DISABLED);
+                CPUMClearGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
                 LogRel(("APIC%u: Switched mode to disabled\n", pVCpu->idCpu));
                 break;
@@ -2013 +2019 @@
                 }
 
-                /* Don't allow enabling xAPIC if the VM is configured with a APIC disabled. */
-                if (pApic->enmOriginalMode != APICMODE_DISABLED)
-                {
-                    uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
-                    APICUpdateCpuIdForMode(pVCpu->CTX_SUFF(pVM), APICMODE_XAPIC);
-                    LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
-                }
-                else
-                    return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
+                uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
+                CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
+                LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
                 break;
             }
@@ -2033 +2033 @@
                 }
 
-                /* Don't allow enabling x2APIC if the VM is configured with a APIC disabled. */
-                if (pApic->enmOriginalMode != APICMODE_DISABLED)
-                {
-                    uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT;
-
-                    /*
-                     * The APIC ID needs updating when entering x2APIC mode.
-                     * Software written APIC ID in xAPIC mode isn't preseved.
-                     * The APIC ID becomes read-only to software in x2APIC mode.
-                     *
-                     * See Intel spec. 10.12.5.1 "x2APIC States".
-                     */
-                    PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
-                    ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
-                    pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
-
-                    /*
-                     * LDR initialization occurs when entering x2APIC mode.
-                     * See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
-                     */
-                    pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
-                                                      | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
-
-                    LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
-                }
-                else
-                    return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
+                /* Don't allow enabling x2APIC if the VM is configured with the APIC disabled. */
+                uBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT | MSR_APICBASE_X2APIC_ENABLE_BIT;
+
+                /*
+                 * The APIC ID needs updating when entering x2APIC mode.
+                 * Software written APIC ID in xAPIC mode isn't preseved.
+                 * The APIC ID becomes read-only to software in x2APIC mode.
+                 *
+                 * See Intel spec. 10.12.5.1 "x2APIC States".
+                 */
+                PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
+                ASMMemZero32(&pX2ApicPage->id, sizeof(pX2ApicPage->id));
+                pX2ApicPage->id.u32ApicId = pVCpu->idCpu;
+
+                /*
+                 * LDR initialization occurs when entering x2APIC mode.
+                 * See Intel spec. 10.12.10.2 "Deriving Logical x2APIC ID from the Local x2APIC ID".
+                 */
+                pX2ApicPage->ldr.u32LogicalApicId = ((pX2ApicPage->id.u32ApicId & UINT32_C(0xffff0)) << 16)
+                                                  | (UINT32_C(1) << pX2ApicPage->id.u32ApicId & UINT32_C(0xf));
+
+                LogRel(("APIC%u: Switched mode to x2APIC\n", pVCpu->idCpu));
                 break;
             }
@@ -2574 +2569 @@
 
 /**
- * Updates the CPUID bits necessary for the given APIC mode.
- *
- * @param   pVM         The cross context VM structure.
- * @param   enmMode     The APIC mode.
- */
-VMM_INT_DECL(void) APICUpdateCpuIdForMode(PVM pVM, APICMODE enmMode)
-{
-    LogFlow(("APIC: APICUpdateCpuIdForMode: enmMode=%d (%s)\n", enmMode, apicGetModeName(enmMode)));
-
-    /* The CPUID bits being updated to reflect the current state is a bit vague. See @bugref{8245#c32}. */
-    /** @todo This needs to be done on a per-VCPU basis! */
-    switch (enmMode)
-    {
-        case APICMODE_DISABLED:
-            CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
-            break;
-
-        case APICMODE_XAPIC:
-            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
-            break;
-
-        case APICMODE_X2APIC:
-            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
-            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
-            break;
-
-        default:
-            AssertMsgFailed(("Invalid APIC mode: %d\n", (int)enmMode));
-            break;
-    }
-}
-
-
-/**
  * Queues a pending interrupt as in-service.
  *

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -244 +244 @@
 
     /* Construct. */
-    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
-    uint64_t uApicBaseMsr = XAPIC_APICBASE_PHYSADDR
-                          | MSR_APICBASE_XAPIC_ENABLE_BIT;
+    PAPICCPU pApicCpu     = VMCPU_TO_APICCPU(pVCpu);
+    PAPIC    pApic        = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
+    uint64_t uApicBaseMsr = XAPIC_APICBASE_PHYSADDR;
     if (pVCpu->idCpu == 0)
         uApicBaseMsr |= MSR_APICBASE_BOOTSTRAP_CPU_BIT;
 
-    /* Update CPUID. */
-    APICUpdateCpuIdForMode(pVCpu->CTX_SUFF(pVM), APICMODE_XAPIC);
-    LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
+    /* If the VM was configured with disabled mode, don't enable xAPIC mode. */
+    if (pApic->enmOriginalMode != APICMODE_DISABLED)
+    {
+        uApicBaseMsr |= MSR_APICBASE_XAPIC_ENABLE_BIT;
+
+        /** @todo CPUID bits needs to be done on a per-VCPU basis! */
+        CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
+        LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
+    }
 
     /* Commit. */
@@ -1452 +1458 @@
     rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
     AssertLogRelRCReturn(rc, rc);
+
     /* Validate APIC modes. */
-    switch (uOriginalMode)
+    APICMODE const enmOriginalMode = (APICMODE)uOriginalMode;
+    switch (enmOriginalMode)
     {
         case APICMODE_DISABLED:
+            pApic->enmOriginalMode = enmOriginalMode;
+            CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
+            CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
+            break;
+
         case APICMODE_X2APIC:
+            pApic->enmOriginalMode = enmOriginalMode;
+            CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
+            break;
+
         case APICMODE_XAPIC:
-            pApic->enmOriginalMode = (APICMODE)uOriginalMode;
+            pApic->enmOriginalMode = enmOriginalMode;
+            /* The CPUID bit will be updated in apicR3ResetBaseMsr(). */
             break;
+
         default:
             return VMR3SetError(pVM->pUVM, VERR_INVALID_STATE, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);