Changeset 60762 in vbox
- Timestamp:
- Apr 29, 2016 1:39:25 PM (9 years ago)
- svn:sync-xref-src-repo-rev:
- 106957
- Location:
- trunk
- Files:
-
- 1 added
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/cpum.h
r60412 r60762 251 251 #define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \ 252 252 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End) 253 254 /** Predicate macro for catching Atom CPUs, Silvermont and upwards. */ 255 #define CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(a_enmMicroarch) \ 256 ((a_enmMicroarch) >= kCpumMicroarch_Intel_Atom_Silvermont && (a_enmMicroarch) <= kCpumMicroarch_Intel_Atom_End) 253 257 254 258 /** Predicate macro for catching AMD Family OFh CPUs (aka K8). */ … … 438 442 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */ 439 443 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */ 444 kCpumMsrRdFn_Ia32VmxVmFunc, /**< Takes real value as reference. */ 440 445 441 446 kCpumMsrRdFn_Amd64Efer, … … 515 520 kCpumMsrRdFn_IntelI7UncArbPerfCtrN, 516 521 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN, 522 kCpumMsrRdFn_IntelI7SmiCount, 517 523 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */ 518 524 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo, … … 520 526 kCpumMsrRdFn_IntelCore1DtsCalControl, 521 527 kCpumMsrRdFn_IntelCore2PeciControl, 528 kCpumMsrRdFn_IntelAtSilvCoreC1Recidency, 522 529 523 530 kCpumMsrRdFn_P6LastBranchFromIp, … … 727 734 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig, 728 735 kCpumMsrWrFn_IntelI7SandyVrMiscConfig, 736 kCpumMsrWrFn_IntelI7SandyRaplPowerUnit, /**< R/O but found writable bits on a Silvermont CPU here. */ 729 737 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN, 738 kCpumMsrWrFn_IntelI7SandyPkgC2Residency, /**< R/O but found writable bits on a Silvermont CPU here. */ 730 739 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit, 731 740 kCpumMsrWrFn_IntelI7RaplDramPowerLimit, -
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r60377 r60762 1267 1267 /** @callback_method_impl{FNCPUMRDMSR} */ 1268 1268 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxTrueEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1269 { 1270 *puValue = 0; 1271 return VINF_SUCCESS; 1272 } 1273 1274 1275 /** @callback_method_impl{FNCPUMRDMSR} */ 1276 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxVmFunc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 1269 1277 { 1270 1278 *puValue = 0; … … 2172 2180 2173 2181 2182 /** @callback_method_impl{FNCPUMWRMSR} */ 2183 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyRaplPowerUnit(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2184 { 2185 /* Note! This is documented as read only and except for a Silvermont sample has 2186 always been classified as read only. This is just here to make it compile. */ 2187 return VINF_SUCCESS; 2188 } 2189 2190 2174 2191 /** @callback_method_impl{FNCPUMRDMSR} */ 2175 2192 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SandyPkgCnIrtlN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) … … 2194 2211 /** @todo intel power management. */ 2195 2212 *puValue = 0; 2213 return VINF_SUCCESS; 2214 } 2215 2216 2217 /** @callback_method_impl{FNCPUMWRMSR} */ 2218 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrWr_IntelI7SandyPkgC2Residency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) 2219 { 2220 /* Note! This is documented as read only and except for a Silvermont sample has 2221 always been classified as read only. This is just here to make it compile. */ 2196 2222 return VINF_SUCCESS; 2197 2223 } … … 2571 2597 2572 2598 /** @callback_method_impl{FNCPUMRDMSR} */ 2599 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelI7SmiCount(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2600 { 2601 /* 2602 * 31:0 is SMI count (read only), 63:32 reserved. 2603 * Since we don't do SMI, the count is always zero. 2604 */ 2605 *puValue = 0; 2606 return VINF_SUCCESS; 2607 } 2608 2609 2610 /** @callback_method_impl{FNCPUMRDMSR} */ 2573 2611 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelCore2EmttmCrTablesN(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2574 2612 { … … 2654 2692 } 2655 2693 2694 2695 /** @callback_method_impl{FNCPUMRDMSR} */ 2696 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_IntelAtSilvCoreC1Recidency(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) 2697 { 2698 *puValue = 0; 2699 return VINF_SUCCESS; 2700 } 2656 2701 2657 2702 … … 4475 4520 cpumMsrRd_Ia32VmxTrueExitCtls, 4476 4521 cpumMsrRd_Ia32VmxTrueEntryCtls, 4522 cpumMsrRd_Ia32VmxVmFunc, 4477 4523 4478 4524 cpumMsrRd_Amd64Efer, … … 4552 4598 cpumMsrRd_IntelI7UncArbPerfCtrN, 4553 4599 cpumMsrRd_IntelI7UncArbPerfEvtSelN, 4600 cpumMsrRd_IntelI7SmiCount, 4554 4601 cpumMsrRd_IntelCore2EmttmCrTablesN, 4555 4602 cpumMsrRd_IntelCore2SmmCStMiscInfo, … … 4557 4604 cpumMsrRd_IntelCore1DtsCalControl, 4558 4605 cpumMsrRd_IntelCore2PeciControl, 4606 cpumMsrRd_IntelAtSilvCoreC1Recidency, 4559 4607 4560 4608 cpumMsrRd_P6LastBranchFromIp, … … 4756 4804 cpumMsrWr_IntelI7SandyVrCurrentConfig, 4757 4805 cpumMsrWr_IntelI7SandyVrMiscConfig, 4806 cpumMsrWr_IntelI7SandyRaplPowerUnit, 4758 4807 cpumMsrWr_IntelI7SandyPkgCnIrtlN, 4808 cpumMsrWr_IntelI7SandyPkgC2Residency, 4759 4809 cpumMsrWr_IntelI7RaplPkgPowerLimit, 4760 4810 cpumMsrWr_IntelI7RaplDramPowerLimit, … … 5183 5233 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueExitCtls); 5184 5234 CPUM_ASSERT_RD_MSR_FN(Ia32VmxTrueEntryCtls); 5235 CPUM_ASSERT_RD_MSR_FN(Ia32VmxVmFunc); 5185 5236 5186 5237 CPUM_ASSERT_RD_MSR_FN(Amd64Efer); … … 5260 5311 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfCtrN); 5261 5312 CPUM_ASSERT_RD_MSR_FN(IntelI7UncArbPerfEvtSelN); 5313 CPUM_ASSERT_RD_MSR_FN(IntelI7SmiCount); 5262 5314 CPUM_ASSERT_RD_MSR_FN(IntelCore2EmttmCrTablesN); 5263 5315 CPUM_ASSERT_RD_MSR_FN(IntelCore2SmmCStMiscInfo); … … 5265 5317 CPUM_ASSERT_RD_MSR_FN(IntelCore1DtsCalControl); 5266 5318 CPUM_ASSERT_RD_MSR_FN(IntelCore2PeciControl); 5319 CPUM_ASSERT_RD_MSR_FN(IntelAtSilvCoreC1Recidency); 5267 5320 5268 5321 CPUM_ASSERT_RD_MSR_FN(P6LastBranchFromIp); … … 5454 5507 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyVrMiscConfig); 5455 5508 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgCnIrtlN); 5509 CPUM_ASSERT_WR_MSR_FN(IntelI7SandyPkgC2Residency); 5456 5510 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplPkgPowerLimit); 5457 5511 CPUM_ASSERT_WR_MSR_FN(IntelI7RaplDramPowerLimit); -
trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp
r60757 r60762 192 192 #include "cpus/Intel_Pentium_M_processor_2_00GHz.h" 193 193 #include "cpus/Intel_Pentium_4_3_00GHz.h" 194 #include "cpus/Intel_Pentium_N3530_2_16GHz.h" 194 195 #include "cpus/Intel_Atom_330_1_60GHz.h" 195 196 #include "cpus/Intel_80386.h" … … 236 237 #ifdef VBOX_CPUDB_Intel_Core_i7_2635QM 237 238 &g_Entry_Intel_Core_i7_2635QM, 239 #endif 240 #ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz 241 &g_Entry_Intel_Pentium_N3530_2_16GHz, 238 242 #endif 239 243 #ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz -
trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_5600U.h
r58568 r60762 237 237 MFX(0x0000048f, "IA32_VMX_TRUE_EXIT_CTLS", Ia32VmxTrueExitCtls, ReadOnly, UINT64_C(0x7fffff00036dfb), 0, 0), /* value=0x7fffff`00036dfb */ 238 238 MFX(0x00000490, "IA32_VMX_TRUE_ENTRY_CTLS", Ia32VmxTrueEntryCtls, ReadOnly, UINT64_C(0xffff000011fb), 0, 0), /* value=0xffff`000011fb */ 239 M VO(0x00000491, "TODO_0000_0491", 0x1),239 MFX(0x00000491, "IA32_VMX_VMFUNC", Ia32VmxVmFunc, ReadOnly, 0x1, 0, 0), /* value=0x1 */ 240 240 RSN(0x000004c1, 0x000004c4, "IA32_A_PMCn", Ia32PmcN, Ia32PmcN, 0x0, 0, UINT64_C(0xffff000000000000)), 241 241 MVO(0x000004e0, "TODO_0000_04e0", 0x1), -
trunk/src/VBox/VMM/VMMR3/cpus/Intel_Core_i7_6700K.h
r58653 r60762 259 259 MFX(0x0000048f, "IA32_VMX_TRUE_EXIT_CTLS", Ia32VmxTrueExitCtls, ReadOnly, UINT64_C(0x1ffffff00036dfb), 0, 0), /* value=0x1ffffff`00036dfb */ 260 260 MFX(0x00000490, "IA32_VMX_TRUE_ENTRY_CTLS", Ia32VmxTrueEntryCtls, ReadOnly, UINT64_C(0x3ffff000011fb), 0, 0), /* value=0x3ffff`000011fb */ 261 M VO(0x00000491, "TODO_0000_0491", 0x1),261 MFX(0x00000491, "IA32_VMX_VMFUNC", Ia32VmxVmFunc, ReadOnly, 0x1, 0, 0), /* value=0x1 */ 262 262 RSN(0x000004c1, 0x000004c4, "IA32_A_PMCn", Ia32PmcN, Ia32PmcN, 0x0, 0, UINT64_C(0xffff000000000000)), 263 263 MVO(0x000004e0, "TODO_0000_04e0", 0x5), -
trunk/src/VBox/VMM/tools/VBoxCpuReport.cpp
r58676 r60762 633 633 case 0x00000032: return "P6_UNK_0000_0032"; /* P6_M_Dothan. */ 634 634 case 0x00000033: return "TEST_CTL"; 635 case 0x00000034: return "P6_UNK_0000_0034"; /* P6_M_Dothan. */ 635 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) 636 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch) 637 ? "MSR_SMI_COUNT" : "P6_UNK_0000_0034"; /* P6_M_Dothan. */ 636 638 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "MSR_CORE_THREAD_COUNT" : "P6_UNK_0000_0035"; /* P6_M_Dothan. */ 637 639 case 0x00000036: return "I7_UNK_0000_0036"; /* SandyBridge, IvyBridge. */ … … 727 729 case 0x0000011c: return "C2_UNK_0000_011c"; /* Core2_Penryn. */ 728 730 case 0x0000011e: return "BBL_CR_CTL3"; 731 case 0x00000120: return "SILV_UNK_0000_0120"; /* Silvermont */ 729 732 case 0x00000130: return g_enmMicroarch == kCpumMicroarch_Intel_Core7_Westmere 730 733 || g_enmMicroarch == kCpumMicroarch_Intel_Core7_Nehalem … … 1039 1042 case 0x0000048f: return "IA32_VMX_TRUE_EXIT_CTLS"; 1040 1043 case 0x00000490: return "IA32_VMX_TRUE_ENTRY_CTLS"; 1044 case 0x00000491: return "IA32_VMX_VMFUNC"; 1041 1045 case 0x000004c1: return "IA32_A_PMC0"; 1042 1046 case 0x000004c2: return "IA32_A_PMC1"; … … 1091 1095 case 0x0000064b: return "I7_IB_MSR_CONFIG_TDP_CONTROL"; 1092 1096 case 0x0000064c: return "I7_IB_MSR_TURBO_ACTIVATION_RATIO"; 1097 case 0x00000660: return "SILV_CORE_C1_RESIDENCY"; 1098 case 0x00000661: return "SILV_UNK_0000_0661"; 1099 case 0x00000662: return "SILV_UNK_0000_0662"; 1100 case 0x00000663: return "SILV_UNK_0000_0663"; 1101 case 0x00000664: return "SILV_UNK_0000_0664"; 1102 case 0x00000665: return "SILV_UNK_0000_0665"; 1103 case 0x00000666: return "SILV_UNK_0000_0666"; 1104 case 0x00000667: return "SILV_UNK_0000_0667"; 1105 case 0x00000668: return "SILV_UNK_0000_0668"; 1106 case 0x00000669: return "SILV_UNK_0000_0669"; 1107 case 0x0000066a: return "SILV_UNK_0000_066a"; 1108 case 0x0000066b: return "SILV_UNK_0000_066b"; 1109 case 0x0000066c: return "SILV_UNK_0000_066c"; 1110 case 0x0000066d: return "SILV_UNK_0000_066d"; 1111 case 0x0000066e: return "SILV_UNK_0000_066e"; 1112 case 0x0000066f: return "SILV_UNK_0000_066f"; 1113 case 0x00000670: return "SILV_UNK_0000_0670"; 1114 case 0x00000671: return "SILV_UNK_0000_0671"; 1115 case 0x00000672: return "SILV_UNK_0000_0672"; 1116 case 0x00000673: return "SILV_UNK_0000_0673"; 1117 case 0x00000674: return "SILV_UNK_0000_0674"; 1118 case 0x00000675: return "SILV_UNK_0000_0675"; 1119 case 0x00000676: return "SILV_UNK_0000_0676"; 1120 case 0x00000677: return "SILV_UNK_0000_0677"; 1121 1093 1122 case 0x00000680: return "MSR_LASTBRANCH_0_FROM_IP"; 1094 1123 case 0x00000681: return "MSR_LASTBRANCH_1_FROM_IP"; … … 1124 1153 case 0x000006cf: return "MSR_LASTBRANCH_15_TO_IP"; 1125 1154 case 0x000006e0: return "IA32_TSC_DEADLINE"; 1155 1156 case 0x00000768: return "SILV_UNK_0000_0768"; 1157 case 0x00000769: return "SILV_UNK_0000_0769"; 1158 case 0x0000076a: return "SILV_UNK_0000_076a"; 1159 case 0x0000076b: return "SILV_UNK_0000_076b"; 1160 case 0x0000076c: return "SILV_UNK_0000_076c"; 1161 case 0x0000076d: return "SILV_UNK_0000_076d"; 1162 case 0x0000076e: return "SILV_UNK_0000_076e"; 1126 1163 1127 1164 case 0x00000c80: return g_enmMicroarch >= kCpumMicroarch_Intel_Core7_IvyBridge ? "IA32_DEBUG_INTERFACE" : NULL; /* Mentioned in an intel dataskit called 4th-gen-core-family-desktop-vol-1-datasheet.pdf. */ … … 1878 1915 case 0x0000002c: *pfTakesValue = true; return g_fIntelNetBurst ? "IntelP4EbcFrequencyId" : NULL; 1879 1916 //case 0x00000033: return "IntelTestCtl"; 1917 case 0x00000034: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) 1918 || CPUMMICROARCH_IS_INTEL_SILVERMONT_PLUS(g_enmMicroarch) 1919 ? "IntelI7SmiCount" : NULL; 1880 1920 case 0x00000035: return CPUMMICROARCH_IS_INTEL_CORE7(g_enmMicroarch) ? "IntelI7CoreThreadCount" : NULL; 1881 1921 case 0x0000003a: return "Ia32FeatureControl"; … … 2067 2107 case 0x0000048f: *pfTakesValue = true; return "Ia32VmxTrueExitCtls"; 2068 2108 case 0x00000490: *pfTakesValue = true; return "Ia32VmxTrueEntryCtls"; 2109 case 0x00000491: *pfTakesValue = true; return "Ia32VmxVmFunc"; 2069 2110 2070 2111 case 0x000004c1: … … 2081 2122 2082 2123 case 0x00000600: return "Ia32DsArea"; 2083 case 0x00000601: return "IntelI7SandyVrCurrentConfig";2084 case 0x00000603: return "IntelI7SandyVrMiscConfig";2085 case 0x00000606: return "IntelI7SandyRaplPowerUnit";2086 case 0x0000060a: return "IntelI7SandyPkgCnIrtlN";2087 case 0x0000060b: return "IntelI7SandyPkgCnIrtlN";2088 case 0x0000060c: return "IntelI7SandyPkgCnIrtlN";2089 case 0x0000060d: return "IntelI7SandyPkgC2Residency";2090 2091 case 0x00000610: return "IntelI7RaplPkgPowerLimit";2092 case 0x00000611: return "IntelI7RaplPkgEnergyStatus";2093 case 0x00000613: return "IntelI7RaplPkgPerfStatus";2094 case 0x00000614: return "IntelI7RaplPkgPowerInfo";2095 case 0x00000618: return "IntelI7RaplDramPowerLimit";2096 case 0x00000619: return "IntelI7RaplDramEnergyStatus";2097 case 0x0000061b: return "IntelI7RaplDramPerfStatus";2098 case 0x0000061c: return "IntelI7RaplDramPowerInfo";2099 case 0x00000638: return "IntelI7RaplPp0PowerLimit";2100 case 0x00000639: return "IntelI7RaplPp0EnergyStatus";2101 case 0x0000063a: return "IntelI7RaplPp0Policy";2102 case 0x0000063b: return "IntelI7RaplPp0PerfStatus";2103 case 0x00000640: return "IntelI7RaplPp1PowerLimit";2104 case 0x00000641: return "IntelI7RaplPp1EnergyStatus";2105 case 0x00000642: return "IntelI7RaplPp1Policy";2106 case 0x00000648: return "IntelI7IvyConfigTdpNominal";2107 case 0x00000649: return "IntelI7IvyConfigTdpLevel1";2108 case 0x0000064a: return "IntelI7IvyConfigTdpLevel2";2124 case 0x00000601: *pfTakesValue = true; return "IntelI7SandyVrCurrentConfig"; 2125 case 0x00000603: *pfTakesValue = true; return "IntelI7SandyVrMiscConfig"; 2126 case 0x00000606: *pfTakesValue = true; return "IntelI7SandyRaplPowerUnit"; 2127 case 0x0000060a: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN"; 2128 case 0x0000060b: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN"; 2129 case 0x0000060c: *pfTakesValue = true; return "IntelI7SandyPkgCnIrtlN"; 2130 case 0x0000060d: *pfTakesValue = true; return "IntelI7SandyPkgC2Residency"; 2131 2132 case 0x00000610: *pfTakesValue = true; return "IntelI7RaplPkgPowerLimit"; 2133 case 0x00000611: *pfTakesValue = true; return "IntelI7RaplPkgEnergyStatus"; 2134 case 0x00000613: *pfTakesValue = true; return "IntelI7RaplPkgPerfStatus"; 2135 case 0x00000614: *pfTakesValue = true; return "IntelI7RaplPkgPowerInfo"; 2136 case 0x00000618: *pfTakesValue = true; return "IntelI7RaplDramPowerLimit"; 2137 case 0x00000619: *pfTakesValue = true; return "IntelI7RaplDramEnergyStatus"; 2138 case 0x0000061b: *pfTakesValue = true; return "IntelI7RaplDramPerfStatus"; 2139 case 0x0000061c: *pfTakesValue = true; return "IntelI7RaplDramPowerInfo"; 2140 case 0x00000638: *pfTakesValue = true; return "IntelI7RaplPp0PowerLimit"; 2141 case 0x00000639: *pfTakesValue = true; return "IntelI7RaplPp0EnergyStatus"; 2142 case 0x0000063a: *pfTakesValue = true; return "IntelI7RaplPp0Policy"; 2143 case 0x0000063b: *pfTakesValue = true; return "IntelI7RaplPp0PerfStatus"; 2144 case 0x00000640: *pfTakesValue = true; return "IntelI7RaplPp1PowerLimit"; 2145 case 0x00000641: *pfTakesValue = true; return "IntelI7RaplPp1EnergyStatus"; 2146 case 0x00000642: *pfTakesValue = true; return "IntelI7RaplPp1Policy"; 2147 case 0x00000648: *pfTakesValue = true; return "IntelI7IvyConfigTdpNominal"; 2148 case 0x00000649: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel1"; 2149 case 0x0000064a: *pfTakesValue = true; return "IntelI7IvyConfigTdpLevel2"; 2109 2150 case 0x0000064b: return "IntelI7IvyConfigTdpControl"; 2110 2151 case 0x0000064c: return "IntelI7IvyTurboActivationRatio"; 2152 2153 case 0x00000660: return "IntelAtSilvCoreC1Recidency"; 2111 2154 2112 2155 case 0x00000680: case 0x00000681: case 0x00000682: case 0x00000683:
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