Changeset 60996 in vbox

Timestamp:

May 17, 2016 9:48:23 AM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

107246

Message:

x86: Added two more CPUID bit definitions.

Location:

trunk

Files:

• include/iprt/x86.h (modified) (2 diffs)
• src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp (modified) (3 diffs)

trunk/include/iprt/x86.h

@@ -547 +547 @@
 /** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
 #define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST        RT_BIT_32(1)
+/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
+#define X86_CPUID_STEXT_FEATURE_EBX_SGX               RT_BIT_32(2)
 /** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
 #define X86_CPUID_STEXT_FEATURE_EBX_BMI1              RT_BIT_32(3)
@@ -553 +555 @@
 /** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
 #define X86_CPUID_STEXT_FEATURE_EBX_AVX2              RT_BIT_32(5)
+/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
+#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY   RT_BIT_32(6)
 /** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
 #define X86_CPUID_STEXT_FEATURE_EBX_SMEP              RT_BIT_32(7)

trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

@@ -2970 +2970 @@
                                //| X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE          RT_BIT(0)
                                //| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST        RT_BIT(1)
-                               //| RT_BIT(2) - reserved
+                               //| X86_CPUID_STEXT_FEATURE_EBX_SGX               RT_BIT(2)
                                //| X86_CPUID_STEXT_FEATURE_EBX_BMI1              RT_BIT(3)
                                //| X86_CPUID_STEXT_FEATURE_EBX_HLE               RT_BIT(4)
                                | (pConfig->enmAvx2 ? X86_CPUID_STEXT_FEATURE_EBX_AVX2 : 0)
-                               //| RT_BIT(6) - reserved
+                               | X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
                                //| X86_CPUID_STEXT_FEATURE_EBX_SMEP              RT_BIT(7)
                                //| X86_CPUID_STEXT_FEATURE_EBX_BMI2              RT_BIT(8)
@@ -3009 +3009 @@
                 {
                     PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEbx, FSGSBASE,   X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE);
+                    PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEbx, SGX,        X86_CPUID_STEXT_FEATURE_EBX_SGX);
                     PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2,       X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
                     PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEbx, SMEP,       X86_CPUID_STEXT_FEATURE_EBX_SMEP);
@@ -5349 +5350 @@
 static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
 {
-    DBGFREGSUBFIELD_RO("FSGSBASE\0"     "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.",    0, 1, 0),
-    DBGFREGSUBFIELD_RO("TSCADJUST\0"    "Supports MSR_IA32_TSC_ADJUST",                  1, 1, 0),
-    DBGFREGSUBFIELD_RO("BMI1\0"         "Advanced Bit Manipulation extension 1",         3, 1, 0),
-    DBGFREGSUBFIELD_RO("HLE\0"          "Hardware Lock Elision",                         4, 1, 0),
-    DBGFREGSUBFIELD_RO("AVX2\0"         "Advanced Vector Extensions 2",                  5, 1, 0),
-    DBGFREGSUBFIELD_RO("SMEP\0"         "Supervisor Mode Execution Prevention",          7, 1, 0),
-    DBGFREGSUBFIELD_RO("BMI2\0"         "Advanced Bit Manipulation extension 2",         8, 1, 0),
-    DBGFREGSUBFIELD_RO("ERMS\0"         "Enhanced REP MOVSB/STOSB instructions",         9, 1, 0),
-    DBGFREGSUBFIELD_RO("INVPCID\0"      "INVPCID instruction",                          10, 1, 0),
-    DBGFREGSUBFIELD_RO("RTM\0"          "Restricted Transactional Memory",              11, 1, 0),
-    DBGFREGSUBFIELD_RO("PQM\0"          "Platform Quality of Service Monitoring",       12, 1, 0),
-    DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set",      13, 1, 0),
-    DBGFREGSUBFIELD_RO("MPE\0"          "Intel Memory Protection Extensions",           14, 1, 0),
-    DBGFREGSUBFIELD_RO("PQE\0"          "Platform Quality of Service Enforcement",      15, 1, 0),
-    DBGFREGSUBFIELD_RO("AVX512F\0"      "AVX512 Foundation instructions",               16, 1, 0),
-    DBGFREGSUBFIELD_RO("RDSEED\0"       "RDSEED instruction",                           18, 1, 0),
-    DBGFREGSUBFIELD_RO("ADX\0"          "ADCX/ADOX instructions",                       19, 1, 0),
-    DBGFREGSUBFIELD_RO("SMAP\0"         "Supervisor Mode Access Prevention",            20, 1, 0),
-    DBGFREGSUBFIELD_RO("CLFLUSHOPT\0"   "CLFLUSHOPT (Cache Line Flush) instruction",    23, 1, 0),
-    DBGFREGSUBFIELD_RO("INTEL_PT\0"     "Intel Processor Trace",                        25, 1, 0),
-    DBGFREGSUBFIELD_RO("AVX512PF\0"     "AVX512 Prefetch instructions",                 26, 1, 0),
-    DBGFREGSUBFIELD_RO("AVX512ER\0"     "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
-    DBGFREGSUBFIELD_RO("AVX512CD\0"     "AVX512 Conflict Detection instructions",       28, 1, 0),
-    DBGFREGSUBFIELD_RO("SHA\0"          "Secure Hash Algorithm extensions",             29, 1, 0),
+    DBGFREGSUBFIELD_RO("FSGSBASE\0"         "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.",    0, 1, 0),
+    DBGFREGSUBFIELD_RO("TSCADJUST\0"        "Supports MSR_IA32_TSC_ADJUST",                  1, 1, 0),
+    DBGFREGSUBFIELD_RO("SGX\0"              "Supports Software Guard Extensions",            2, 1, 0),
+    DBGFREGSUBFIELD_RO("BMI1\0"             "Advanced Bit Manipulation extension 1",         3, 1, 0),
+    DBGFREGSUBFIELD_RO("HLE\0"              "Hardware Lock Elision",                         4, 1, 0),
+    DBGFREGSUBFIELD_RO("AVX2\0"             "Advanced Vector Extensions 2",                  5, 1, 0),
+    DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0"  "FPU DP only updated on exceptions",             6, 1, 0),
+    DBGFREGSUBFIELD_RO("SMEP\0"             "Supervisor Mode Execution Prevention",          7, 1, 0),
+    DBGFREGSUBFIELD_RO("BMI2\0"             "Advanced Bit Manipulation extension 2",         8, 1, 0),
+    DBGFREGSUBFIELD_RO("ERMS\0"             "Enhanced REP MOVSB/STOSB instructions",         9, 1, 0),
+    DBGFREGSUBFIELD_RO("INVPCID\0"          "INVPCID instruction",                          10, 1, 0),
+    DBGFREGSUBFIELD_RO("RTM\0"              "Restricted Transactional Memory",              11, 1, 0),
+    DBGFREGSUBFIELD_RO("PQM\0"              "Platform Quality of Service Monitoring",       12, 1, 0),
+    DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0"     "Deprecates FPU CS, FPU DS values if set",      13, 1, 0),
+    DBGFREGSUBFIELD_RO("MPE\0"              "Intel Memory Protection Extensions",           14, 1, 0),
+    DBGFREGSUBFIELD_RO("PQE\0"              "Platform Quality of Service Enforcement",      15, 1, 0),
+    DBGFREGSUBFIELD_RO("AVX512F\0"          "AVX512 Foundation instructions",               16, 1, 0),
+    DBGFREGSUBFIELD_RO("RDSEED\0"           "RDSEED instruction",                           18, 1, 0),
+    DBGFREGSUBFIELD_RO("ADX\0"              "ADCX/ADOX instructions",                       19, 1, 0),
+    DBGFREGSUBFIELD_RO("SMAP\0"             "Supervisor Mode Access Prevention",            20, 1, 0),
+    DBGFREGSUBFIELD_RO("CLFLUSHOPT\0"       "CLFLUSHOPT (Cache Line Flush) instruction",    23, 1, 0),
+    DBGFREGSUBFIELD_RO("INTEL_PT\0"         "Intel Processor Trace",                        25, 1, 0),
+    DBGFREGSUBFIELD_RO("AVX512PF\0"         "AVX512 Prefetch instructions",                 26, 1, 0),
+    DBGFREGSUBFIELD_RO("AVX512ER\0"         "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
+    DBGFREGSUBFIELD_RO("AVX512CD\0"         "AVX512 Conflict Detection instructions",       28, 1, 0),
+    DBGFREGSUBFIELD_RO("SHA\0"              "Secure Hash Algorithm extensions",             29, 1, 0),
     DBGFREGSUBFIELD_TERMINATOR()
 };