Index: trunk/src/VBox/VMM/VMMAll/APICAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 61077)
+++ trunk/src/VBox/VMM/VMMAll/APICAll.cpp	(revision 61078)
@@ -543,5 +543,5 @@
     VMCPU_ASSERT_EMT(pVCpu);
 
-    uint32_t   uValidMask = XAPIC_SVR;
+    uint32_t   uValidMask = XAPIC_SVR_VALID;
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     if (pXApicPage->version.u.fEoiBroadcastSupression)
@@ -1030,5 +1030,5 @@
 
     PXAPICPAGE pXApicPage  = VMCPU_TO_XAPICPAGE(pVCpu);
-    pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR;
+    pXApicPage->icr_lo.all.u32IcrLo = uIcrLo & XAPIC_ICR_LO_WR_VALID;
     Log2(("APIC%u: apicSetIcrLo: uIcrLo=%#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
 
@@ -1053,5 +1053,5 @@
     /* Validate. */
     uint32_t const uLo = RT_LO_U32(u64Icr);
-    if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR)))
+    if (RT_LIKELY(!(uLo & ~XAPIC_ICR_LO_WR_VALID)))
     {
         /* Update high dword first, then update the low dword which sends the IPI. */
@@ -1078,5 +1078,5 @@
 
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
-        && (uEsr & ~XAPIC_ESR_WO))
+        && (uEsr & ~XAPIC_ESR_WO_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_ESR, APICMSRACCESS_WRITE_RSVD_BITS);
 
@@ -1151,5 +1151,5 @@
 
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
-        && (uTpr & ~XAPIC_TPR))
+        && (uTpr & ~XAPIC_TPR_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TPR, APICMSRACCESS_WRITE_RSVD_BITS);
 
@@ -1177,5 +1177,5 @@
 
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
-        && (uEoi & ~XAPIC_EOI_WO))
+        && (uEoi & ~XAPIC_EOI_WO_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_EOI, APICMSRACCESS_WRITE_RSVD_BITS);
 
@@ -1222,5 +1222,5 @@
 
     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
-    apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR);
+    apicWriteRaw32(pXApicPage, XAPIC_OFF_LDR, uLdr & XAPIC_LDR_VALID);
     return VINF_SUCCESS;
 }
@@ -1241,5 +1241,5 @@
     Assert(!XAPIC_IN_X2APIC_MODE(pVCpu));
 
-    uDfr &= XAPIC_DFR;
+    uDfr &= XAPIC_DFR_VALID;
     uDfr |= XAPIC_DFR_RSVD_MB1;
 
@@ -1263,5 +1263,5 @@
     VMCPU_ASSERT_EMT(pVCpu);
     if (   XAPIC_IN_X2APIC_MODE(pVCpu)
-        && (uTimerDcr & ~XAPIC_TIMER_DCR))
+        && (uTimerDcr & ~XAPIC_TIMER_DCR_VALID))
         return apicMsrAccessError(pVCpu, MSR_IA32_X2APIC_TIMER_DCR, APICMSRACCESS_WRITE_RSVD_BITS);
 
Index: trunk/src/VBox/VMM/VMMR3/APIC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 61077)
+++ trunk/src/VBox/VMM/VMMR3/APIC.cpp	(revision 61078)
@@ -871,5 +871,5 @@
     uint32_t u32Tpr;
     SSMR3GetU32(pSSM, &u32Tpr);
-    pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR;
+    pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
 
     SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
Index: trunk/src/VBox/VMM/include/APICInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/APICInternal.h	(revision 61077)
+++ trunk/src/VBox/VMM/include/APICInternal.h	(revision 61078)
@@ -104,8 +104,8 @@
 #define XAPIC_ESR_ILLEGAL_REG_ADDRESS        RT_BIT(7)
 /** ESR - Valid write-only bits. */
-#define XAPIC_ESR_WO                         UINT32_C(0x0)
+#define XAPIC_ESR_WO_VALID                   UINT32_C(0x0)
 
 /** TPR - Valid bits. */
-#define XAPIC_TPR                            UINT32_C(0xff)
+#define XAPIC_TPR_VALID                      UINT32_C(0xff)
 /** TPR - Task-priority class. */
 #define XAPIC_TPR_TP                         UINT32_C(0xf0)
@@ -118,5 +118,5 @@
 
 /** PPR - Valid bits. */
-#define XAPIC_PPR                            UINT32_C(0xff)
+#define XAPIC_PPR_VALID                      UINT32_C(0xff)
 /** PPR - Processor-priority class. */
 #define XAPIC_PPR_PP                         UINT32_C(0xf0)
@@ -164,18 +164,18 @@
 #define XAPIC_LVT_INTR_INPUT_PIN_POLARITY    RT_BIT(13)
 /** LVT - Valid bits common to all LVTs. */
-#define XAPIC_LVT_COMMON                     (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
+#define XAPIC_LVT_COMMON_VALID               (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
 /** LVT CMCI - Valid bits. */
-#define XAPIC_LVT_CMCI_VALID                 (XAPIC_LVT_COMMON | XAPIC_LVT_DELIVERY_MODE)
+#define XAPIC_LVT_CMCI_VALID                 (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
 /** LVT Timer - Valid bits. */
-#define XAPIC_LVT_TIMER_VALID                (XAPIC_LVT_COMMON | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
+#define XAPIC_LVT_TIMER_VALID                (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
 /** LVT Thermal - Valid bits. */
-#define XAPIC_LVT_THERMAL_VALID              (XAPIC_LVT_COMMON | XAPIC_LVT_DELIVERY_MODE)
+#define XAPIC_LVT_THERMAL_VALID              (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
 /** LVT Perf - Valid bits. */
-#define XAPIC_LVT_PERF_VALID                 (XAPIC_LVT_COMMON | XAPIC_LVT_DELIVERY_MODE)
+#define XAPIC_LVT_PERF_VALID                 (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
 /** LVT LINTx - Valid bits. */
-#define XAPIC_LVT_LINT_VALID                 (  XAPIC_LVT_COMMON | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
+#define XAPIC_LVT_LINT_VALID                 (  XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
                                               | XAPIC_LVT_INTR_INPUT_PIN_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)
 /** LVT Error - Valid bits. */
-#define XAPIC_LVT_ERROR_VALID                (XAPIC_LVT_COMMON)
+#define XAPIC_LVT_ERROR_VALID                (XAPIC_LVT_COMMON_VALID)
 
 /** SVR - The vector. */
@@ -187,5 +187,5 @@
 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
 /** SVR - Valid bits. */
-# define XAPIC_SVR                           (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
+# define XAPIC_SVR_VALID                     (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
 #else
 # error "Implement Pentium and P6 family APIC architectures"
@@ -193,5 +193,5 @@
 
 /** DFR - Valid bits. */
-#define XAPIC_DFR                            UINT32_C(0xf0000000)
+#define XAPIC_DFR_VALID                      UINT32_C(0xf0000000)
 /** DFR - Reserved bits that must always remain set. */
 #define XAPIC_DFR_RSVD_MB1                   UINT32_C(0x0fffffff)
@@ -202,5 +202,5 @@
 
 /** LDR - Valid bits. */
-#define XAPIC_LDR                            UINT32_C(0xff000000)
+#define XAPIC_LDR_VALID                      UINT32_C(0xff000000)
 /** LDR - Cluster ID mask (x2APIC). */
 #define X2APIC_LDR_CLUSTER_ID                UINT32_C(0xffff0000)
@@ -221,12 +221,12 @@
 
 /** EOI - Valid write-only bits. */
-#define XAPIC_EOI_WO                         UINT32_C(0x0)
+#define XAPIC_EOI_WO_VALID                   UINT32_C(0x0)
 /** Timer ICR - Valid bits. */
-#define XAPIC_TIMER_ICR                      UINT32_C(0xffffffff)
+#define XAPIC_TIMER_ICR_VALID                UINT32_C(0xffffffff)
 /** Timer DCR - Valid bits. */
-#define XAPIC_TIMER_DCR                      (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
+#define XAPIC_TIMER_DCR_VALID                (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
 
 /** Self IPI - Valid bits. */
-#define XAPIC_SELF_IPI                       UINT32_C(0xff)
+#define XAPIC_SELF_IPI_VALID                 UINT32_C(0xff)
 /** Self IPI - The vector. */
 #define XAPIC_SELF_IPI_VECTOR                UINT32_C(0xff)
@@ -251,5 +251,5 @@
 #define XAPIC_ICR_LO_DEST_SHORTHAND          (RT_BIT(18) | RT_BIT(19))
 /** ICR Low - Valid write bits. */
-#define XAPIC_ICR_LO_WR                      (  XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
+#define XAPIC_ICR_LO_WR_VALID                (  XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
                                               | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)
 
@@ -259,5 +259,5 @@
 #define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi)    (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)
 /** ICR High - Valid write bits in xAPIC mode. */
-#define XAPIC_ICR_HI_WR                      XAPIC_ICR_HI_DEST
+#define XAPIC_ICR_HI_WR_VALID                XAPIC_ICR_HI_DEST
 
 /** APIC ID broadcast mask - x2APIC mode. */
