VirtualBox

Changeset 61538 in vbox for trunk/src/VBox


Ignore:
Timestamp:
Jun 7, 2016 1:16:06 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
107875
Message:

end of meeting

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/Makefile.kmk

    r61535 r61538  
    271271
    272272# CPU instruction decoding experiments.
    273 #MISCBINS += bs3-cpu-decode-1
    274 bs3-cpu-decode-1_TEMPLATE = VBoxBS3KitImg
    275 bs3-cpu-decode-1_INCS  = .
    276 bs3-cpu-decode-1_DEFS  =  BS3_CMN_INSTANTIATE_FILE1=bs3-cpu-decode-1-template.c
    277 bs3-cpu-decode-1_DEFS += BS3_MODE_INSTANTIATE_FILE1=bs3-cpu-decode-1-template.c
    278 bs3-cpu-decode-1_SOURCES = \
    279         bs3kit/bs3-first-rm.asm \
    280         bs3-cpu-decode-1.c32 \
    281        bs3kit/bs3-cmn-instantiate.c16 \
    282        bs3kit/bs3-cmn-instantiate.c32 \
    283        bs3kit/bs3-cmn-instantiate.c64 \
    284         bs3-cpu-decode-1-asm.asm
    285 bs3-cpu-decode-1-template.o:: \
    286         $$(bs3-cpu-decode-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o16 \
    287         $$(bs3-cpu-decode-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o32 \
    288         $$(bs3-cpu-decode-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o64 \
    289         $$(bs3-cpu-decode-1_0_OUTDIR)/bs3-cpu-decode-1-asm.o16
     273MISCBINS += bs3-cpu-decoding-1
     274bs3-cpu-decoding-1_TEMPLATE = VBoxBS3KitImg
     275bs3-cpu-decoding-1_INCS  = .
     276bs3-cpu-decoding-1_DEFS  =  BS3_CMN_INSTANTIATE_FILE1=bs3-cpu-decoding-1-template.c
     277bs3-cpu-decoding-1_DEFS += BS3_MODE_INSTANTIATE_FILE1=bs3-cpu-decoding-1-template.c
     278bs3-cpu-decoding-1_SOURCES = \
     279        bs3kit/bs3-first-init-all-pe32.asm \
     280        bs3-cpu-decoding-1.c32 \
     281        bs3-cpu-decoding-1-asm.asm
     282#       bs3kit/bs3-cmn-instantiate.c16 \
     283#       bs3kit/bs3-cmn-instantiate.c32 \
     284#       bs3kit/bs3-cmn-instantiate.c64
     285#bs3-cpu-decoding-1-template.o:: \
     286#       $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o16 \
     287#       $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o32 \
     288#       $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3kit/bs3-cmn-instantiate.o64 \
     289#       $$(bs3-cpu-decoding-1_0_OUTDIR)/bs3-cpu-decoding-1-asm.o16
    290290
    291291endif # VBOX_WITH_BS3KIT

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1-asm.asm

    r61535 r61538  
    11; $Id$
    22;; @file
    3 ; BS3Kit - bs3-fpustate-1, assembly helpers and template instantiation.
     3; BS3Kit - bs3-cpu-decoding-1, assembly helpers and template instantiation.
    44;
    55
    … …  
    3232
    3333
    34 ;*********************************************************************************************************************************
    35 ;*  Global Variables                                                                                                             *
    36 ;*********************************************************************************************************************************
    37 BS3_BEGIN_DATA16
    38 ;; @name Floating point constants.
    39 ; @{
    40 g_r32_0dot1:    dd 0.1
    41 g_r32_3dot2:    dd 3.2
    42 g_r32_Zero:     dd 0.0
    43 g_r32_One:      dd 1.0
    44 g_r32_Two:      dd 2.0
    45 g_r32_Three:    dd 3.0
    46 g_r32_Ten:      dd 10.0
    47 g_r32_Eleven:   dd 11.0
    48 g_r32_ThirtyTwo:dd 32.0
    49 g_r32_Min:      dd 000800000h
    50 g_r32_Max:      dd 07f7fffffh
    51 g_r32_Inf:      dd 07f800000h
    52 g_r32_SNaN:     dd 07f800001h
    53 g_r32_SNaNMax:  dd 07fbfffffh
    54 g_r32_QNaN:     dd 07fc00000h
    55 g_r32_QNaNMax:  dd 07fffffffh
    56 g_r32_NegQNaN:  dd 0ffc00000h
    57 
    58 g_r64_0dot1:    dq 0.1
    59 g_r64_6dot9:    dq 6.9
    60 g_r64_Zero:     dq 0.0
    61 g_r64_One:      dq 1.0
    62 g_r64_Two:      dq 2.0
    63 g_r64_Three:    dq 3.0
    64 g_r64_Ten:      dq 10.0
    65 g_r64_Eleven:   dq 11.0
    66 g_r64_ThirtyTwo:dq 32.0
    67 g_r64_Min:      dq 00010000000000000h
    68 g_r64_Max:      dq 07fefffffffffffffh
    69 g_r64_Inf:      dq 07ff0000000000000h
    70 g_r64_SNaN:     dq 07ff0000000000001h
    71 g_r64_SNaNMax:  dq 07ff7ffffffffffffh
    72 g_r64_NegQNaN:  dq 0fff8000000000000h
    73 g_r64_QNaN:     dq 07ff8000000000000h
    74 g_r64_QNaNMax:  dq 07fffffffffffffffh
    75 g_r64_DnMin:    dq 00000000000000001h
    76 g_r64_DnMax:    dq 0000fffffffffffffh
    77 
    78 
    79 g_r80_0dot1:    dt 0.1
    80 g_r80_3dot2:    dt 3.2
    81 g_r80_Zero:     dt 0.0
    82 g_r80_One:      dt 1.0
    83 g_r80_Two:      dt 2.0
    84 g_r80_Three:    dt 3.0
    85 g_r80_Ten:      dt 10.0
    86 g_r80_Eleven:   dt 11.0
    87 g_r80_ThirtyTwo:dt 32.0
    88 %ifdef __NASM__
    89 g_r80_Min:      dq 08000000000000000h
    90                 dw 00001h
    91 g_r80_Max:      dq     0ffffffffffffffffh
    92                 dw 07ffeh
    93 g_r80_Inf:      dq     08000000000000000h
    94                 dw 07fffh
    95 g_r80_QNaN:     dq     0c000000000000000h
    96                 dw 07fffh
    97 g_r80_QNaNMax:  dq     0ffffffffffffffffh
    98                 dw 07fffh
    99 g_r80_NegQNaN:  dq     0c000000000000000h
    100                 dw 0ffffh
    101 g_r80_SNaN:     dq     08000000000000001h
    102                 dw 07fffh
    103 g_r80_SNaNMax:  dq     0bfffffffffffffffh
    104                 dw 07fffh
    105 g_r80_DnMin:    dq     00000000000000001h
    106                 dw 00000h
    107 g_r80_DnMax:    dq     07fffffffffffffffh
    108                 dw 00000h
    109 %else
    110 g_r80_Min:      dt 000018000000000000000h
    111 g_r80_Max:      dt 07ffeffffffffffffffffh
    112 g_r80_Inf:      dt 07fff8000000000000000h
    113 g_r80_QNaN:     dt 07fffc000000000000000h
    114 g_r80_QNaNMax:  dt 07fffffffffffffffffffh
    115 g_r80_NegQNaN:  dt 0ffffc000000000000000h
    116 g_r80_SNaN:     dt 07fff8000000000000001h
    117 g_r80_SNaNMax:  dt 07fffbfffffffffffffffh
    118 g_r80_DnMin:    dt 000000000000000000001h
    119 g_r80_DnMax:    dt 000007fffffffffffffffh
    120 %endif
    121 
    122 g_r32V1:        dd 3.2
    123 g_r32V2:        dd -1.9
    124 g_r64V1:        dq 6.4
    125 g_r80V1:        dt 8.0
    126 
    127 ; Denormal numbers.
    128 g_r32D0:        dd 000200000h
    129 ;; @}
    130 
    131 ;; @name Upconverted Floating point constants
    132 ; @{
    133 ;g_r80_r32_0dot1:        dt 0.1
    134 %ifdef __NASM__
    135 g_r80_r32_3dot2:        dq     0cccccd0000000000h
    136                         dw 04000h
    137 %else
    138 g_r80_r32_3dot2:        dt 04000cccccd0000000000h
    139 %endif
    140 ;g_r80_r32_Zero:         dt 0.0
    141 ;g_r80_r32_One:          dt 1.0
    142 ;g_r80_r32_Two:          dt 2.0
    143 ;g_r80_r32_Three:        dt 3.0
    144 ;g_r80_r32_Ten:          dt 10.0
    145 ;g_r80_r32_Eleven:       dt 11.0
    146 ;g_r80_r32_ThirtyTwo:    dt 32.0
    147 ;; @}
    148 
    149 ;; @name Decimal constants.
    150 ; @{
    151 g_u64Zero:      dd 0
    152 g_u32Zero:      dw 0
    153 g_u64Two:       dd 2
    154 g_u32Two:       dw 2
    155 ;; @}
    156 
    157 
    15834;
    15935; Instantiate code templates.
    16036;
    161 BS3_INSTANTIATE_TEMPLATE_ESSENTIALS      "bs3-fpustate-1-template.mac"
     37BS3_INSTANTIATE_TEMPLATE_ESSENTIALS      "bs3-cpu-decoding-1-template.mac"
    16238

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1-template.c

    r61535 r61538  
    11/* $Id$ */
    22/** @file
    3  * BS3Kit - bs3-fpustate-1, C code template.
     3 * BS3Kit - bs3-cpu-decoding-1, C code template.
    44 */
    55
    … …  
    3838*********************************************************************************************************************************/
    3939
    40 
     40/*
     41 * Common code.
     42 * Common code.
     43 * Common code.
     44 */
    4145#ifdef BS3_INSTANTIATING_CMN
    42 
    43 /**
    44  * Displays the differences between the two states.
    45  */
    46 # define bs3FpuState1_Diff BS3_CMN_NM(bs3FpuState1_Diff)
    47 BS3_DECL_NEAR(void) bs3FpuState1_Diff(X86FXSTATE const BS3_FAR *pExpected, X86FXSTATE const BS3_FAR *pChecking)
    48 {
    49     unsigned i;
    50 
    51 # define CHECK(a_Member, a_Fmt) \
    52         if (pExpected->a_Member != pChecking->a_Member) \
    53             Bs3TestPrintf("  " #a_Member ": " a_Fmt ", expected " a_Fmt "\n", pChecking->a_Member, pExpected->a_Member); \
    54         else do { } while (0)
    55     CHECK(FCW,          "%#RX16");
    56     CHECK(FSW,          "%#RX16");
    57     CHECK(FTW,          "%#RX16");
    58     CHECK(FOP,          "%#RX16");
    59     CHECK(FPUIP,        "%#RX32");
    60     CHECK(CS,           "%#RX16");
    61     CHECK(Rsrvd1,       "%#RX16");
    62     CHECK(FPUDP,        "%#RX32");
    63     CHECK(DS,           "%#RX16");
    64     CHECK(Rsrvd2,       "%#RX16");
    65     CHECK(MXCSR,        "%#RX32");
    66     CHECK(MXCSR_MASK,   "%#RX32");
    67 # undef CHECK
    68     for (i = 0; i < RT_ELEMENTS(pExpected->aRegs); i++)
    69         if (   pChecking->aRegs[i].au64[0] != pExpected->aRegs[i].au64[0]
    70             || pChecking->aRegs[i].au64[1] != pExpected->aRegs[i].au64[1])
    71             Bs3TestPrintf("st%u: %.16Rhxs\n"
    72                           "exp: %.16Rhxs\n",
    73                           i, &pChecking->aRegs[i], &pExpected->aRegs[i]);
    74     for (i = 0; i < RT_ELEMENTS(pExpected->aXMM); i++)
    75         if (   pChecking->aXMM[i].au64[0] != pExpected->aXMM[i].au64[0]
    76             || pChecking->aXMM[i].au64[1] != pExpected->aXMM[i].au64[1])
    77             Bs3TestPrintf("xmm%u: %.16Rhxs\n"
    78                           " %sexp: %.16Rhxs\n",
    79                           i, &pChecking->aRegs[i], &pExpected->aRegs[i], i >= 10 ? " " : "");
    80 }
    81 
    8246
    8347#endif /* BS3_INSTANTIATING_CMN */
    … …  
    9054 */
    9155#ifdef BS3_INSTANTIATING_MODE
    92 # if TMPL_MODE == BS3_MODE_PE32 \
    93   || TMPL_MODE == BS3_MODE_PP32 \
    94   || TMPL_MODE == BS3_MODE_PAE32 \
    95   || TMPL_MODE == BS3_MODE_LM64 \
    96   || TMPL_MODE == BS3_MODE_RM
    9756
    98 /* Assembly helpers: */
    99 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_InitState)(X86FXSTATE BS3_FAR *pFxState, void BS3_FAR *pvMmioReg);
    100 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Restore)(X86FXSTATE const BS3_FAR *pFxState);
    101 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Save)(X86FXSTATE BS3_FAR *pFxState);
    102 
    103 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FNStEnv)(void BS3_FAR *pvMmioReg);
    104 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Read)(void BS3_FAR *pvMmioReg);
    105 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Write)(void BS3_FAR *pvMmioReg);
    106 BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FMul)(void BS3_FAR *pvMmioReg);
    107 
    108 
    109 /**
    110  * Tests for FPU state corruption.
    111  *
    112  * First we don't do anything to quit guest context for a while.
    113  * Then we start testing weird MMIO accesses, some which amonger other things
    114  * forces the use of the FPU state or host FPU to do the emulation.  Both are a
    115  * little complicated in raw-mode and ring-0 contexts.
    116  *
    117  * We ASSUME FXSAVE/FXRSTOR support here.
    118  */
    119 BS3_DECL_FAR(uint8_t) TMPL_NM(bs3FpuState1_Corruption)(uint8_t bMode)
    120 {
    121     /* We don't need to test that many modes, probably.  */
    122 
    123     uint8_t             abBuf[sizeof(X86FXSTATE)*2 + 32];
    124     uint8_t BS3_FAR    *pbTmp = &abBuf[0x10 - (((uintptr_t)abBuf) & 0x0f)];
    125     X86FXSTATE BS3_FAR *pExpected = (X86FXSTATE BS3_FAR *)pbTmp;
    126     X86FXSTATE BS3_FAR *pChecking = pExpected + 1;
    127     uint32_t            iLoop;
    128     uint32_t            uStartTick;
    129     bool                fMmioReadback;
    130     bool                fReadBackError = false;
    131     BS3PTRUNION         MmioReg;
    132 
    133 
    134 # undef  CHECK_STATE
    135 # define CHECK_STATE(a_Instr) \
    136         do { \
    137             TMPL_NM(bs3FpuState1_Save)(pChecking); \
    138             if (Bs3MemCmp(pExpected, pChecking, sizeof(*pExpected)) != 0) \
    139             { \
    140                 Bs3TestFailedF("State differs after " #a_Instr " (write) in loop #%RU32\n", iLoop); \
    141                 bs3FpuState1_Diff(pExpected, pChecking); \
    142                 Bs3PitDisable(); \
    143                 return 1; \
    144             } \
    145         } while (0)
    146 
    147     /*
    148      * Setup the test.
    149      */
    150 
    151     /* Make this code executable in raw-mode.  A bit tricky. */
    152     ASMSetCR0(ASMGetCR0() | X86_CR0_WP);
    153     Bs3PitSetupAndEnablePeriodTimer(20);
    154     ASMIntEnable();
    155 # if ARCH_BITS != 64
    156     ASMHalt();
    157 # endif
    158 
    159     /* Figure out which MMIO region we'll be using so we can correctly initialize FPUDS. */
    160 # if BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
    161     MmioReg.pv = BS3_FP_MAKE(0xffff, VMMDEV_TESTING_MMIO_BASE - _1M + 16);
    162 # elif BS3_MODE_IS_16BIT_CODE(TMPL_MODE)
    163     MmioReg.pv = BS3_FP_MAKE(BS3_SEL_VMMDEV_MMIO16, VMMDEV_TESTING_MMIO_BASE - _1M);
    164 # else
    165     MmioReg.pv = (uint8_t *)VMMDEV_TESTING_MMIO_BASE;
    166 # endif
    167     if (MmioReg.pu32[VMMDEV_TESTING_MMIO_OFF_NOP / sizeof(uint32_t)] == VMMDEV_TESTING_NOP_RET)
    168     {
    169         fMmioReadback = true;
    170         MmioReg.pb += VMMDEV_TESTING_MMIO_OFF_READBACK;
    171     }
    172     else
    173     {
    174         Bs3TestPrintf("VMMDev MMIO not found, using VGA instead\n");
    175         fMmioReadback = false;
    176         MmioReg.pv = Bs3XptrFlatToCurrent(0xa7800);
    177     }
    178 
    179     /* Make 100% sure we don't trap accessing the FPU state and that we can use fxsave/fxrstor. */
    180     g_usBs3TestStep = 1;
    181     ASMSetCR0((ASMGetCR0() & ~(X86_CR0_TS | X86_CR0_EM)) | X86_CR0_MP);
    182     ASMSetCR4(ASMGetCR4() | X86_CR4_OSFXSR /*| X86_CR4_OSXMMEEXCPT*/);
    183 
    184     /* Come up with a distinct state. We do that from assembly (will do FPU in R0/RC). */
    185     g_usBs3TestStep = 2;
    186     Bs3MemSet(abBuf, 0x42, sizeof(abBuf));
    187     TMPL_NM(bs3FpuState1_InitState)(pExpected, MmioReg.pb);
    188 
    189 
    190     /*
    191      * Test #1: Check that we can keep it consistent for a while.
    192      */
    193     g_usBs3TestStep = 3;
    194     uStartTick = g_cBs3PitTicks;
    195     for (iLoop = 0; iLoop < _16M; iLoop++)
    196     {
    197         CHECK_STATE(nop);
    198         if (   (iLoop & 0xffff) == 0xffff
    199             && g_cBs3PitTicks - uStartTick >= 20 * 20) /* 20 seconds*/
    200             break;
    201     }
    202 
    203     /*
    204      * Test #2: Use various FPU, SSE and weird instructions to do MMIO writes.
    205      *
    206      * We'll use the VMMDev readback register if possible, but make do
    207      * with VGA if not configured.
    208      */
    209     g_usBs3TestStep = 4;
    210     uStartTick = g_cBs3PitTicks;
    211     for (iLoop = 0; iLoop < _1M; iLoop++)
    212     {
    213         unsigned off;
    214         uint8_t  abCompare[64];
    215         uint8_t  abReadback[64];
    216 
    217         /* Macros  */
    218 # undef  CHECK_READBACK_WRITE_RUN
    219 # define CHECK_READBACK_WRITE_RUN(a_Instr, a_Worker, a_Type) \
    220             do { \
    221                 off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
    222                 if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
    223                     off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
    224                 a_Worker((a_Type *)&MmioReg.pb[off]); \
    225                 if (fMmioReadback && (!fReadBackError || iLoop == 0)) \
    226                 { \
    227                     a_Worker((a_Type *)&abCompare[0]); \
    228                     Bs3MemCpy(abReadback, &MmioReg.pb[off], sizeof(a_Type)); \
    229                     if (Bs3MemCmp(abReadback, abCompare, sizeof(a_Type)) != 0) \
    230                     { \
    231                         Bs3TestFailedF("Read back error for " #a_Instr " in loop #%RU32:\n%.*Rhxs expected:\n%.*Rhxs\n", \
    232                                        iLoop, sizeof(a_Type), abReadback, sizeof(a_Type), abCompare); \
    233                         fReadBackError = true; \
    234                     } \
    235                 } \
    236             } while (0)
    237 
    238 # undef  CHECK_READBACK_WRITE
    239 # define CHECK_READBACK_WRITE(a_Instr, a_Worker, a_Type) \
    240             CHECK_READBACK_WRITE_RUN(a_Instr, a_Worker, a_Type); \
    241             CHECK_STATE(a_Instr)
    242 # undef  CHECK_READBACK_WRITE_Z
    243 # define CHECK_READBACK_WRITE_Z(a_Instr, a_Worker, a_Type) \
    244             do { \
    245                 if (fMmioReadback && (!fReadBackError || iLoop == 0)) \
    246                 { \
    247                     Bs3MemZero(&abCompare[0], sizeof(a_Type)); \
    248                     off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
    249                     if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
    250                         off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
    251                     Bs3MemZero(&MmioReg.pb[off], sizeof(a_Type)); \
    252                 } \
    253                 CHECK_READBACK_WRITE(a_Instr, a_Worker, a_Type); \
    254             } while (0)
    255 
    256 # undef  CHECK_READBACK_READ_RUN
    257 # define CHECK_READBACK_READ_RUN(a_Instr, a_Worker, a_Type) \
    258             do { \
    259                 off = (unsigned)(iLoop & (VMMDEV_TESTING_READBACK_SIZE / 2 - 1)); \
    260                 if (off + sizeof(a_Type) > VMMDEV_TESTING_READBACK_SIZE) \
    261                     off = VMMDEV_TESTING_READBACK_SIZE - sizeof(a_Type); \
    262                 a_Worker((a_Type *)&MmioReg.pb[off]); \
    263                 TMPL_NM(bs3FpuState1_Save)(pChecking); \
    264             } while (0)
    265 # undef  CHECK_READBACK_READ
    266 # define CHECK_READBACK_READ(a_Instr, a_Worker, a_Type) \
    267             CHECK_READBACK_READ_RUN(a_Instr, a_Worker, a_Type); \
    268             CHECK_STATE(a_Instr)
    269 
    270 
    271         /* The tests. */
    272         CHECK_READBACK_WRITE_Z(SIDT,     ASMGetIDTR,                         RTIDTR);
    273         CHECK_READBACK_WRITE_Z(FNSTENV,  TMPL_NM(bs3FpuState1_FNStEnv),      X86FSTENV32P); /** @todo x86.h is missing types */
    274         CHECK_READBACK_WRITE(  MOVDQU,   TMPL_NM(bs3FpuState1_MovDQU_Write), X86XMMREG);
    275         CHECK_READBACK_READ(   MOVDQU,   TMPL_NM(bs3FpuState1_MovDQU_Read),  X86XMMREG);
    276 
    277         /* Using the FPU is a little complicated, but we really need to check these things. */
    278         CHECK_READBACK_READ_RUN(FMUL,    TMPL_NM(bs3FpuState1_FMul),         uint64_t);
    279         pExpected->FOP    = 0x7dc;
    280 # if ARCH_BITS == 64
    281         pExpected->FPUDP  = (uint32_t) (uintptr_t)&MmioReg.pb[off];
    282         pExpected->DS     = (uint16_t)((uintptr_t)&MmioReg.pb[off] >> 32);
    283         pExpected->Rsrvd2 = (uint16_t)((uintptr_t)&MmioReg.pb[off] >> 48);
    284 # elif BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
    285         pExpected->FPUDP  = Bs3SelPtrToFlat(&MmioReg.pb[off]);
    286 # else
    287         pExpected->FPUDP  = BS3_FP_OFF(&MmioReg.pb[off]);
    288 # endif
    289         CHECK_STATE(FMUL);
    290 
    291         /* check for timeout every now an then. */
    292         if (   (iLoop & 0xfff) == 0xfff
    293             && g_cBs3PitTicks - uStartTick >= 20 * 20) /* 20 seconds*/
    294             break;
    295     }
    296 
    297     Bs3PitDisable();
    298     return 0;
    299 }
    300 # endif
    30157#endif /* BS3_INSTANTIATING_MODE */
    30258

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1-template.mac

    r61535 r61538  
    11; $Id$
    22;; @file
    3 ; BS3Kit - bs3-fpustate-1, assembly template.
     3; BS3Kit - bs3-cpu-decoding-1, assembly template.
    44;
    55
    … …  
    3838
    3939
    40 ;;
    41 ; Initializes the FPU state and saves it to pFxState.
    42 ;
    43 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_InitState)(X86FXSTATE BS3_FAR *pFxState, void *pvMmioReg);
    44 ;
    45 BS3_PROC_BEGIN_MODE bs3FpuState1_InitState, BS3_PBC_NEAR
    46         BS3_CALL_CONV_PROLOG 2
    47         push    xBP
    48         mov     xBP, xSP
    49         push    xBX
    50 TONLY16 push    ds
    51         pushf
    52 TONLY64 sub     xSP, 20h
    53 
    54         ;
    55         ; x87 state.
    56         ;
    57         fninit
    58         fld     dword [TMPL_DATA16_WRT(g_r32V1)]
    59         fld     qword [TMPL_DATA16_WRT(g_r64V1)]
    60         fld     tword [TMPL_DATA16_WRT(g_r80V1)]
    61         fld     qword [TMPL_DATA16_WRT(g_r64V1)]
    62         fld     dword [TMPL_DATA16_WRT(g_r32V2)]
    63         fld     dword [TMPL_DATA16_WRT(g_r80_QNaNMax)]
    64         fld     tword [TMPL_DATA16_WRT(g_r80_SNaNMax)]
    65         fld     tword [TMPL_DATA16_WRT(g_r80_ThirtyTwo)]
    66 
    67         ;
    68         ; We'll later be using FMUL to test actually using the FPU in RC & R0,
    69         ; so for everything to line up correctly with FPU CS:IP and FPU DS:DP,
    70         ; we'll call the function here too.  This has the benefitial side effect
    71         ; of loading correct FPU DS/DS values so we can check that they don't
    72         ; get lost either.  Also, we now don't have to guess whether the CPU
    73         ; emulation sets CS/DS or not.
    74         ;
    75 TONLY16 push    xPRE [xBP + xCB + cbCurRetAddr + sCB + 2]
    76         push    xPRE [xBP + xCB + cbCurRetAddr + sCB]
    77         BS3_CALL TMPL_NM(bs3FpuState1_FMul), 1
    78         add     xSP, sCB
    79 
    80         ;
    81         ; SSE state
    82         ;
    83         movdqu  xmm0, [TMPL_DATA16_WRT(g_r32_0dot1)]
    84         movdqu  xmm1, [TMPL_DATA16_WRT(g_r32_Two)]
    85         movdqu  xmm2, [TMPL_DATA16_WRT(g_r32_ThirtyTwo)]
    86         movdqu  xmm3, [TMPL_DATA16_WRT(g_r32_ThirtyTwo)]
    87         movdqu  xmm4, [TMPL_DATA16_WRT(g_r32_SNaN)]
    88         movdqu  xmm5, [TMPL_DATA16_WRT(g_r32_NegQNaN)]
    89         movdqu  xmm6, [TMPL_DATA16_WRT(g_r64_Zero)]
    90         movdqu  xmm7, [TMPL_DATA16_WRT(g_r64_Two)]
    91 %if TMPL_BITS == 64
    92         movdqu  xmm8, [TMPL_DATA16_WRT(g_r64_Ten)]
    93         movdqu  xmm9, [TMPL_DATA16_WRT(g_r64_ThirtyTwo)]
    94         movdqu  xmm10, [TMPL_DATA16_WRT(g_r64_Max)]
    95         movdqu  xmm11, [TMPL_DATA16_WRT(g_r64_SNaN)]
    96         movdqu  xmm12, [TMPL_DATA16_WRT(g_r64_NegQNaN)]
    97         movdqu  xmm13, [TMPL_DATA16_WRT(g_r64_QNaNMax)]
    98         movdqu  xmm14, [TMPL_DATA16_WRT(g_r64_DnMax)]
    99         movdqu  xmm15, [TMPL_DATA16_WRT(g_r80_Eleven)]
    100 %endif
    101 
    102         ;; @todo status regs
    103 
    104         ;
    105         ; Save it.  Note that DS is no longer valid in 16-bit code.
    106         ; To be on the safe side, we load and save the state once again.
    107         ;
    108 TONLY16 mov     ds, [xBP + xCB + cbCurRetAddr + 2]
    109         mov     xBX, [xBP + xCB + cbCurRetAddr]
    110         cli
    111 %if TMPL_BITS == 64
    112         o64 fxsave [xBX]
    113         fninit
    114         o64 fxrstor [xBX]
    115         o64 fxsave [xBX]
    116 %else
    117         fxsave  [xBX]
    118         fninit
    119         fxrstor [xBX]
    120         fxsave  [xBX]
    121 %endif
    122 
    123 .return:
    124 TONLY64 add     xSP, 20h
    125         popf
    126 TONLY16 pop     ds
    127         pop     xBX
    128         mov     xSP, xBP
    129         pop     xBP
    130         BS3_CALL_CONV_EPILOG 2
    131         BS3_HYBRID_RET
    132 BS3_PROC_END_MODE   bs3FpuState1_InitState
    133 
    134 
    135 ;;
    136 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Restore)(X86FXSTATE const BS3_FAR *pFxState);
    137 ;
    138 BS3_PROC_BEGIN_MODE bs3FpuState1_Restore, BS3_PBC_NEAR
    139         push    xBP
    140         mov     xBP, xSP
    141 
    142 %if TMPL_BITS == 64
    143         o64     fxrstor [rcx]
    144 
    145 %elif TMPL_BITS == 32
    146         mov     eax, [xBP + xCB*2]
    147         fxrstor [eax]
    148 
    149 %elif TMPL_BITS == 16
    150         mov     ax, ds
    151         mov     ds, [xBP + xCB + cbCurRetAddr + 2]
    152         mov     xBX, [xBP + xCB + cbCurRetAddr]
    153         fxrstor [bx]
    154         mov     ds, ax
    155 %else
    156  %error TMPL_BITS
    157 %endif
    158 
    159         mov     xSP, xBP
    160         pop     xBP
    161         BS3_HYBRID_RET
    162 BS3_PROC_END_MODE   bs3FpuState1_Restore
    163 
    164 ;;
    165 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_Save)(X86FXSTATE BS3_FAR *pFxState);
    166 ;
    167 BS3_PROC_BEGIN_MODE bs3FpuState1_Save, BS3_PBC_NEAR
    168         push    xBP
    169         mov     xBP, xSP
    170 
    171 %if TMPL_BITS == 64
    172         o64     fxsave [rcx]
    173 
    174 %elif TMPL_BITS == 32
    175         mov     eax, [xBP + xCB*2]
    176         fxsave  [eax]
    177 
    178 %elif TMPL_BITS == 16
    179         push    bx
    180         push    ds
    181         mov     ds, [xBP + xCB + cbCurRetAddr + 2]
    182         mov     bx, [xBP + xCB + cbCurRetAddr]
    183         fxsave  [bx]
    184         pop     ds
    185         pop     bx
    186 %else
    187  %error TMPL_BITS
    188 %endif
    189 
    190         mov     xSP, xBP
    191         pop     xBP
    192         BS3_HYBRID_RET
    193 BS3_PROC_END_MODE   bs3FpuState1_Save
    194 
    195 
    196 ;;
    197 ; Performs a MOVDQU write on the specified memory.
    198 ;
    199 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Write)(void *pvMmioReg);
    200 ;
    201 BS3_PROC_BEGIN_MODE bs3FpuState1_MovDQU_Write, BS3_PBC_NEAR
    202         BS3_CALL_CONV_PROLOG 1
    203         push    xBP
    204         mov     xBP, xSP
    205         push    xBX
    206 TONLY16 push    ds
    207 
    208         ; Load the register pointer.
    209         mov     xBX, [xBP + xCB + cbCurRetAddr]
    210 TONLY16 mov     ds,  [xBP + xCB + cbCurRetAddr + 2]
    211 
    212         ; Do read.
    213         movdqu  [xBX], xmm3
    214 
    215 TONLY16 pop     ds
    216         pop     xBX
    217         leave
    218         BS3_CALL_CONV_EPILOG 1
    219         BS3_HYBRID_RET
    220 BS3_PROC_END_MODE   bs3FpuState1_MovDQU_Write
    221 
    222 
    223 ;;
    224 ; Performs a MOVDQU write to the specified memory.
    225 ;
    226 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_MovDQU_Read)(void *pvMmioReg);
    227 ;
    228 BS3_PROC_BEGIN_MODE bs3FpuState1_MovDQU_Read, BS3_PBC_NEAR
    229         BS3_CALL_CONV_PROLOG 1
    230         push    xBP
    231         mov     xBP, xSP
    232         push    xBX
    233 TONLY16 push    ds
    234         sub     xSP, 20h
    235 %if TMPL_BITS == 16
    236         movdqu  [xBP - xCB - xCB - 2 - 18h], xmm2
    237 %else
    238         movdqu  [xSP], xmm2
    239 %endif
    240 
    241         ; Load the register pointer.
    242         mov     xBX, [xBP + xCB + cbCurRetAddr]
    243 TONLY16 mov     ds,  [xBP + xCB + cbCurRetAddr + 2]
    244 
    245 
    246         ; Do read.
    247         movdqu  xmm2, [xBX]
    248 
    249 %if TMPL_BITS == 16
    250         movdqu  xmm2, [xBP - xCB - xCB - 2 - 18h]
    251 %else
    252         movdqu  xmm2, [xSP]
    253 %endif
    254         add     xSP, 20h
    255 TONLY16 pop     ds
    256         pop     xBX
    257         mov     xSP, xBP
    258         pop     xBP
    259         BS3_CALL_CONV_EPILOG 1
    260         BS3_HYBRID_RET
    261 BS3_PROC_END_MODE   bs3FpuState1_MovDQU_Read
    262 
    263 
    264 ;;
    265 ; Performs a FNSTENV write on the specified memory.
    266 ;
    267 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FNStEnv)(void *pvMmioReg);
    268 ;
    269 BS3_PROC_BEGIN_MODE bs3FpuState1_FNStEnv, BS3_PBC_NEAR
    270         BS3_CALL_CONV_PROLOG 1
    271         push    xBP
    272         mov     xBP, xSP
    273         push    xBX
    274 TONLY16 push    ds
    275 
    276         ; Load the register pointer.
    277         mov     xBX, [xBP + xCB + cbCurRetAddr]
    278 TONLY16 mov     ds,  [xBP + xCB + cbCurRetAddr + 2]
    279 
    280         ; Just write.
    281         fnstenv [xBX]
    282 
    283 TONLY16 pop     ds
    284         pop     xBX
    285         mov     xSP, xBP
    286         pop     xBP
    287         BS3_CALL_CONV_EPILOG 1
    288         BS3_HYBRID_RET
    289 BS3_PROC_END_MODE   bs3FpuState1_FNStEnv
    290 
    291 
    292 ;;
    293 ; Performs a FMUL on the specified memory, after writing a 64-bit value to it first.
    294 ;
    295 ; BS3_DECL_NEAR(void) TMPL_NM(bs3FpuState1_FMul)(void *pvMmioReg);
    296 ;
    297 BS3_PROC_BEGIN_MODE bs3FpuState1_FMul, BS3_PBC_NEAR
    298         BS3_CALL_CONV_PROLOG 1
    299         push    xBP
    300         mov     xBP, xSP
    301         push    xBX
    302 TONLY16 push    ds
    303 
    304         ; Load the value we'll be multiplying with into register(s) while ds is DATA16.
    305         mov     sAX, [TMPL_DATA16_WRT(g_r64_One)]
    306 TNOT64  mov     edx, [4 + TMPL_DATA16_WRT(g_r64_One)]
    307 
    308         ; Load the register pointer.
    309         mov     xBX, [xBP + xCB + cbCurRetAddr]
    310 TONLY16 mov     ds,  [xBP + xCB + cbCurRetAddr + 2]
    311 
    312         ; Just write.
    313         mov     [xBX], sAX
    314 TNOT64  mov     [xBX + 4], edx
    315         call    .do_it
    316 
    317 TONLY16 pop     ds
    318         pop     xBX
    319         mov     xSP, xBP
    320         pop     xBP
    321         BS3_CALL_CONV_EPILOG 1
    322         BS3_HYBRID_RET
    323 .do_it:
    324         fmul    qword [xBX]
    325         ret
    326 BS3_PROC_END_MODE   bs3FpuState1_FMul
    327 
    328 
    32940%include "bs3kit-template-footer.mac"   ; reset environment
    33041

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-decoding-1.c32

    r61535 r61538  
    11/* $Id$ */
    22/** @file
    3  * BS3Kit - bs3-fpustate-1, 16-bit C code.
     3 * BS3Kit - bs3-cpu-decoding-1, 32-bit C code.
    44 */
    55
    … …  
    3232#include <iprt/asm-amd64-x86.h>
    3333
     34/**
     35 * Simple test.
     36 */
     37typedef struct CPUDECODE1TST
     38{
     39    uint8_t fFlags;
     40    uint8_t cbUd;
     41    uint8_t cbOpcodes;
     42    uint8_t abOpcodes[21];
     43} CPUDECODE1TST;
     44typedef CPUDECODE1TST BS3_FAR *PCPUDECODE1TST;
     45
     46#define P_CS  X86_OP_PRF_CS
     47#define P_SS  X86_OP_PRF_SS
     48#define P_DS  X86_OP_PRF_DS
     49#define P_ES  X86_OP_PRF_ES
     50#define P_FS  X86_OP_PRF_FS
     51#define P_GS  X86_OP_PRF_GS
     52#define P_OZ  X86_OP_PRF_SIZE_OP
     53#define P_AZ  X86_OP_PRF_SIZE_ADDR
     54#define P_LK  X86_OP_PRF_LOCK
     55#define P_RZ  X86_OP_PRF_REPZ
     56#define P_RN  X86_OP_PRF_REPNZ
     57
     58
     59CPUDECODE1TST const g_aSimpleTests[] =
     60{
     61    {  0,  2, 2,  { 0x0f, 0x38, } },
     62    {  0,  3, 3,  { P_LK, 0x0f, 0x38, } },
     63};
     64
     65void DecodeEdgeTest(void)
     66{
     67    /*
     68     * Allocate and initialize a page pair
     69     */
     70    uint8_t BS3_FAR *pbPages  = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32);
     71    if (pbPages)
     72    {
     73        unsigned        i;
     74        BS3REGCTX       Ctx;
     75        BS3TRAPFRAME    TrapFrame;
     76        bs3kit.h
     77//BS3_CMN_PROTO_STUB(void, Bs3TrapSetJmpAndRestore,(PCBS3REGCTX pCtxRestore, PBS3TRAPFRAME pTrapFrame));
     78
     79        for (i = 0; i < RT_ELEMENTS(g_aSimpleTests); i++)
     80        {
     81            unsigned off = g_aSimpleTests[i].cbOpcodes;
     82            while (off-- > 0)
     83            {
     84                Bs3MemCpy(&pbPages[X86_PAGE_SIZE - off], &g_aSimpleTests[i].abOpcodes[0], off);
     85
     86            }
     87        }
     88
     89        Bs3MemGuardedTestPageFree(pbPages);
     90    }
     91    else
     92        Bs3TestFailed("Failed to allocate two pages!\n");
     93
     94    /*
     95     * Test instruction sequences.
     96     */
     97
     98
     99}
     100
    34101
    35102BS3_DECL(void) Main_pe32()
    … …  
    43110}
    44111
    45 
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