Changeset 61581 in vbox

Timestamp:

Jun 8, 2016 2:35:00 PM (9 years ago)

Author:

vboxsync

Message:

VMM/APIC: Fix remote IRR bit for level-triggered LINT0 interrupts and make LINT0/LINT1 only edge-triggered interrupts
on an edge-transition to the active state. For this we need to track the interrupt line state for LINT0/LINT1 pins.
Saved-state change will follow.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (3 diffs)
• VMMR3/APIC.cpp (modified) (1 diff)
• include/APICInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -1213 +1213 @@
             apicClearVectorInReg(&pXApicPage->tmr, uVector);
             apicBusBroadcastEoi(pVCpu, uVector);
+
+            /*
+             * Clear the remote IRR bit for level-triggered, fixed mode LINT0 interrupt.
+             * The LINT1 pin does not support level-triggered interrupts.
+             * See Intel spec. 10.5.1 "Local Vector Table".
+             */
+            uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
+            if (   XAPIC_LVT_GET_REMOTE_IRR(uLvtLint0)
+                && XAPIC_LVT_GET_VECTOR(uLvtLint0) == uVector
+                && XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint0) == XAPICDELIVERYMODE_FIXED)
+            {
+                ASMAtomicAndU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, ~XAPIC_LVT_REMOTE_IRR);
+                Log2(("APIC%u: apicSetEoi: Cleared remote-IRR for LINT0. uVector=%#x\n", pVCpu->idCpu, uVector));
+            }
+
             Log2(("APIC%u: apicSetEoi: Cleared level triggered interrupt from TMR. uVector=%#x\n", pVCpu->idCpu, uVector));
         }
@@ -2292 +2307 @@
                 case XAPICDELIVERYMODE_FIXED:
                 {
+                    PAPICCPU       pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+                    uint8_t const  uVector  = XAPIC_LVT_GET_VECTOR(uLvt);
+                    bool           fActive  = RT_BOOL(u8Level & 1);
+                    bool volatile *pfActiveLine = u8Pin == 0 ? &pApicCpu->fActiveLint0 : &pApicCpu->fActiveLint1;
+                    /** @todo Polarity is busted elsewhere, we need to fix that
+                     *        first. See @bugref{8386#c7}. */
+#if 0
+                    uint8_t const u8Polarity = XAPIC_LVT_GET_POLARITY(uLvt);
+                    fActive ^= u8Polarity; */
+#endif
+                    if (!fActive)
+                    {
+                        ASMAtomicWriteBool(pfActiveLine, false);
+                        break;
+                    }
+
                     /* Level-sensitive interrupts are not supported for LINT1. See Intel spec. 10.5.1 "Local Vector Table". */
                     if (offLvt == XAPIC_OFF_LVT_LINT1)
@@ -2299 +2330 @@
                               use level-sensitive triggering, regardless if edge-sensitive triggering is selected."
                               means. */
-                    /* fallthru */
+
+                    bool fSendIntr;
+                    if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
+                    {
+                        /* Recognize and send the interrupt only on an edge transition. */
+                        fSendIntr = ASMAtomicCmpXchgBool(pfActiveLine, true, false);
+                    }
+                    else
+                    {
+                        /* For level-triggered interrupts, redundant interrupts are not a problem. */
+                        Assert(enmTriggerMode == XAPICTRIGGERMODE_LEVEL);
+                        ASMAtomicCmpXchgBool(pfActiveLine, true, false);
+
+                        /* Only when the remote IRR isn't set, set it and send the interrupt. */
+                        if (!(pXApicPage->lvt_lint0.all.u32LvtLint0 & XAPIC_LVT_REMOTE_IRR))
+                        {
+                            Assert(offLvt == XAPIC_OFF_LVT_LINT0);
+                            ASMAtomicOrU32((volatile uint32_t *)&pXApicPage->lvt_lint0.all.u32LvtLint0, XAPIC_LVT_REMOTE_IRR);
+                            fSendIntr = true;
+                        }
+                        else
+                            fSendIntr = false;
+                    }
+
+                    if (fSendIntr)
+                    {
+                        VMCPUSET DestCpuSet;
+                        VMCPUSET_EMPTY(&DestCpuSet);
+                        VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
+                        rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode,
+                                                &DestCpuSet, rcRZ);
+                    }
+                    break;
                 }
+
                 case XAPICDELIVERYMODE_SMI:
                 case XAPICDELIVERYMODE_NMI:

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -217 +217 @@
     RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
     RT_BZERO(pApicCpu->pvApicPibR3,   sizeof(APICPIB));
+
+    /* Clear the interrupt line states for LINT0 and LINT1 pins. */
+    pApicCpu->fActiveLint0 = false;
+    pApicCpu->fActiveLint1 = false;
 }
 

trunk/src/VBox/VMM/include/APICInternal.h

@@ -1286 +1286 @@
     /** The APIC PIB for level-sensitive interrupts. */
     APICPIB                     ApicPibLevel;
+    /** Whether the LINT0 interrupt line is active. */
+    bool volatile               fActiveLint0;
+    /** Whether the LINT1 interrupt line is active. */
+    bool volatile               fActiveLint1;
+    /** Alignment padding. */
+    uint8_t                     auAlignment0[6];
     /** @} */