Changeset 61647 in vbox for trunk/include
- Timestamp:
- Jun 10, 2016 8:28:24 AM (9 years ago)
- svn:sync-xref-src-repo-rev:
- 107997
- File:
-
- 1 edited
-
trunk/include/VBox/vmm/hm_vmx.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/hm_vmx.h
r61646 r61647 152 152 */ 153 153 /** Unsupported pin-based VM-execution controls combo. */ 154 #define VMX_UFC_CTRL_PIN_EXEC 0154 #define VMX_UFC_CTRL_PIN_EXEC 1 155 155 /** Unsupported processor-based VM-execution controls combo. */ 156 #define VMX_UFC_CTRL_PROC_EXEC 1156 #define VMX_UFC_CTRL_PROC_EXEC 2 157 157 /** Unsupported move debug register VM-exit combo. */ 158 #define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 2158 #define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3 159 159 /** Unsupported VM-entry controls combo. */ 160 #define VMX_UFC_CTRL_ENTRY 3160 #define VMX_UFC_CTRL_ENTRY 4 161 161 /** Unsupported VM-exit controls combo. */ 162 #define VMX_UFC_CTRL_EXIT 4162 #define VMX_UFC_CTRL_EXIT 5 163 163 /** MSR storage capacity of the VMCS autoload/store area is not sufficient 164 164 * for storing host MSRs. */ 165 #define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 5165 #define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6 166 166 /** MSR storage capacity of the VMCS autoload/store area is not sufficient 167 167 * for storing guest MSRs. */ 168 #define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 6168 #define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7 169 169 /** Invalid VMCS size. */ 170 #define VMX_UFC_INVALID_VMCS_SIZE 7170 #define VMX_UFC_INVALID_VMCS_SIZE 8 171 171 /** Unsupported secondary processor-based VM-execution controls combo. */ 172 #define VMX_UFC_CTRL_PROC_EXEC2 8172 #define VMX_UFC_CTRL_PROC_EXEC2 9 173 173 /** Invalid unrestricted-guest execution controls combo. */ 174 #define VMX_UFC_INVALID_UX_COMBO 9174 #define VMX_UFC_INVALID_UX_COMBO 10 175 175 /** EPT flush type not supported. */ 176 #define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 1 0176 #define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11 177 177 /** EPT paging structure memory type is not write-back. */ 178 #define VMX_UFC_EPT_MEM_TYPE_NOT_WB 1 1178 #define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12 179 179 /** EPT requires INVEPT instr. support but it's not available. */ 180 #define VMX_UFC_EPT_INVEPT_UNAVAILABLE 1 2180 #define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13 181 181 /** EPT requires page-walk length of 4. */ 182 #define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 1 3182 #define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14 183 183 /** @} */ 184 184 … … 188 188 */ 189 189 /** An error occurred while checking invalid-guest-state. */ 190 #define VMX_IGS_ERROR 0190 #define VMX_IGS_ERROR 500 191 191 /** The invalid guest-state checks did not find any reason why. */ 192 #define VMX_IGS_REASON_NOT_FOUND 1192 #define VMX_IGS_REASON_NOT_FOUND 501 193 193 /** CR0 fixed1 bits invalid. */ 194 #define VMX_IGS_CR0_FIXED1 2194 #define VMX_IGS_CR0_FIXED1 502 195 195 /** CR0 fixed0 bits invalid. */ 196 #define VMX_IGS_CR0_FIXED0 3196 #define VMX_IGS_CR0_FIXED0 503 197 197 /** CR0.PE and CR0.PE invalid VT-x/host combination. */ 198 #define VMX_IGS_CR0_PG_PE_COMBO 4198 #define VMX_IGS_CR0_PG_PE_COMBO 504 199 199 /** CR4 fixed1 bits invalid. */ 200 #define VMX_IGS_CR4_FIXED1 5 200 #define VMX_IGS_CR4_FIXED1 505 201 201 /** CR4 fixed0 bits invalid. */ 202 #define VMX_IGS_CR4_FIXED0 6202 #define VMX_IGS_CR4_FIXED0 506 203 203 /** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when 204 204 * VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */ 205 #define VMX_IGS_DEBUGCTL_MSR_RESERVED 7205 #define VMX_IGS_DEBUGCTL_MSR_RESERVED 507 206 206 /** CR0.PG not set for long-mode when not using unrestricted guest. */ 207 #define VMX_IGS_CR0_PG_LONGMODE 8207 #define VMX_IGS_CR0_PG_LONGMODE 508 208 208 /** CR4.PAE not set for long-mode guest when not using unrestricted guest. */ 209 #define VMX_IGS_CR4_PAE_LONGMODE 9209 #define VMX_IGS_CR4_PAE_LONGMODE 509 210 210 /** CR4.PCIDE set for 32-bit guest. */ 211 #define VMX_IGS_CR4_PCIDE 10211 #define VMX_IGS_CR4_PCIDE 510 212 212 /** VMCS' DR7 reserved bits not set to 0. */ 213 #define VMX_IGS_DR7_RESERVED 11213 #define VMX_IGS_DR7_RESERVED 511 214 214 /** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */ 215 #define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 12215 #define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512 216 216 /** VMCS' EFER MSR reserved bits not set to 0. */ 217 #define VMX_IGS_EFER_MSR_RESERVED 13217 #define VMX_IGS_EFER_MSR_RESERVED 513 218 218 /** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */ 219 #define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 14219 #define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514 220 220 /** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging 221 221 * without unrestricted guest. */ 222 #define VMX_IGS_EFER_LMA_LME_MISMATCH 15222 #define VMX_IGS_EFER_LMA_LME_MISMATCH 515 223 223 /** CS.Attr.P bit invalid. */ 224 #define VMX_IGS_CS_ATTR_P_INVALID 16224 #define VMX_IGS_CS_ATTR_P_INVALID 516 225 225 /** CS.Attr reserved bits not set to 0. */ 226 #define VMX_IGS_CS_ATTR_RESERVED 17226 #define VMX_IGS_CS_ATTR_RESERVED 517 227 227 /** CS.Attr.G bit invalid. */ 228 #define VMX_IGS_CS_ATTR_G_INVALID 18228 #define VMX_IGS_CS_ATTR_G_INVALID 518 229 229 /** CS is unusable. */ 230 #define VMX_IGS_CS_ATTR_UNUSABLE 19230 #define VMX_IGS_CS_ATTR_UNUSABLE 519 231 231 /** CS and SS DPL unequal. */ 232 #define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 20232 #define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520 233 233 /** CS and SS DPL mismatch. */ 234 #define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 21234 #define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521 235 235 /** CS Attr.Type invalid. */ 236 #define VMX_IGS_CS_ATTR_TYPE_INVALID 22236 #define VMX_IGS_CS_ATTR_TYPE_INVALID 522 237 237 /** CS and SS RPL unequal. */ 238 #define VMX_IGS_SS_CS_RPL_UNEQUAL 23238 #define VMX_IGS_SS_CS_RPL_UNEQUAL 523 239 239 /** SS.Attr.DPL and SS RPL unequal. */ 240 #define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 24240 #define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524 241 241 /** SS.Attr.DPL invalid for segment type. */ 242 #define VMX_IGS_SS_ATTR_DPL_INVALID 25242 #define VMX_IGS_SS_ATTR_DPL_INVALID 525 243 243 /** SS.Attr.Type invalid. */ 244 #define VMX_IGS_SS_ATTR_TYPE_INVALID 26244 #define VMX_IGS_SS_ATTR_TYPE_INVALID 526 245 245 /** SS.Attr.P bit invalid. */ 246 #define VMX_IGS_SS_ATTR_P_INVALID 27246 #define VMX_IGS_SS_ATTR_P_INVALID 527 247 247 /** SS.Attr reserved bits not set to 0. */ 248 #define VMX_IGS_SS_ATTR_RESERVED 28248 #define VMX_IGS_SS_ATTR_RESERVED 528 249 249 /** SS.Attr.G bit invalid. */ 250 #define VMX_IGS_SS_ATTR_G_INVALID 29250 #define VMX_IGS_SS_ATTR_G_INVALID 529 251 251 /** DS.Attr.A bit invalid. */ 252 #define VMX_IGS_DS_ATTR_A_INVALID 30252 #define VMX_IGS_DS_ATTR_A_INVALID 530 253 253 /** DS.Attr.P bit invalid. */ 254 #define VMX_IGS_DS_ATTR_P_INVALID 31254 #define VMX_IGS_DS_ATTR_P_INVALID 531 255 255 /** DS.Attr.DPL and DS RPL unequal. */ 256 #define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 32256 #define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532 257 257 /** DS.Attr reserved bits not set to 0. */ 258 #define VMX_IGS_DS_ATTR_RESERVED 33258 #define VMX_IGS_DS_ATTR_RESERVED 533 259 259 /** DS.Attr.G bit invalid. */ 260 #define VMX_IGS_DS_ATTR_G_INVALID 34260 #define VMX_IGS_DS_ATTR_G_INVALID 534 261 261 /** DS.Attr.Type invalid. */ 262 #define VMX_IGS_DS_ATTR_TYPE_INVALID 35262 #define VMX_IGS_DS_ATTR_TYPE_INVALID 535 263 263 /** ES.Attr.A bit invalid. */ 264 #define VMX_IGS_ES_ATTR_A_INVALID 36264 #define VMX_IGS_ES_ATTR_A_INVALID 536 265 265 /** ES.Attr.P bit invalid. */ 266 #define VMX_IGS_ES_ATTR_P_INVALID 37266 #define VMX_IGS_ES_ATTR_P_INVALID 537 267 267 /** ES.Attr.DPL and DS RPL unequal. */ 268 #define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 38268 #define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538 269 269 /** ES.Attr reserved bits not set to 0. */ 270 #define VMX_IGS_ES_ATTR_RESERVED 39270 #define VMX_IGS_ES_ATTR_RESERVED 539 271 271 /** ES.Attr.G bit invalid. */ 272 #define VMX_IGS_ES_ATTR_G_INVALID 40272 #define VMX_IGS_ES_ATTR_G_INVALID 540 273 273 /** ES.Attr.Type invalid. */ 274 #define VMX_IGS_ES_ATTR_TYPE_INVALID 41274 #define VMX_IGS_ES_ATTR_TYPE_INVALID 541 275 275 /** FS.Attr.A bit invalid. */ 276 #define VMX_IGS_FS_ATTR_A_INVALID 42276 #define VMX_IGS_FS_ATTR_A_INVALID 542 277 277 /** FS.Attr.P bit invalid. */ 278 #define VMX_IGS_FS_ATTR_P_INVALID 43278 #define VMX_IGS_FS_ATTR_P_INVALID 543 279 279 /** FS.Attr.DPL and DS RPL unequal. */ 280 #define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 44280 #define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544 281 281 /** FS.Attr reserved bits not set to 0. */ 282 #define VMX_IGS_FS_ATTR_RESERVED 45282 #define VMX_IGS_FS_ATTR_RESERVED 545 283 283 /** FS.Attr.G bit invalid. */ 284 #define VMX_IGS_FS_ATTR_G_INVALID 46284 #define VMX_IGS_FS_ATTR_G_INVALID 546 285 285 /** FS.Attr.Type invalid. */ 286 #define VMX_IGS_FS_ATTR_TYPE_INVALID 47286 #define VMX_IGS_FS_ATTR_TYPE_INVALID 547 287 287 /** GS.Attr.A bit invalid. */ 288 #define VMX_IGS_GS_ATTR_A_INVALID 48288 #define VMX_IGS_GS_ATTR_A_INVALID 548 289 289 /** GS.Attr.P bit invalid. */ 290 #define VMX_IGS_GS_ATTR_P_INVALID 49290 #define VMX_IGS_GS_ATTR_P_INVALID 549 291 291 /** GS.Attr.DPL and DS RPL unequal. */ 292 #define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 5 0292 #define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550 293 293 /** GS.Attr reserved bits not set to 0. */ 294 #define VMX_IGS_GS_ATTR_RESERVED 5 1294 #define VMX_IGS_GS_ATTR_RESERVED 551 295 295 /** GS.Attr.G bit invalid. */ 296 #define VMX_IGS_GS_ATTR_G_INVALID 5 2296 #define VMX_IGS_GS_ATTR_G_INVALID 552 297 297 /** GS.Attr.Type invalid. */ 298 #define VMX_IGS_GS_ATTR_TYPE_INVALID 5 3298 #define VMX_IGS_GS_ATTR_TYPE_INVALID 553 299 299 /** V86 mode CS.Base invalid. */ 300 #define VMX_IGS_V86_CS_BASE_INVALID 5 4300 #define VMX_IGS_V86_CS_BASE_INVALID 554 301 301 /** V86 mode CS.Limit invalid. */ 302 #define VMX_IGS_V86_CS_LIMIT_INVALID 55 302 #define VMX_IGS_V86_CS_LIMIT_INVALID 555 303 303 /** V86 mode CS.Attr invalid. */ 304 #define VMX_IGS_V86_CS_ATTR_INVALID 5 6304 #define VMX_IGS_V86_CS_ATTR_INVALID 556 305 305 /** V86 mode SS.Base invalid. */ 306 #define VMX_IGS_V86_SS_BASE_INVALID 5 7306 #define VMX_IGS_V86_SS_BASE_INVALID 557 307 307 /** V86 mode SS.Limit invalid. */ 308 #define VMX_IGS_V86_SS_LIMIT_INVALID 5 8308 #define VMX_IGS_V86_SS_LIMIT_INVALID 558 309 309 /** V86 mode SS.Attr invalid. */ 310 #define VMX_IGS_V86_SS_ATTR_INVALID 5 9310 #define VMX_IGS_V86_SS_ATTR_INVALID 559 311 311 /** V86 mode DS.Base invalid. */ 312 #define VMX_IGS_V86_DS_BASE_INVALID 60312 #define VMX_IGS_V86_DS_BASE_INVALID 560 313 313 /** V86 mode DS.Limit invalid. */ 314 #define VMX_IGS_V86_DS_LIMIT_INVALID 61314 #define VMX_IGS_V86_DS_LIMIT_INVALID 561 315 315 /** V86 mode DS.Attr invalid. */ 316 #define VMX_IGS_V86_DS_ATTR_INVALID 62316 #define VMX_IGS_V86_DS_ATTR_INVALID 562 317 317 /** V86 mode ES.Base invalid. */ 318 #define VMX_IGS_V86_ES_BASE_INVALID 63318 #define VMX_IGS_V86_ES_BASE_INVALID 563 319 319 /** V86 mode ES.Limit invalid. */ 320 #define VMX_IGS_V86_ES_LIMIT_INVALID 64320 #define VMX_IGS_V86_ES_LIMIT_INVALID 564 321 321 /** V86 mode ES.Attr invalid. */ 322 #define VMX_IGS_V86_ES_ATTR_INVALID 65322 #define VMX_IGS_V86_ES_ATTR_INVALID 565 323 323 /** V86 mode FS.Base invalid. */ 324 #define VMX_IGS_V86_FS_BASE_INVALID 66324 #define VMX_IGS_V86_FS_BASE_INVALID 566 325 325 /** V86 mode FS.Limit invalid. */ 326 #define VMX_IGS_V86_FS_LIMIT_INVALID 67326 #define VMX_IGS_V86_FS_LIMIT_INVALID 567 327 327 /** V86 mode FS.Attr invalid. */ 328 #define VMX_IGS_V86_FS_ATTR_INVALID 68328 #define VMX_IGS_V86_FS_ATTR_INVALID 568 329 329 /** V86 mode GS.Base invalid. */ 330 #define VMX_IGS_V86_GS_BASE_INVALID 69330 #define VMX_IGS_V86_GS_BASE_INVALID 569 331 331 /** V86 mode GS.Limit invalid. */ 332 #define VMX_IGS_V86_GS_LIMIT_INVALID 70332 #define VMX_IGS_V86_GS_LIMIT_INVALID 570 333 333 /** V86 mode GS.Attr invalid. */ 334 #define VMX_IGS_V86_GS_ATTR_INVALID 71334 #define VMX_IGS_V86_GS_ATTR_INVALID 571 335 335 /** Longmode CS.Base invalid. */ 336 #define VMX_IGS_LONGMODE_CS_BASE_INVALID 72336 #define VMX_IGS_LONGMODE_CS_BASE_INVALID 572 337 337 /** Longmode SS.Base invalid. */ 338 #define VMX_IGS_LONGMODE_SS_BASE_INVALID 73338 #define VMX_IGS_LONGMODE_SS_BASE_INVALID 573 339 339 /** Longmode DS.Base invalid. */ 340 #define VMX_IGS_LONGMODE_DS_BASE_INVALID 74340 #define VMX_IGS_LONGMODE_DS_BASE_INVALID 574 341 341 /** Longmode ES.Base invalid. */ 342 #define VMX_IGS_LONGMODE_ES_BASE_INVALID 75342 #define VMX_IGS_LONGMODE_ES_BASE_INVALID 575 343 343 /** SYSENTER ESP is not canonical. */ 344 #define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 76344 #define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576 345 345 /** SYSENTER EIP is not canonical. */ 346 #define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 77346 #define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577 347 347 /** PAT MSR invalid. */ 348 #define VMX_IGS_PAT_MSR_INVALID 78348 #define VMX_IGS_PAT_MSR_INVALID 578 349 349 /** PAT MSR reserved bits not set to 0. */ 350 #define VMX_IGS_PAT_MSR_RESERVED 79350 #define VMX_IGS_PAT_MSR_RESERVED 579 351 351 /** GDTR.Base is not canonical. */ 352 #define VMX_IGS_GDTR_BASE_NOT_CANONICAL 80352 #define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580 353 353 /** IDTR.Base is not canonical. */ 354 #define VMX_IGS_IDTR_BASE_NOT_CANONICAL 81354 #define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581 355 355 /** GDTR.Limit invalid. */ 356 #define VMX_IGS_GDTR_LIMIT_INVALID 82356 #define VMX_IGS_GDTR_LIMIT_INVALID 582 357 357 /** IDTR.Limit invalid. */ 358 #define VMX_IGS_IDTR_LIMIT_INVALID 83358 #define VMX_IGS_IDTR_LIMIT_INVALID 583 359 359 /** Longmode RIP is invalid. */ 360 #define VMX_IGS_LONGMODE_RIP_INVALID 84360 #define VMX_IGS_LONGMODE_RIP_INVALID 584 361 361 /** RFLAGS reserved bits not set to 0. */ 362 #define VMX_IGS_RFLAGS_RESERVED 85362 #define VMX_IGS_RFLAGS_RESERVED 585 363 363 /** RFLAGS RA1 reserved bits not set to 1. */ 364 #define VMX_IGS_RFLAGS_RESERVED1 86364 #define VMX_IGS_RFLAGS_RESERVED1 586 365 365 /** RFLAGS.VM (V86 mode) invalid. */ 366 #define VMX_IGS_RFLAGS_VM_INVALID 87366 #define VMX_IGS_RFLAGS_VM_INVALID 587 367 367 /** RFLAGS.IF invalid. */ 368 #define VMX_IGS_RFLAGS_IF_INVALID 88368 #define VMX_IGS_RFLAGS_IF_INVALID 588 369 369 /** Activity state invalid. */ 370 #define VMX_IGS_ACTIVITY_STATE_INVALID 89370 #define VMX_IGS_ACTIVITY_STATE_INVALID 589 371 371 /** Activity state HLT invalid when SS.Attr.DPL is not zero. */ 372 #define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 90372 #define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590 373 373 /** Activity state ACTIVE invalid when block-by-STI or MOV SS. */ 374 #define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 91374 #define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591 375 375 /** Activity state SIPI WAIT invalid. */ 376 #define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 92376 #define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592 377 377 /** Interruptibility state reserved bits not set to 0. */ 378 #define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 93378 #define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593 379 379 /** Interruptibility state cannot be block-by-STI -and- MOV SS. */ 380 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 94380 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594 381 381 /** Interruptibility state block-by-STI invalid for EFLAGS. */ 382 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 95382 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595 383 383 /** Interruptibility state invalid while trying to deliver external 384 384 * interrupt. */ 385 #define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 96385 #define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596 386 386 /** Interruptibility state block-by-MOVSS invalid while trying to deliver an 387 387 * NMI. */ 388 #define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 97388 #define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597 389 389 /** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */ 390 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 98390 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598 391 391 /** Interruptibility state block-by-SMI invalid when trying to enter SMM. */ 392 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 99392 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599 393 393 /** Interruptibility state block-by-STI (maybe) invalid when trying to 394 394 * deliver an NMI. */ 395 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 100395 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600 396 396 /** Interruptibility state block-by-NMI invalid when virtual-NMIs control is 397 397 * active. */ 398 #define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 101398 #define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601 399 399 /** Pending debug exceptions reserved bits not set to 0. */ 400 #define VMX_IGS_PENDING_DEBUG_RESERVED 102400 #define VMX_IGS_PENDING_DEBUG_RESERVED 602 401 401 /** Longmode pending debug exceptions reserved bits not set to 0. */ 402 #define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 103402 #define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603 403 403 /** Pending debug exceptions.BS bit is not set when it should be. */ 404 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 104404 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604 405 405 /** Pending debug exceptions.BS bit is not clear when it should be. */ 406 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 105406 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605 407 407 /** VMCS link pointer reserved bits not set to 0. */ 408 #define VMX_IGS_VMCS_LINK_PTR_RESERVED 106408 #define VMX_IGS_VMCS_LINK_PTR_RESERVED 606 409 409 /** TR cannot index into LDT, TI bit MBZ. */ 410 #define VMX_IGS_TR_TI_INVALID 107410 #define VMX_IGS_TR_TI_INVALID 607 411 411 /** LDTR cannot index into LDT. TI bit MBZ. */ 412 #define VMX_IGS_LDTR_TI_INVALID 108412 #define VMX_IGS_LDTR_TI_INVALID 608 413 413 /** TR.Base is not canonical. */ 414 #define VMX_IGS_TR_BASE_NOT_CANONICAL 109414 #define VMX_IGS_TR_BASE_NOT_CANONICAL 609 415 415 /** FS.Base is not canonical. */ 416 #define VMX_IGS_FS_BASE_NOT_CANONICAL 110416 #define VMX_IGS_FS_BASE_NOT_CANONICAL 610 417 417 /** GS.Base is not canonical. */ 418 #define VMX_IGS_GS_BASE_NOT_CANONICAL 111418 #define VMX_IGS_GS_BASE_NOT_CANONICAL 611 419 419 /** LDTR.Base is not canonical. */ 420 #define VMX_IGS_LDTR_BASE_NOT_CANONICAL 112420 #define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612 421 421 /** TR is unusable. */ 422 #define VMX_IGS_TR_ATTR_UNUSABLE 113422 #define VMX_IGS_TR_ATTR_UNUSABLE 613 423 423 /** TR.Attr.S bit invalid. */ 424 #define VMX_IGS_TR_ATTR_S_INVALID 114424 #define VMX_IGS_TR_ATTR_S_INVALID 614 425 425 /** TR is not present. */ 426 #define VMX_IGS_TR_ATTR_P_INVALID 115426 #define VMX_IGS_TR_ATTR_P_INVALID 615 427 427 /** TR.Attr reserved bits not set to 0. */ 428 #define VMX_IGS_TR_ATTR_RESERVED 116428 #define VMX_IGS_TR_ATTR_RESERVED 616 429 429 /** TR.Attr.G bit invalid. */ 430 #define VMX_IGS_TR_ATTR_G_INVALID 117430 #define VMX_IGS_TR_ATTR_G_INVALID 617 431 431 /** Longmode TR.Attr.Type invalid. */ 432 #define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 118432 #define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618 433 433 /** TR.Attr.Type invalid. */ 434 #define VMX_IGS_TR_ATTR_TYPE_INVALID 119434 #define VMX_IGS_TR_ATTR_TYPE_INVALID 619 435 435 /** CS.Attr.S invalid. */ 436 #define VMX_IGS_CS_ATTR_S_INVALID 120436 #define VMX_IGS_CS_ATTR_S_INVALID 620 437 437 /** CS.Attr.DPL invalid. */ 438 #define VMX_IGS_CS_ATTR_DPL_INVALID 121438 #define VMX_IGS_CS_ATTR_DPL_INVALID 621 439 439 /** PAE PDPTE reserved bits not set to 0. */ 440 #define VMX_IGS_PAE_PDPTE_RESERVED 123440 #define VMX_IGS_PAE_PDPTE_RESERVED 623 441 441 /** @} */ 442 442
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