Changeset 61736 in vbox
- Timestamp:
- Jun 17, 2016 8:00:50 AM (9 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/APICAll.cpp
r61735 r61736 1573 1573 * @param puValue Where to store the register value. 1574 1574 */ 1575 static intapicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue)1575 DECLINLINE(VBOXSTRICTRC) apicReadRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t *puValue) 1576 1576 { 1577 1577 VMCPU_ASSERT_EMT(pVCpu); 1578 1578 Assert(offReg <= XAPIC_OFF_MAX_VALID); 1579 1579 1580 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);1581 uint32_t uValue = 0;1582 intrc = VINF_SUCCESS;1580 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu); 1581 uint32_t uValue = 0; 1582 VBOXSTRICTRC rc = VINF_SUCCESS; 1583 1583 switch (offReg) 1584 1584 { … … 1629 1629 { 1630 1630 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu)); 1631 rc = VBOXSTRICTRC_VAL(apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue));1631 rc = apicGetTimerCcr(pVCpu, VINF_IOM_R3_MMIO_READ, &uValue); 1632 1632 break; 1633 1633 } … … 1647 1647 { 1648 1648 Assert(!XAPIC_IN_X2APIC_MODE(pVCpu)); 1649 rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, offReg); 1649 rc = PDMDevHlpDBGFStop(pApicDev->CTX_SUFF(pDevIns), RT_SRC_POS, "VCPU[%u]: offReg=%#RX16\n", pVCpu->idCpu, 1650 offReg); 1650 1651 apicSetError(pVCpu, XAPIC_ESR_ILLEGAL_REG_ADDRESS); 1651 1652 break; … … 1667 1668 * @param uValue The register value. 1668 1669 */ 1669 static VBOXSTRICTRCapicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue)1670 DECLINLINE(VBOXSTRICTRC) apicWriteRegister(PAPICDEV pApicDev, PVMCPU pVCpu, uint16_t offReg, uint32_t uValue) 1670 1671 { 1671 1672 VMCPU_ASSERT_EMT(pVCpu); … … 2535 2536 STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioRead)); 2536 2537 2537 int rc = apicReadRegister(pApicDev, pVCpu, offReg, &uValue);2538 int rc = VBOXSTRICTRC_VAL(apicReadRegister(pApicDev, pVCpu, offReg, &uValue)); 2538 2539 *(uint32_t *)pv = uValue; 2539 2540
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