Changeset 61744 in vbox

Timestamp:

Jun 17, 2016 1:35:12 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

108130

Message:

VMM/APIC: Reserve the full MSR range defined by the architecture rather than just the valid ones
to the APIC device. Shouldn't change behaviour as we'll still be #GP'ing just from the APIC now
rather than as an unhandled MSR in IEM.

File:

• trunk/src/VBox/VMM/VMMR3/APIC.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -61 +61 @@
 *********************************************************************************************************************************/
 /**
- * Array of MSR ranges supported by the x2APIC.
- */
-static CPUMMSRRANGE const g_aMsrRanges_x2Apic[] =
-{
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_ID,        MSR_IA32_X2APIC_VERSION,   "x2APIC range 0"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_VERSION,   MSR_IA32_X2APIC_TPR,       "x2APIC range 1"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_TPR,       MSR_IA32_X2APIC_TPR,       "x2APIC range 2"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_PPR,       MSR_IA32_X2APIC_EOI,       "x2APIC range 3"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_LDR,       MSR_IA32_X2APIC_LDR,       "x2APIC range 4"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_SVR,       MSR_IA32_X2APIC_SVR,       "x2APIC range 5"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_ISR0,      MSR_IA32_X2APIC_ISR7,      "x2APIC range 7"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_TMR0,      MSR_IA32_X2APIC_TMR7,      "x2APIC range 8"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_IRR0,      MSR_IA32_X2APIC_IRR7,      "x2APIC range 8"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_ESR,       MSR_IA32_X2APIC_ESR,       "x2APIC range 9"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_LVT_CMCI,  MSR_IA32_X2APIC_ICR,       "x2APIC range 10"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_LVT_TIMER, MSR_IA32_X2APIC_TIMER_CCR, "x2APIC range 11"),
-    X2APIC_MSRRANGE(MSR_IA32_X2APIC_TIMER_DCR, MSR_IA32_X2APIC_SELF_IPI,  "x2APIC range 12")
-};
+ * MSR range supported by the x2APIC.
+ * See Intel spec. 10.12.2 "x2APIC Register Availability".
+ */
+static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
 #undef X2APIC_MSRRANGE
 
@@ -1688 +1674 @@
             CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
 
-            /* Insert all MSR ranges of the x2APIC. */
-            for (size_t i = 0; i < RT_ELEMENTS(g_aMsrRanges_x2Apic); i++)
-            {
-                rc = CPUMR3MsrRangesInsert(pVM, &g_aMsrRanges_x2Apic[i]);
-                AssertLogRelRCReturn(rc, rc);
-            }
+            /* Insert the MSR range of the x2APIC. */
+            rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
+            AssertLogRelRCReturn(rc, rc);
             break;
         }