VirtualBox

Changeset 61776 in vbox for trunk/include


Ignore:
Timestamp:
Jun 20, 2016 11:25:06 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
108168
Message:

CPUM,APIC: Per-CPU APIC CPUID feature bit and MSR_IA32_APICBASE GP mask adjustments.

  • Changed the PDMAPICHLPR3::pfnChangeFeature to pfnSetFeatureLevel, removing the RC and R0 versions.
  • Only use pfnSetFeatureLevel from the APIC constructor to communicate to CPUM the max APIC feature level, not to globally flip CPUID[1].EDX[9].
  • Renamed APIC enmOriginalMode to enmMaxMode, changing the type of it and the corresponding config values to PDMAPICMODE. This makes the above simpler and eliminates two conversion functions. It also makes APICMODE private to the APIC again.
  • Introduced CPUMSetGuestCpuIdPerCpuApicFeature for the per-CPU APIC feature bit management.
  • Introduced CPUMCPUIDLEAF_F_CONTAINS_APIC which works same as CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE and CPUMCPUIDLEAF_F_CONTAINS_APIC_ID. Updated existing CPU profiles with this.
  • Made the patch manager helper function actually handle CPUMCPUIDLEAF_F_CONTAINS_APIC and CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE (the latter previously relied on CPUMSetGuestCpuIdFeature/CPUMClearGuestCpuIdFeature from CPUMSetGuestCR4).
  • Pushed CPUMSetGuestCpuIdFeature, CPUMGetGuestCpuIdFeature and CPUMClearGuestCpuIdFeature down to ring-3 only (now CPUMR3*). The latter two function are deprecated.
  • Added call to CPUMSetGuestCpuIdPerCpuApicFeature from load function just in case the APIC is disabled by the guest at the time of saving.
  • CPUMSetGuestCpuIdFeature ensures we've got a MSR_IA32_APICBASE register when enabling the APIC.
  • CPUMSetGuestCpuIdFeature adjust the MSR_IA32_APICBASE GP mask when enabling x2APIC so setting MSR_IA32_APICBASE_EXTD does not trap.
Location:
trunk/include
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/apic.h

    r61116 r61776  
    141141#define XAPIC_OFF_LVT_EXT_END                XAPIC_OFF_LVT_CMCI
    142142
    143 /**
    144  * APIC operating modes.
    145  *
    146  * The values match hardware states.
    147  * See Intel spec. 10.12.1 "Detecting and Enabling x2APIC Mode".
    148  */
    149 typedef enum APICMODE
    150 {
    151     APICMODE_DISABLED = 0,
    152     APICMODE_INVALID,
    153     APICMODE_XAPIC,
    154     APICMODE_X2APIC
    155 } APICMODE;
    156 
    157143RT_C_DECLS_BEGIN
    158144

  • trunk/include/VBox/vmm/cpum.h

    r61348 r61776  
    4646{
    4747    CPUMCPUIDFEATURE_INVALID = 0,
    48     /** The APIC feature bit. (Std+Ext) */
     48    /** The APIC feature bit. (Std+Ext)
     49     * Note! There is a per-cpu flag for masking this CPUID feature bit when the
     50     *       APICBASE.ENABLED bit is zero.  So, this feature is only set/cleared
     51     *       at VM construction time like all the others.  This didn't used to be
     52     *       that way, this is new with 5.1. */
    4953    CPUMCPUIDFEATURE_APIC,
    5054    /** The sysenter/sysexit feature bit. (Std) */
    … …  
    7074    /** The MWait Extensions bits (Std) */
    7175    CPUMCPUIDFEATURE_MWAIT_EXTS,
    72     /** The CR4.OSXSAVE bit CPUID mirroring, only use from CPUMSetGuestCR4. */
    73     CPUMCPUIDFEATURE_OSXSAVE,
    7476    /** 32bit hackishness. */
    7577    CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
    … …  
    327329/** The leaf contains an OSXSAVE which needs individual handling on each CPU. */
    328330#define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE            RT_BIT_32(2)
     331/** The leaf contains an APIC feature bit which is tied to APICBASE.EN. */
     332#define CPUMCPUIDLEAF_F_CONTAINS_APIC               RT_BIT_32(3)
    329333/** Mask of the valid flags. */
    330 #define CPUMCPUIDLEAF_F_VALID_MASK                  UINT32_C(0x7)
     334#define CPUMCPUIDLEAF_F_VALID_MASK                  UINT32_C(0xf)
    331335/** @} */
    332336
    … …  
    11131117VMMDECL(int)        CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
    11141118VMMDECL(void)       CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
    1115 VMMDECL(void)       CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
    1116 VMMDECL(void)       CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
    1117 VMMDECL(bool)       CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
     1119VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
     1120VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
     1121VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
     1122VMM_INT_DECL(bool)  CPUMSetGuestCpuIdPerCpuApicFeature(PVMCPU pVCpu, bool fVisible);
    11181123VMMDECL(void)       CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
    11191124VMM_INT_DECL(void)  CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);

  • trunk/include/VBox/vmm/cpum.mac

    r60891 r61776  
    5151    .fFlags             resd    1
    5252endstruc
    53 %define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES RT_BIT_32(0)
     53%define CPUMCPUIDLEAF_F_INTEL_TOPOLOGY_SUBLEAVES    RT_BIT_32(0)
     54%define CPUMCPUIDLEAF_F_CONTAINS_APIC_ID            RT_BIT_32(1)
     55%define CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE            RT_BIT_32(2)
     56%define CPUMCPUIDLEAF_F_CONTAINS_APIC               RT_BIT_32(3)
     57
    5458
    5559;;

  • trunk/include/VBox/vmm/pdmdev.h

    r61735 r61776  
    14211421
    14221422    /**
    1423      * Modifies APIC-related bits in the CPUID feature mask.
    1424      *
    1425      * @param   pDevIns         Device instance of the APIC.
    1426      * @param   enmMode         Supported APIC mode.
    1427      */
    1428     DECLRCCALLBACKMEMBER(void, pfnChangeFeature,(PPDMDEVINS pDevIns, PDMAPICMODE enmMode));
    1429 
    1430     /**
    14311423     * Acquires the PDM lock.
    14321424     *
    … …  
    14611453
    14621454/** Current PDMAPICHLPRC version number. */
    1463 #define PDM_APICHLPRC_VERSION                   PDM_VERSION_MAKE(0xfff5, 4, 0)
     1455#define PDM_APICHLPRC_VERSION                   PDM_VERSION_MAKE(0xfff5, 5, 0)
    14641456
    14651457
    … …  
    15071499     */
    15081500    DECLR0CALLBACKMEMBER(uint32_t, pfnCalcIrqTag,(PPDMDEVINS pDevIns, uint8_t u8Level));
    1509 
    1510     /**
    1511      * Modifies APIC-related bits in the CPUID feature mask.
    1512      *
    1513      * @param   pDevIns         Device instance of the APIC.
    1514      * @param   enmMode         Supported APIC mode.
    1515      */
    1516     DECLR0CALLBACKMEMBER(void, pfnChangeFeature,(PPDMDEVINS pDevIns, PDMAPICMODE enmMode));
    15171501
    15181502    /**
    … …  
    15491533
    15501534/** Current PDMAPICHLPR0 version number. */
    1551 #define PDM_APICHLPR0_VERSION                   PDM_VERSION_MAKE(0xfff4, 4, 0)
     1535#define PDM_APICHLPR0_VERSION                   PDM_VERSION_MAKE(0xfff4, 5, 0)
    15521536
    15531537/**
    … …  
    15961580
    15971581    /**
    1598      * Modifies APIC-related bits in the CPUID feature mask.
     1582     * Modifies APIC-related bits in the CPUID feature mask and preps MSRs.
    15991583     *
    16001584     * @param   pDevIns         Device instance of the APIC.
    1601      * @param   enmMode         Supported APIC mode.
    1602      */
    1603     DECLR3CALLBACKMEMBER(void, pfnChangeFeature,(PPDMDEVINS pDevIns, PDMAPICMODE enmMode));
     1585     * @param   enmMode         Max supported APIC mode.
     1586     */
     1587    DECLR3CALLBACKMEMBER(void, pfnSetFeatureLevel,(PPDMDEVINS pDevIns, PDMAPICMODE enmMode));
    16041588
    16051589    /**

  • trunk/include/iprt/x86.h

    r61249 r61776  
    454454/** ECX Bit 26 - XSAVE instruction. */
    455455#define X86_CPUID_FEATURE_ECX_XSAVE     RT_BIT_32(26)
    456 /** ECX Bit 27 - OSXSAVE instruction. */
     456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
    457457#define X86_CPUID_FEATURE_ECX_OSXSAVE   RT_BIT_32(27)
    458458/** ECX Bit 28 - AVX. */
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