Changeset 61776 in vbox for trunk/src/VBox/VMM/VMMRC

Timestamp:

Jun 20, 2016 11:25:06 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

108168

Message:

CPUM,APIC: Per-CPU APIC CPUID feature bit and MSR_IA32_APICBASE GP mask adjustments.

• Changed the PDMAPICHLPR3::pfnChangeFeature to pfnSetFeatureLevel, removing the RC and R0 versions.
• Only use pfnSetFeatureLevel from the APIC constructor to communicate to CPUM the max APIC feature level, not to globally flip CPUID[1].EDX[9].
• Renamed APIC enmOriginalMode to enmMaxMode, changing the type of it and the corresponding config values to PDMAPICMODE. This makes the above simpler and eliminates two conversion functions. It also makes APICMODE private to the APIC again.
• Introduced CPUMSetGuestCpuIdPerCpuApicFeature for the per-CPU APIC feature bit management.
• Introduced CPUMCPUIDLEAF_F_CONTAINS_APIC which works same as CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE and CPUMCPUIDLEAF_F_CONTAINS_APIC_ID. Updated existing CPU profiles with this.
• Made the patch manager helper function actually handle CPUMCPUIDLEAF_F_CONTAINS_APIC and CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE (the latter previously relied on CPUMSetGuestCpuIdFeature/CPUMClearGuestCpuIdFeature from CPUMSetGuestCR4).
• Pushed CPUMSetGuestCpuIdFeature, CPUMGetGuestCpuIdFeature and CPUMClearGuestCpuIdFeature down to ring-3 only (now CPUMR3*). The latter two function are deprecated.
• Added call to CPUMSetGuestCpuIdPerCpuApicFeature from load function just in case the APIC is disabled by the guest at the time of saving.
• CPUMSetGuestCpuIdFeature ensures we've got a MSR_IA32_APICBASE register when enabling the APIC.
• CPUMSetGuestCpuIdFeature adjust the MSR_IA32_APICBASE GP mask when enabling x2APIC so setting MSR_IA32_APICBASE_EXTD does not trap.

Location:

trunk/src/VBox/VMM/VMMRC

Files:

• CPUMRCPatchHlp.asm (modified) (5 diffs)
• PDMRCDevice.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMRC/CPUMRCPatchHlp.asm

@@ -24 +24 @@
 %include "VBox/vmm/vm.mac"
 %include "VMMRC.mac"
+%include "iprt/x86.mac"
 
 
@@ -69 +70 @@
     ; Find the middle element
     mov     ebx, edx
-cpuid_lookup_leaf_ebx_loeaded:
+cpuid_lookup_leaf_ebx_loaded:
     sub     ebx, ecx
     shr     ebx, 1 + CPUMCPUIDLEAF_SIZE_LOG2
@@ -83 +84 @@
     cmp     ecx, ebx                    ; start == middle? if so, we failed.
     mov     edx, ebx                    ; end = middle;
-    jne     cpuid_lookup_leaf_ebx_loeaded
+    jne     cpuid_lookup_leaf_ebx_loaded
     jmp     cpuid_unknown
 
@@ -179 +180 @@
 
     ;
-    ; Normal return.
+    ; Normal return unless flags (we ignore APIC_ID as we only have a single CPU with ID 0).
     ;
 cpuid_fetch:
+    test    dword [ss:ebx + CPUMCPUIDLEAF.fFlags], CPUMCPUIDLEAF_F_CONTAINS_APIC | CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
+    jnz     cpuid_fetch_with_flags
     mov     edx, [ss:ebx + CPUMCPUIDLEAF.uEdx]
     mov     ecx, [ss:ebx + CPUMCPUIDLEAF.uEcx]
@@ -191 +194 @@
     add     esp, 12
     ret
+
+
+    ;
+    ; Need to adjust the result according to VCpu state.
+    ;
+    ; APIC:    CPUID[0x00000001].EDX[9]  &= pVCpu->cpum.s.fCpuIdApicFeatureVisible;
+    ;          CPUID[0x80000001].EDX[9]  &= pVCpu->cpum.s.fCpuIdApicFeatureVisible;
+    ;
+    ; OSXSAVE: CPUID[0x00000001].ECX[27]  = CR4.OSXSAVE;
+    ;
+cpuid_fetch_with_flags:
+    mov     edx, [ss:ebx + CPUMCPUIDLEAF.uEdx]
+    mov     ecx, [ss:ebx + CPUMCPUIDLEAF.uEcx]
+
+    mov     eax, [ss:edi + VM.offVMCPU]
+
+    ; APIC
+    test    dword [ss:ebx + CPUMCPUIDLEAF.fFlags], CPUMCPUIDLEAF_F_CONTAINS_APIC
+    jz      cpuid_fetch_with_flags_done_apic
+    test    byte [ss:edi + eax + VMCPU.cpum + CPUMCPU.fCpuIdApicFeatureVisible], 0ffh
+    jnz     cpuid_fetch_with_flags_done_apic
+    and     edx, ~X86_CPUID_FEATURE_EDX_APIC
+cpuid_fetch_with_flags_done_apic:
+
+    ; OSXSAVE
+    test    dword [ss:ebx + CPUMCPUIDLEAF.fFlags], CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE
+    jz      cpuid_fetch_with_flags_done_osxsave
+    and     ecx, ~X86_CPUID_FEATURE_ECX_OSXSAVE
+    test    dword [ss:edi + eax + VMCPU.cpum + CPUMCPU.Guest.cr4], X86_CR4_OSXSAVE
+    jz      cpuid_fetch_with_flags_done_osxsave
+    or      ecx, X86_CPUID_FEATURE_ECX_OSXSAVE
+cpuid_fetch_with_flags_done_osxsave:
+
+    ; Load the two remaining registers and jump to the common normal exit.
+    mov     eax, [ss:ebx + CPUMCPUIDLEAF.uEax]
+    mov     ebx, [ss:ebx + CPUMCPUIDLEAF.uEbx]
+    jmp     cpuid_done
+
 ENDPROC CPUMPatchHlpCpuId
 

trunk/src/VBox/VMM/VMMRC/PDMRCDevice.cpp

@@ -602 +602 @@
 
 
-/** @interface_method_impl{PDMAPICHLPRC,pfnChangeFeature} */
-static DECLCALLBACK(void) pdmRCApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICMODE enmMode)
-{
-    PDMDEV_ASSERT_DEVINS(pDevIns);
-    LogFlow(("pdmRCApicHlp_ChangeFeature: caller=%p/%d: mode=%d\n", pDevIns, pDevIns->iInstance, (int)enmMode));
-    switch (enmMode)
-    {
-        case PDMAPICMODE_NONE:
-            CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
-            CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
-            break;
-        case PDMAPICMODE_APIC:
-            CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
-            CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
-            break;
-        case PDMAPICMODE_X2APIC:
-            CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_X2APIC);
-            CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC);
-            break;
-        default:
-            AssertMsgFailed(("Unknown APIC mode: %d\n", (int)enmMode));
-    }
-}
-
-
 /** @interface_method_impl{PDMAPICHLPRC,pfnLock} */
 static DECLCALLBACK(int) pdmRCApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
@@ -661 +636 @@
     pdmRCApicHlp_BusBroadcastEoi,
     pdmRCApicHlp_CalcIrqTag,
-    pdmRCApicHlp_ChangeFeature,
     pdmRCApicHlp_Lock,
     pdmRCApicHlp_Unlock,