Changeset 61794 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Jun 21, 2016 2:11:06 PM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

108192

Message:

VMM/APIC: Cleanup.

File:

• trunk/src/VBox/VMM/VMMAll/APICAll.cpp (modified) (33 diffs)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -529 +529 @@
             {
                 Log2(("APIC%u: apicSignalNextPendingIntr: Signaling pending interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
-                APICSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
+                apicSetInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
             }
             else
@@ -541 +541 @@
     {
         Log2(("APIC%u: apicSignalNextPendingIntr: APIC software-disabled, clearing pending interrupt\n", pVCpu->idCpu));
-        APICClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
+        apicClearInterruptFF(pVCpu, PDMAPICIRQ_HARDWARE);
     }
 }
@@ -614 +614 @@
                 if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
                     && apicIsEnabled(&pVM->aCpus[idCpu]))
-                    APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
+                    apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             }
             break;
@@ -624 +624 @@
             if (   idCpu < pVM->cCpus
                 && apicIsEnabled(&pVM->aCpus[idCpu]))
-                APICPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
+                apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             else
                 Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
@@ -637 +637 @@
                 {
                     Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
-                    APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
+                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
                 }
             }
@@ -651 +651 @@
                 {
                     Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
-                    APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
+                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
                 }
             }
@@ -696 +696 @@
                 {
                     Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
-                    APICSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
+                    apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
                 }
             break;
@@ -1419 +1419 @@
         pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
         if (uInitialCount)
-            APICStartTimer(pVCpu, uInitialCount);
+            apicStartTimer(pVCpu, uInitialCount);
         else
-            APICStopTimer(pVCpu);
+            apicStopTimer(pVCpu);
         TMTimerUnlock(pTimer);
     }
@@ -1793 +1793 @@
  * @interface_method_impl{PDMAPICREG,pfnReadMsrR3}
  */
-VMMDECL(VBOXSTRICTRC) APICReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
+VMM_INT_DECL(VBOXSTRICTRC) apicReadMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
 {
     /*
@@ -1900 +1900 @@
  * @interface_method_impl{PDMAPICREG,pfnWriteMsrR3}
  */
-VMMDECL(VBOXSTRICTRC) APICWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
+VMM_INT_DECL(VBOXSTRICTRC) apicWriteMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint32_t u32Reg, uint64_t u64Value)
 {
     /*
@@ -1990 +1990 @@
             {
                 uint8_t const uVector = XAPIC_SELF_IPI_GET_VECTOR(u32Value);
-                APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
+                apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
                 rcStrict = VINF_SUCCESS;
                 break;
@@ -2037 +2037 @@
  * @interface_method_impl{PDMAPICREG,pfnSetBaseMsrR3}
  */
-VMMDECL(VBOXSTRICTRC) APICSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
+VMMDECL(VBOXSTRICTRC) apicSetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint64_t u64BaseMsr)
 {
     Assert(pVCpu);
@@ -2094 +2094 @@
                  * need to update the CPUID leaf ourselves.
                  */
-                APICR3Reset(pVCpu, false /* fResetApicBaseMsr */);
+                apicR3ResetEx(pVCpu, false /* fResetApicBaseMsr */);
                 uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
                 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, false /*fVisible*/);
@@ -2174 +2174 @@
  * @interface_method_impl{PDMAPICREG,pfnGetBaseMsrR3}
  */
-VMMDECL(uint64_t) APICGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
+VMM_INT_DECL(uint64_t) apicGetBaseMsr(PPDMDEVINS pDevIns, PVMCPU pVCpu)
 {
     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
@@ -2186 +2186 @@
  * @interface_method_impl{PDMAPICREG,pfnSetTprR3}
  */
-VMMDECL(void) APICSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
+VMM_INT_DECL(void) apicSetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Tpr)
 {
     apicSetTpr(pVCpu, u8Tpr);
@@ -2218 +2218 @@
  * @interface_method_impl{PDMAPICREG,pfnGetTprR3}
  */
-VMMDECL(uint8_t) APICGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr)
+VMMDECL(uint8_t) apicGetTpr(PPDMDEVINS pDevIns, PVMCPU pVCpu, bool *pfPending, uint8_t *pu8PendingIntr)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -2239 +2239 @@
  * @interface_method_impl{PDMAPICREG,pfnGetTimerFreqR3}
  */
-VMMDECL(uint64_t) APICGetTimerFreq(PPDMDEVINS pDevIns)
+VMM_INT_DECL(uint64_t) apicGetTimerFreq(PPDMDEVINS pDevIns)
 {
     PVM      pVM      = PDMDevHlpGetVM(pDevIns);
@@ -2253 +2253 @@
  * @remarks This is a private interface between the IOAPIC and the APIC.
  */
-VMMDECL(int) APICBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
+VMM_INT_DECL(int) apicBusDeliver(PPDMDEVINS pDevIns, uint8_t uDest, uint8_t uDestMode, uint8_t uDeliveryMode, uint8_t uVector,
                             uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc)
 {
@@ -2287 +2287 @@
  * @remarks This is a private interface between the PIC and the APIC.
  */
-VMMDECL(VBOXSTRICTRC) APICLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
+VMM_INT_DECL(VBOXSTRICTRC) apicLocalInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t u8Pin, uint8_t u8Level, int rcRZ)
 {
     NOREF(pDevIns);
@@ -2401 +2401 @@
                           u8Level ? "Raising" : "Lowering", u8Pin));
                     if (u8Level)
-                        APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
+                        apicSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
                     else
-                        APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
+                        apicClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
                     break;
                 }
@@ -2429 +2429 @@
                   u8Level ? "raising" : "lowering"));
             if (u8Level)
-                APICSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
+                apicSetInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
             else
-                APICClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
+                apicClearInterruptFF(pVCpu, PDMAPICIRQ_EXTINT);
         }
         else
@@ -2437 +2437 @@
             /* LINT1 behaves as NMI. */
             Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
-            APICSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
+            apicSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
         }
     }
@@ -2448 +2448 @@
  * @interface_method_impl{PDMAPICREG,pfnGetInterruptR3}
  */
-VMMDECL(int) APICGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
+VMM_INT_DECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, PVMCPU pVCpu, uint8_t *pu8Vector, uint32_t *pu32TagSrc)
 {
     VMCPU_ASSERT_EMT(pVCpu);
@@ -2520 +2520 @@
  * @callback_method_impl{FNIOMMMIOREAD}
  */
-VMMDECL(int) APICReadMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
+VMM_INT_DECL(int) apicReadMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
     NOREF(pvUser);
@@ -2544 +2544 @@
  * @callback_method_impl{FNIOMMMIOWRITE}
  */
-VMMDECL(int) APICWriteMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
+VMM_INT_DECL(int) apicWriteMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
 {
     NOREF(pvUser);
@@ -2557 +2557 @@
     STAM_COUNTER_INC(&pVCpu->apic.s.CTX_SUFF(StatMmioWrite));
 
-    Log2(("APIC%u: APICWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    Log2(("APIC%u: apicWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
 
     int rc = VBOXSTRICTRC_VAL(apicWriteRegister(pApicDev, pVCpu, offReg, uValue));
@@ -2570 +2570 @@
  * @param   enmType         The IRQ type.
  */
-VMMDECL(void) APICSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
+VMM_INT_DECL(void) apicSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
 {
     PVM      pVM      = pVCpu->CTX_SUFF(pVM);
@@ -2584 +2584 @@
  * @param   enmType         The IRQ type.
  */
-VMMDECL(void) APICClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
+VMM_INT_DECL(void) apicClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType)
 {
     PVM      pVM      = pVCpu->CTX_SUFF(pVM);
@@ -2606 +2606 @@
  * @thread  Any.
  */
-VMM_INT_DECL(void) APICPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
+VMM_INT_DECL(void) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
 {
     Assert(pVCpu);
@@ -2642 +2642 @@
                     {
                         Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
-                        APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
+                        apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
                     }
                 }
@@ -2657 +2657 @@
                 {
                     Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
-                    APICSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
+                    apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
                 }
             }
@@ -2683 +2683 @@
  * @thread  Any.
  */
-VMM_INT_DECL(void) APICStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
+VMM_INT_DECL(void) apicStartTimer(PVMCPU pVCpu, uint32_t uInitialCount)
 {
     Assert(pVCpu);
@@ -2715 +2715 @@
  * @thread  Any.
  */
-VMM_INT_DECL(void) APICStopTimer(PVMCPU pVCpu)
+VMM_INT_DECL(void) apicStopTimer(PVMCPU pVCpu)
 {
     Assert(pVCpu);