VirtualBox

Changeset 61795 in vbox


Ignore:
Timestamp:
Jun 21, 2016 2:18:04 PM (9 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
108193
Message:

VMM/APIC: Cleanup.

Location:
trunk/src/VBox/VMM
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r61794 r61795  
    20912091                 *
    20922092                 * We'll also manually manage the APIC base MSR here. We want a single-point of commit
    2093                  * at the end of this function rather than touching it in APICR3Reset. This means we also
     2093                 * at the end of this function rather than updating it in apicR3ResetCpu. This means we also
    20942094                 * need to update the CPUID leaf ourselves.
    20952095                 */
    2096                 apicR3ResetEx(pVCpu, false /* fResetApicBaseMsr */);
     2096                apicR3ResetCpu(pVCpu, false /* fResetApicBaseMsr */);
    20972097                uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
    20982098                CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, false /*fVisible*/);
    … …  
    23982398                case XAPICDELIVERYMODE_EXTINT:
    23992399                {
    2400                     Log2(("APIC%u: APICLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
     2400                    Log2(("APIC%u: apicLocalInterrupt: %s ExtINT through LINT%u\n", pVCpu->idCpu,
    24012401                          u8Level ? "Raising" : "Lowering", u8Pin));
    24022402                    if (u8Level)
    … …  
    24262426        {
    24272427            /* LINT0 behaves as an external interrupt pin. */
    2428             Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
     2428            Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, %s INTR\n", pVCpu->idCpu,
    24292429                  u8Level ? "raising" : "lowering"));
    24302430            if (u8Level)
    … …  
    24362436        {
    24372437            /* LINT1 behaves as NMI. */
    2438             Log2(("APIC%u: APICLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
     2438            Log2(("APIC%u: apicLocalInterrupt: APIC hardware-disabled, raising NMI\n", pVCpu->idCpu));
    24392439            apicSetInterruptFF(pVCpu, PDMAPICIRQ_NMI);
    24402440        }
    … …  
    24542454    NOREF(pu32TagSrc);
    24552455
    2456     LogFlow(("APIC%u: APICGetInterrupt:\n", pVCpu->idCpu));
     2456    LogFlow(("APIC%u: apicGetInterrupt:\n", pVCpu->idCpu));
    24572457
    24582458    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    … …  
    24752475                && XAPIC_TPR_GET_TP(uVector) <= XAPIC_TPR_GET_TP(uTpr))
    24762476            {
    2477                 Log2(("APIC%u: APICGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
     2477                Log2(("APIC%u: apicGetInterrupt: Interrupt masked. uVector=%#x uTpr=%#x SpuriousVector=%#x\n", pVCpu->idCpu,
    24782478                      uVector, uTpr, pXApicPage->svr.u.u8SpuriousVector));
    24792479                *pu8Vector = uVector;
    … …  
    24962496                apicSignalNextPendingIntr(pVCpu);
    24972497
    2498                 Log2(("APIC%u: APICGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
     2498                Log2(("APIC%u: apicGetInterrupt: Valid Interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
    24992499                *pu8Vector = uVector;
    25002500                return VINF_SUCCESS;
    … …  
    25032503            {
    25042504                STAM_COUNTER_INC(&pVCpu->apic.s.StatMaskedByPpr);
    2505                 Log2(("APIC%u: APICGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
     2505                Log2(("APIC%u: apicGetInterrupt: Interrupt's priority is not higher than the PPR. uVector=%#x PPR=%#x\n",
    25062506                      pVCpu->idCpu, uVector, uPpr));
    25072507            }
    25082508        }
    25092509        else
    2510             Log2(("APIC%u: APICGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
     2510            Log2(("APIC%u: apicGetInterrupt: No pending bits in IRR\n", pVCpu->idCpu));
    25112511    }
    25122512    else
    2513         Log2(("APIC%u: APICGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
     2513        Log2(("APIC%u: apicGetInterrupt: APIC %s disabled\n", pVCpu->idCpu, !fApicHwEnabled ? "hardware" : "software"));
    25142514
    25152515    return VERR_APIC_INTR_NOT_PENDING;
    … …  
    25362536    *(uint32_t *)pv = uValue;
    25372537
    2538     Log2(("APIC%u: APICReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
     2538    Log2(("APIC%u: apicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
    25392539    return rc;
    25402540}
    … …  
    26942694    uint64_t const cTicksToNext = (uint64_t)uInitialCount << uTimerShift;
    26952695
    2696     Log2(("APIC%u: APICStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
     2696    Log2(("APIC%u: apicStartTimer: uInitialCount=%#RX32 uTimerShift=%u cTicksToNext=%RU64\n", pVCpu->idCpu, uInitialCount,
    26972697          uTimerShift, cTicksToNext));
    26982698
    … …  
    27212721    Assert(TMTimerIsLockOwner(pApicCpu->CTX_SUFF(pTimer)));
    27222722
    2723     Log2(("APIC%u: APICStopTimer\n", pVCpu->idCpu));
     2723    Log2(("APIC%u: apicStopTimer\n", pVCpu->idCpu));
    27242724
    27252725    PTMTIMER pTimer = pApicCpu->CTX_SUFF(pTimer);

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r61794 r61795  
    292292 * @param   fResetApicBaseMsr   Whether to reset the APIC base MSR.
    293293 */
    294 VMMR3_INT_DECL(void) apicR3ResetEx(PVMCPU pVCpu, bool fResetApicBaseMsr)
     294VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
    295295{
    296296    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    297297
    298     LogFlow(("APIC%u: APICR3Reset: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
     298    LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
    299299
    300300#ifdef VBOX_STRICT
    … …  
    13011301            TMTimerStop(pApicCpu->pTimerR3);
    13021302
    1303         apicR3ResetEx(pVCpuDest, true /* fResetApicBaseMsr */);
     1303        apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
    13041304
    13051305        /* Clear the interrupt pending force flag. */
    … …  
    15051505                /* Initialize the virtual-APIC state. */
    15061506                RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
    1507                 apicR3ResetEx(pVCpu, true /* fResetApicBaseMsr */);
     1507                apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
    15081508
    15091509#ifdef DEBUG_ramshankar
    … …  
    16671667
    16681668    /*
    1669      * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
     1669     * We always require R0 functionality (e.g. apicGetTpr() called by HMR0 VT-x/AMD-V code).
    16701670     * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
    1671      * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
     1671     * to ring-3. We still need other handlers like apicGetTpr() in ring-0 for now.
    16721672     */
    16731673    {
    … …  
    18371837        APIC_REG_COUNTER(&pApicCpu->StatTprRead,       "Number of TPR reads.",  "/Devices/APIC/%u/TprRead");
    18381838        APIC_REG_COUNTER(&pApicCpu->StatEoiWrite,      "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
    1839         APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr,   "Number of times TPR masks an interrupt in APICGetInterrupt.",
     1839        APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr,   "Number of times TPR masks an interrupt in apicGetInterrupt.",
    18401840                         "/Devices/APIC/%u/MaskedByTpr");
    1841         APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr,   "Number of times PPR masks an interrupt in APICGetInterrupt.",
     1841        APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr,   "Number of times PPR masks an interrupt in apicGetInterrupt.",
    18421842                         "/Devices/APIC/%u/MaskedByPpr");
    18431843        APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",

  • trunk/src/VBox/VMM/include/APICInternal.h

    r61794 r61795  
    13491349    /** Profiling of APICUpdatePendingInterrupts().  */
    13501350    STAMPROFILE                 StatUpdatePendingIntrs;
    1351     /** Profiling of APICPostInterrupt().  */
     1351    /** Profiling of apicPostInterrupt().  */
    13521352    STAMPROFILE                 StatPostIntr;
    13531353    /** Number of times an interrupt is already pending in
    1354      *  APICPostInterrupts().*/
     1354     *  apicPostInterrupts().*/
    13551355    STAMCOUNTER                 StatPostIntrAlreadyPending;
    13561356    /** Number of times the timer callback is invoked. */
    … …  
    13621362    /** Number of times the EOI is written. */
    13631363    STAMCOUNTER                 StatEoiWrite;
    1364     /** Number of times TPR masks an interrupt in APICGetInterrupt(). */
     1364    /** Number of times TPR masks an interrupt in apicGetInterrupt(). */
    13651365    STAMCOUNTER                 StatMaskedByTpr;
    1366     /** Number of times PPR masks an interrupt in APICGetInterrupt(). */
     1366    /** Number of times PPR masks an interrupt in apicGetInterrupt(). */
    13671367    STAMCOUNTER                 StatMaskedByPpr;
    13681368    /** Number of times the timer ICR is written. */
    … …  
    14391439
    14401440#ifdef IN_RING3
    1441 VMMR3_INT_DECL(void)        apicR3ResetEx(PVMCPU pVCpu, bool fResetApicBaseMsr);
     1441VMMR3_INT_DECL(void)        apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr);
    14421442#endif
    14431443
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