Changeset 61847 in vbox for trunk/src/VBox/VMM

Timestamp:

Jun 23, 2016 12:03:01 PM (9 years ago)

Author:

vboxsync

Message:

IOAPIC, VMM/APIC: Use dedicated rc for when the APIC doesn't accept an IRQ (very rare but can happen).
Also added more stats, assertions to verify interrupt delivery a bit better.

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (25 diffs)
• VMMAll/PDMAll.cpp (modified) (3 diffs)
• VMMR3/APIC.cpp (modified) (1 diff)
• include/APICInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -598 +598 @@
  * @param   enmDeliveryMode     The delivery mode.
  * @param   pDestCpuSet         The destination CPU set.
+ * @param   pfIntrAccepted      Where to store whether this interrupt was
+ *                              accepted by the target APIC(s) or not.
+ *                              Optional, can be NULL.
  * @param   rcRZ                The return code if the operation cannot be
  *                              performed in the current context.
  */
 static VBOXSTRICTRC apicSendIntr(PVM pVM, PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode,
-                                 XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, int rcRZ)
-{
-    VBOXSTRICTRC  rcStrict = VINF_SUCCESS;
-    VMCPUID const cCpus    = pVM->cCpus;
+                                 XAPICDELIVERYMODE enmDeliveryMode, PCVMCPUSET pDestCpuSet, bool *pfIntrAccepted, int rcRZ)
+{
+    VBOXSTRICTRC  rcStrict  = VINF_SUCCESS;
+    VMCPUID const cCpus     = pVM->cCpus;
+    bool          fAccepted = false;
     switch (enmDeliveryMode)
     {
@@ -614 +618 @@
                 if (   VMCPUSET_IS_PRESENT(pDestCpuSet, idCpu)
                     && apicIsEnabled(&pVM->aCpus[idCpu]))
-                    apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
+                    fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             }
             break;
@@ -624 +628 @@
             if (   idCpu < pVM->cCpus
                 && apicIsEnabled(&pVM->aCpus[idCpu]))
-                apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
+                fAccepted = apicPostInterrupt(&pVM->aCpus[idCpu], uVector, enmTriggerMode);
             else
-                Log2(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
+                AssertMsgFailed(("APIC: apicSendIntr: No CPU found for lowest-priority delivery mode!\n"));
             break;
         }
@@ -638 +642 @@
                     Log2(("APIC: apicSendIntr: Raising SMI on VCPU%u\n", idCpu));
                     apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_SMI);
+                    fAccepted = true;
                 }
             }
@@ -652 +657 @@
                     Log2(("APIC: apicSendIntr: Raising NMI on VCPU%u\n", idCpu));
                     apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_NMI);
+                    fAccepted = true;
                 }
             }
@@ -665 +671 @@
                     Log2(("APIC: apicSendIntr: Issuing INIT to VCPU%u\n", idCpu));
                     VMMR3SendInitIpi(pVM, idCpu);
+                    fAccepted = true;
                 }
 #else
             /* We need to return to ring-3 to deliver the INIT. */
             rcStrict = rcRZ;
+            fAccepted = true;
 #endif
             break;
@@ -681 +689 @@
                     Log2(("APIC: apicSendIntr: Issuing SIPI to VCPU%u\n", idCpu));
                     VMMR3SendStartupIpi(pVM, idCpu, uVector);
+                    fAccepted = true;
                 }
 #else
             /* We need to return to ring-3 to deliver the SIPI. */
             rcStrict = rcRZ;
+            fAccepted = true;
             Log2(("APIC: apicSendIntr: SIPI issued, returning to RZ. rc=%Rrc\n", rcRZ));
 #endif
@@ -697 +707 @@
                     Log2(("APIC: apicSendIntr: Raising EXTINT on VCPU%u\n", idCpu));
                     apicSetInterruptFF(&pVM->aCpus[idCpu], PDMAPICIRQ_EXTINT);
+                    fAccepted = true;
                 }
             break;
@@ -735 +746 @@
         }
     }
+
+    if (pfIntrAccepted)
+        *pfIntrAccepted = fAccepted;
+
     return rcStrict;
 }
@@ -1006 +1021 @@
     }
 
-    return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet, rcRZ);
+    return apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
+                        NULL /* pfIntrAccepted */, rcRZ);
 }
 
@@ -1254 +1270 @@
         apicSignalNextPendingIntr(pVCpu);
     }
+    else
+        AssertMsgFailed(("APIC%u: apicSetEoi: Failed to find any ISR bit\n", pVCpu->idCpu));
 
     return VINF_SUCCESS;
@@ -2275 +2293 @@
           uVector));
 
+    bool     fIntrAccepted;
     VMCPUSET DestCpuSet;
     apicGetDestCpuSet(pVM, fDestMask, fBroadcastMask, enmDestMode, enmDeliveryMode, &DestCpuSet);
     VBOXSTRICTRC rcStrict = apicSendIntr(pVM, NULL /* pVCpu */, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
-                                         VINF_SUCCESS /* rcRZ */);
-    return VBOXSTRICTRC_VAL(rcStrict);
+                                         &fIntrAccepted, VINF_SUCCESS /* rcRZ */);
+    if (fIntrAccepted)
+        return VBOXSTRICTRC_VAL(rcStrict);
+    return VERR_APIC_INTR_DISCARDED;
 }
 
@@ -2379 +2400 @@
                         VMCPUSET_ADD(&DestCpuSet, pVCpu->idCpu);
                         rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode,
-                                                &DestCpuSet, rcRZ);
+                                                &DestCpuSet, NULL /* pfIntrAccepted */, rcRZ);
                     }
                     break;
@@ -2392 +2413 @@
                     uint8_t const uVector = XAPIC_LVT_GET_VECTOR(uLvt);
                     rcStrict = apicSendIntr(pVCpu->CTX_SUFF(pVM), pVCpu, uVector, enmTriggerMode, enmDeliveryMode, &DestCpuSet,
-                                            rcRZ);
+                                            NULL /* pfIntrAccepted */, rcRZ);
                     break;
                 }
@@ -2600 +2621 @@
  * Don't use this function to try and deliver ExtINT style interrupts.
  *
+ * @returns true if the interrupt was accepted, false otherwise.
  * @param   pVCpu               The cross context virtual CPU structure.
  * @param   uVector             The vector of the interrupt to be posted.
@@ -2606 +2628 @@
  * @thread  Any.
  */
-VMM_INT_DECL(void) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
+VMM_INT_DECL(bool) apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode)
 {
     Assert(pVCpu);
     Assert(uVector > XAPIC_ILLEGAL_VECTOR_END);
 
-    PVM      pVM      = pVCpu->CTX_SUFF(pVM);
-    PCAPIC   pApic    = VM_TO_APIC(pVM);
-    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
+    PVM      pVM       = pVCpu->CTX_SUFF(pVM);
+    PCAPIC   pApic     = VM_TO_APIC(pVM);
+    PAPICCPU pApicCpu  = VMCPU_TO_APICCPU(pVCpu);
+    bool     fAccepted = true;
 
     STAM_PROFILE_START(&pApicCpu->StatPostIntr, a);
@@ -2630 +2653 @@
         if (!apicTestVectorInReg(&pXApicPage->irr, uVector))     /* PAV */
         {
-            Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
+            Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u uVector=%#x\n", VMMGetCpuId(pVM), pVCpu->idCpu, uVector));
             if (enmTriggerMode == XAPICTRIGGERMODE_EDGE)
             {
@@ -2641 +2664 @@
                     if (!fAlreadySet)
                     {
-                        Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
+                        Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for edge-triggered intr. uVector=%#x\n", uVector));
                         apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
                     }
@@ -2656 +2679 @@
                 if (!fAlreadySet)
                 {
-                    Log2(("APIC: APICPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
+                    Log2(("APIC: apicPostInterrupt: Setting UPDATE_APIC FF for level-triggered intr. uVector=%#x\n", uVector));
                     apicSetInterruptFF(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
                 }
@@ -2663 +2686 @@
         else
         {
-            Log2(("APIC: APICPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
+            Log2(("APIC: apicPostInterrupt: SrcCpu=%u TargetCpu=%u. Vector %#x Already in IRR, skipping\n", VMMGetCpuId(pVM),
                   pVCpu->idCpu, uVector));
             STAM_COUNTER_INC(&pApicCpu->StatPostIntrAlreadyPending);
@@ -2669 +2692 @@
     }
     else
+    {
+        fAccepted = false;
         apicSetError(pVCpu, XAPIC_ESR_RECV_ILLEGAL_VECTOR);
+    }
 
     STAM_PROFILE_STOP(&pApicCpu->StatPostIntr, a);
+    return fAccepted;
 }
 
@@ -2817 +2844 @@
 
     /* Update edge-triggered pending interrupts. */
+    PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
     for (;;)
     {
@@ -2823 +2851 @@
             break;
 
-        PAPICPIB pPib = (PAPICPIB)pApicCpu->CTX_SUFF(pvApicPib);
         AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
-
         for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
         {
@@ -2845 +2871 @@
 
     /* Update level-triggered pending interrupts. */
+    pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
     for (;;)
     {
@@ -2851 +2878 @@
             break;
 
-        PAPICPIB pPib = (PAPICPIB)&pApicCpu->ApicPibLevel;
         AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 2 * RT_ELEMENTS(pPib->aVectorBitmap));
-
         for (size_t idxPib = 0, idxReg = 0; idxPib < RT_ELEMENTS(pPib->aVectorBitmap); idxPib++, idxReg += 2)
         {

trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

@@ -64 +64 @@
      * The local APIC has a higher priority than the PIC.
      */
+    int rc = VERR_NO_DATA;
     if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC))
     {
@@ -71 +72 @@
         uint32_t uTagSrc;
         uint8_t  uVector;
-        int rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc);
+        rc = pVM->pdm.s.Apic.CTX_SUFF(pfnGetInterrupt)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), pVCpu, &uVector, &uTagSrc);
         if (RT_SUCCESS(rc))
         {
@@ -119 +120 @@
 
     pdmUnlock(pVM);
-    return VERR_NO_DATA;
+    return rc;
 }
 

trunk/src/VBox/VMM/VMMR3/APIC.cpp

@@ -1797 +1797 @@
     } while(0)
 
-    bool const fHasRC = !HMIsEnabled(pVM);
+    bool const fHasRC = !HMIsEnabledNotMacro(pVM);
     for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
     {

trunk/src/VBox/VMM/include/APICInternal.h

@@ -1442 +1442 @@
                                              uint8_t uVector, uint8_t uPolarity, uint8_t uTriggerMode, uint32_t uTagSrc);
 
-VMM_INT_DECL(void)            apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode);
+VMM_INT_DECL(bool)            apicPostInterrupt(PVMCPU pVCpu, uint8_t uVector, XAPICTRIGGERMODE enmTriggerMode);
 VMM_INT_DECL(void)            apicStartTimer(PVMCPU pVCpu, uint32_t uInitialCount);
 VMM_INT_DECL(void)            apicStopTimer(PVMCPU pVCpu);