- Timestamp:
- Jul 22, 2016 10:09:53 AM (8 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 3 edited
-
VMMAll/GIMAllHv.cpp (modified) (12 diffs)
-
VMMR3/GIMHv.cpp (modified) (12 diffs)
-
include/GIMHvInternal.h (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp
r62357 r62417 286 286 if ( pMsgIn->uConnectionId == GIM_HV_VMBUS_MSG_CONNECTION_ID 287 287 && pMsgIn->enmMessageType == GIMHVMSGTYPE_VMBUS 288 && !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu-> uSint2Msr)288 && !MSR_GIM_HV_SINT_IS_MASKED(pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT]) 289 289 && MSR_GIM_HV_SIMP_IS_ENABLED(pHvCpu->uSimpMsr)) 290 290 { … … 483 483 return VINF_SUCCESS; 484 484 485 case MSR_GIM_HV_SINT2: 485 case MSR_GIM_HV_SINT0: case MSR_GIM_HV_SINT1: case MSR_GIM_HV_SINT2: case MSR_GIM_HV_SINT3: 486 case MSR_GIM_HV_SINT4: case MSR_GIM_HV_SINT5: case MSR_GIM_HV_SINT6: case MSR_GIM_HV_SINT7: 487 case MSR_GIM_HV_SINT8: case MSR_GIM_HV_SINT9: case MSR_GIM_HV_SINT10: case MSR_GIM_HV_SINT11: 488 case MSR_GIM_HV_SINT12: case MSR_GIM_HV_SINT13: case MSR_GIM_HV_SINT14: case MSR_GIM_HV_SINT15: 486 489 { 487 490 PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu; 488 *puValue = pHvCpu-> uSint2Msr;491 *puValue = pHvCpu->auSintXMsr[idMsr - MSR_GIM_HV_SINT0]; 489 492 return VINF_SUCCESS; 490 493 } … … 496 499 return VINF_SUCCESS; 497 500 } 501 502 case MSR_GIM_HV_SVERSION: 503 *puValue = GIM_HV_SVERSION; 504 return VINF_SUCCESS; 498 505 499 506 case MSR_GIM_HV_RESET: … … 590 597 { 591 598 gimR3HvDisableHypercallPage(pVM); 592 pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE _BIT;599 pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE; 593 600 LogRel(("GIM: HyperV: Hypercall page disabled via Guest OS ID MSR\n")); 594 601 } … … 642 649 * see @bugref{7270#c116}. */ 643 650 /* First, update all but the hypercall page enable bit. */ 644 pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE _BIT);651 pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_PAGE_ENABLE); 645 652 646 653 /* Hypercall page can only be enabled when the guest has enabled hypercalls. */ 647 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT);654 bool fEnable = MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(uRawValue); 648 655 if ( fEnable 649 656 && !gimHvAreHypercallsEnabled(pVCpu)) … … 679 686 #else /* IN_RING3 */ 680 687 /* First, update all but the TSC page enable bit. */ 681 pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE _BIT);688 pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE); 682 689 683 690 /* Is the guest disabling the TSC page? */ 684 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);691 bool fEnable = MSR_GIM_HV_REF_TSC_IS_ENABLED(uRawValue); 685 692 if (!fEnable) 686 693 { … … 709 716 #else /* IN_RING3 */ 710 717 PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu; 711 /* First, update all but the APIC-assist page enable bit. */ 712 pHvCpu->uApicAssistPageMsr = (uRawValue & ~MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT); 713 714 /* Is the guest disabling the APIC-assist page? */ 715 bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT); 716 if (!fEnable) 717 { 718 gimR3HvDisableApicAssistPage(pVM); 719 pHvCpu->uApicAssistPageMsr = uRawValue; 720 return VINF_SUCCESS; 721 } 722 723 /* Enable the APIC-assist page. */ 724 RTGCPHYS GCPhysApicAssist = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT; 725 int rc = gimR3HvEnableApicAssistPage(pVM, GCPhysApicAssist); 726 if (RT_SUCCESS(rc)) 727 { 728 pHvCpu->uApicAssistPageMsr = uRawValue; 729 return VINF_SUCCESS; 730 } 718 pHvCpu->uApicAssistPageMsr = uRawValue; 719 720 if (MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(uRawValue)) 721 { 722 RTGCPHYS GCPhysApicAssistPage = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT; 723 if (PGMPhysIsGCPhysNormal(pVM, GCPhysApicAssistPage)) 724 { 725 int rc = gimR3HvEnableApicAssistPage(pVCpu, GCPhysApicAssistPage); 726 if (RT_SUCCESS(rc)) 727 { 728 pHvCpu->uApicAssistPageMsr = uRawValue; 729 return VINF_SUCCESS; 730 } 731 } 732 else 733 { 734 LogRelMax(5, ("GIM: HyperV%u: APIC-assist page address %#RGp invalid!\n", pVCpu->idCpu, 735 GCPhysApicAssistPage)); 736 } 737 } 738 else 739 gimR3HvDisableApicAssistPage(pVCpu); 731 740 732 741 return VERR_CPUM_RAISE_GP_0; … … 739 748 return VINF_CPUM_R3_MSR_WRITE; 740 749 #else 741 if (MSR_GIM_HV_RESET_IS_ SET(uRawValue))750 if (MSR_GIM_HV_RESET_IS_ENABLED(uRawValue)) 742 751 { 743 752 LogRel(("GIM: HyperV: Reset initiated through MSR\n")); … … 755 764 return VINF_CPUM_R3_MSR_WRITE; 756 765 #else 757 if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY _BIT)766 if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY) 758 767 { 759 768 LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n", … … 851 860 if ( RT_SUCCESS(rc) 852 861 && cbWrite == cbWritten) 853 pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS _BIT;862 pHv->uDbgStatusMsr = MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS; 854 863 else 855 864 pHv->uDbgStatusMsr = 0; … … 882 891 { 883 892 pHv->uDbgStatusMsr = ((uint16_t)cbReallyRead) << 16; 884 pHv->uDbgStatusMsr |= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS _BIT;893 pHv->uDbgStatusMsr |= MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS; 885 894 } 886 895 else … … 907 916 return VINF_CPUM_R3_MSR_WRITE; 908 917 #else 909 PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;910 uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);918 PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu; 919 uint8_t uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue); 911 920 if ( !MSR_GIM_HV_SINT_IS_MASKED(uRawValue) 912 && uVector < 16)913 { 914 LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2 , uVector=%u -> #GP(0)\n", uVector));921 && uVector < GIM_HV_SINT_VECTOR_VALID_MIN) 922 { 923 LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2 (VMBUS_MSG_SINT), uVector=%u -> #GP(0)\n", uVector)); 915 924 return VERR_CPUM_RAISE_GP_0; 916 925 } 917 926 918 pHvCpu-> uSint2Msr= uRawValue;927 pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT] = uRawValue; 919 928 if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue)) 920 LogRel(("GIM: HyperV: Masked SINT2 \n"));929 LogRel(("GIM: HyperV: Masked SINT2 (VMBUS_MSG_SINT)\n")); 921 930 else 922 LogRel(("GIM: HyperV: Unmasked SINT2, uVector=%u\n", uVector)); 923 return VINF_SUCCESS; 924 #endif 931 LogRel(("GIM: HyperV: Unmasked SINT2 (VMBUS_MSG_SINT), uVector=%u\n", uVector)); 932 return VINF_SUCCESS; 933 #endif 934 } 935 936 case MSR_GIM_HV_SIEFP: 937 { 938 #ifndef IN_RING3 939 return VINF_CPUM_R3_MSR_WRITE; 940 #else 941 PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu; 942 pHvCpu->uSiefpMsr = uRawValue; 943 if (MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(uRawValue)) 944 { 945 RTGCPHYS GCPhysSiefPage = MSR_GIM_HV_SIEF_GUEST_PFN(uRawValue) << PAGE_SHIFT; 946 if (PGMPhysIsGCPhysNormal(pVM, GCPhysSiefPage)) 947 { 948 int rc = gimR3HvEnableSiefPage(pVCpu, GCPhysSiefPage); 949 if (RT_SUCCESS(rc)) 950 { 951 /** @todo SIEF setup. */ 952 return VINF_SUCCESS; 953 } 954 } 955 else 956 LogRelMax(5, ("GIM: HyperV%u: SIEF page address %#RGp invalid!\n", pVCpu->idCpu, GCPhysSiefPage)); 957 } 958 else 959 gimR3HvDisableSiefPage(pVCpu); 960 961 return VERR_CPUM_RAISE_GP_0; 962 #endif 963 break; 925 964 } 926 965 -
trunk/src/VBox/VMM/VMMR3/GIMHv.cpp
r62359 r62417 436 436 */ 437 437 if (pHv->uMiscFeat & GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS) 438 pHv->uCrashCtlMsr = MSR_GIM_HV_CRASH_CTL_NOTIFY _BIT;438 pHv->uCrashCtlMsr = MSR_GIM_HV_CRASH_CTL_NOTIFY; 439 439 for (VMCPUID i = 0; i < pVM->cCpus; i++) 440 pVM->aCpus[i].gim.s.u.HvCpu.uSint2Msr = MSR_GIM_HV_SINT_MASKED_BIT; 440 { 441 PGIMHVCPU pHvCpu = &pVM->aCpus[i].gim.s.u.HvCpu; 442 for (size_t idxSintMsr = 0; idxSintMsr < RT_ELEMENTS(pHvCpu->auSintXMsr); idxSintMsr++) 443 pHvCpu->auSintXMsr[idxSintMsr] = MSR_GIM_HV_SINT_MASKED; 444 } 441 445 442 446 /* … … 554 558 for (VMCPUID i = 0; i < pVM->cCpus; i++) 555 559 { 556 PVMCPU pVCpu = &pVM->aCpus[i]; 557 pVCpu->gim.s.u.HvCpu.uSint2Msr = MSR_GIM_HV_SINT_MASKED_BIT; 558 pVCpu->gim.s.u.HvCpu.uSimpMsr = 0; 559 pVCpu->gim.s.u.HvCpu.uApicAssistPageMsr = 0; 560 PGIMHVCPU pHvCpu = &pVM->aCpus[i].gim.s.u.HvCpu; 561 pHvCpu->uSimpMsr = 0; 562 pHvCpu->uSiefpMsr = 0; 563 pHvCpu->uApicAssistPageMsr = 0; 564 for (size_t idxSintMsr = 0; idxSintMsr < RT_ELEMENTS(pHvCpu->auSintXMsr); idxSintMsr++) 565 pHvCpu->auSintXMsr[idxSintMsr] = MSR_GIM_HV_SINT_MASKED; 560 566 } 561 567 } … … 726 732 PGIMHVCPU pHvCpu = &pVM->aCpus[i].gim.s.u.HvCpu; 727 733 SSMR3PutU64(pSSM, pHvCpu->uSimpMsr); 728 SSMR3PutU64(pSSM, pHvCpu-> uSint2Msr);734 SSMR3PutU64(pSSM, pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT]); 729 735 } 730 736 … … 856 862 PGIMHVCPU pHvCpu = &pVM->aCpus[i].gim.s.u.HvCpu; 857 863 SSMR3GetU64(pSSM, &pHvCpu->uSimpMsr); 858 SSMR3GetU64(pSSM, &pHvCpu-> uSint2Msr);864 SSMR3GetU64(pSSM, &pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT]); 859 865 } 860 866 … … 873 879 * 874 880 * @returns VBox status code. 875 * @param pV M The cross context VMstructure.881 * @param pVCpu The cross context virtual CPU structure. 876 882 * @param GCPhysApicAssistPage Where to map the APIC-assist page. 877 883 */ 878 VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVM pVM, RTGCPHYS GCPhysApicAssistPage) 879 { 884 VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysApicAssistPage) 885 { 886 PVM pVM = pVCpu->CTX_SUFF(pVM); 880 887 PPDMDEVINSR3 pDevIns = pVM->gim.s.pDevInsR3; 881 888 AssertPtrReturn(pDevIns, VERR_GIM_DEVICE_NOT_REGISTERED); … … 886 893 /** @todo this is buggy when large pages are used due to a PGM limitation, see 887 894 * @bugref{7532}. Instead of the overlay style mapping, we just 888 * 895 * rewrite guest memory directly. */ 889 896 size_t const cbApicAssistPage = PAGE_SIZE; 890 897 void *pvApicAssist = RTMemAllocZ(cbApicAssistPage); … … 895 902 { 896 903 /** @todo Inform APIC. */ 897 LogRel(("GIM: HyperV : Enabled APIC-assist page at %#RGp\n", GCPhysApicAssistPage));904 LogRel(("GIM: HyperV%u: Enabled APIC-assist page at %#RGp\n", pVCpu->idCpu, GCPhysApicAssistPage)); 898 905 } 899 906 else 900 907 { 901 LogRelFunc(("GIM: HyperV : PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", rc));908 LogRelFunc(("GIM: HyperV%u: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", pVCpu->idCpu, rc)); 902 909 rc = VERR_GIM_OPERATION_FAILED; 903 910 } … … 907 914 } 908 915 909 LogRelFunc(("GIM: HyperV : Failed to alloc %u bytes\n", cbApicAssistPage));916 LogRelFunc(("GIM: HyperV%u: Failed to alloc %u bytes\n", pVCpu->idCpu, cbApicAssistPage)); 910 917 return VERR_NO_MEMORY; 911 918 } … … 916 923 * 917 924 * @returns VBox status code. 918 * @param pV M The cross context VMstructure.919 */ 920 VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVM pVM)921 { 922 LogRel(("GIM: HyperV : Disabled APIC-assist page\n"));925 * @param pVCpu The cross context virtual CPU structure. 926 */ 927 VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu) 928 { 929 LogRel(("GIM: HyperV%u: Disabled APIC-assist page\n", pVCpu->idCpu)); 923 930 /** @todo inform APIC */ 931 return VINF_SUCCESS; 932 } 933 934 935 /** 936 * Enables the Hyper-V SIEF page. 937 * 938 * @returns VBox status code. 939 * @param pVCpu The cross context virtual CPU structure. 940 * @param GCPhysSiefPage Where to map the SIEF page. 941 */ 942 VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage) 943 { 944 PVM pVM = pVCpu->CTX_SUFF(pVM); 945 PPDMDEVINSR3 pDevIns = pVM->gim.s.pDevInsR3; 946 AssertPtrReturn(pDevIns, VERR_GIM_DEVICE_NOT_REGISTERED); 947 948 /* 949 * Map the SIEF page at the specified address. 950 */ 951 /** @todo this is buggy when large pages are used due to a PGM limitation, see 952 * @bugref{7532}. Instead of the overlay style mapping, we just 953 * rewrite guest memory directly. */ 954 size_t const cbSiefPage = PAGE_SIZE; 955 void *pvSiefPage = RTMemAllocZ(cbSiefPage); 956 if (RT_LIKELY(pvSiefPage)) 957 { 958 int rc = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSiefPage, pvSiefPage, cbSiefPage); 959 if (RT_SUCCESS(rc)) 960 { 961 /** @todo SIEF setup. */ 962 LogRel(("GIM: HyperV%u: Enabled SIEF page at %#RGp\n", pVCpu->idCpu, GCPhysSiefPage)); 963 } 964 else 965 { 966 LogRelFunc(("GIM: HyperV%u: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", pVCpu->idCpu, rc)); 967 rc = VERR_GIM_OPERATION_FAILED; 968 } 969 970 RTMemFree(pvSiefPage); 971 return rc; 972 } 973 974 LogRelFunc(("GIM: HyperV%u: Failed to alloc %u bytes\n", pVCpu->idCpu, cbSiefPage)); 975 return VERR_NO_MEMORY; 976 } 977 978 979 /** 980 * Disables the Hyper-V SIEF page. 981 * 982 * @returns VBox status code. 983 * @param pVCpu The cross context virtual CPU structure. 984 */ 985 VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu) 986 { 987 LogRel(("GIM: HyperV%u: Disabled APIC-assist page\n", pVCpu->idCpu)); 988 /** @todo SIEF teardown. */ 924 989 return VINF_SUCCESS; 925 990 } … … 966 1031 /** @todo this is buggy when large pages are used due to a PGM limitation, see 967 1032 * @bugref{7532}. Instead of the overlay style mapping, we just 968 * 1033 * rewrite guest memory directly. */ 969 1034 #if 0 970 1035 rc = gimR3Mmio2Map(pVM, pRegion, GCPhysTscPage); … … 1043 1108 1044 1109 /** 1110 * Enables the Hyper-V SIM page. 1111 * 1112 * @returns VBox status code. 1113 * @param pVCpu The cross context virtual CPU structure. 1114 * @param GCPhysSimPage Where to map the SIM page. 1115 */ 1116 VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage) 1117 { 1118 PVM pVM = pVCpu->CTX_SUFF(pVM); 1119 PPDMDEVINSR3 pDevIns = pVM->gim.s.pDevInsR3; 1120 AssertPtrReturn(pDevIns, VERR_GIM_DEVICE_NOT_REGISTERED); 1121 1122 /* 1123 * Map the SIMP page at the specified address. 1124 */ 1125 /** @todo this is buggy when large pages are used due to a PGM limitation, see 1126 * @bugref{7532}. Instead of the overlay style mapping, we just 1127 * rewrite guest memory directly. */ 1128 size_t const cbSimPage = PAGE_SIZE; 1129 void *pvSimPage = RTMemAllocZ(cbSimPage); 1130 if (RT_LIKELY(pvSimPage)) 1131 { 1132 int rc = PGMPhysSimpleWriteGCPhys(pVM, GCPhysSimPage, pvSimPage, cbSimPage); 1133 if (RT_SUCCESS(rc)) 1134 { 1135 /** @todo SIM setup. */ 1136 LogRel(("GIM: HyperV%u: Enabled SIM page at %#RGp\n", pVCpu->idCpu, GCPhysSimPage)); 1137 } 1138 else 1139 { 1140 LogRelFunc(("GIM: HyperV%u: PGMPhysSimpleWriteGCPhys failed. rc=%Rrc\n", pVCpu->idCpu, rc)); 1141 rc = VERR_GIM_OPERATION_FAILED; 1142 } 1143 1144 RTMemFree(pvSimPage); 1145 return rc; 1146 } 1147 1148 LogRelFunc(("GIM: HyperV%u: Failed to alloc %u bytes\n", pVCpu->idCpu, cbSimPage)); 1149 return VERR_NO_MEMORY; 1150 } 1151 1152 1153 /** 1154 * Disables the Hyper-V SIM page. 1155 * 1156 * @returns VBox status code. 1157 * @param pVCpu The cross context virtual CPU structure. 1158 */ 1159 VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu) 1160 { 1161 LogRel(("GIM: HyperV%u: Disabled SIM page\n", pVCpu->idCpu)); 1162 /** @todo SIM teardown. */ 1163 return VINF_SUCCESS; 1164 } 1165 1166 1167 1168 /** 1045 1169 * Disables the Hyper-V TSC page. 1046 1170 * … … 1128 1252 /** @todo this is buggy when large pages are used due to a PGM limitation, see 1129 1253 * @bugref{7532}. Instead of the overlay style mapping, we just 1130 * 1254 * rewrite guest memory directly. */ 1131 1255 #if 0 1132 1256 int rc = gimR3Mmio2Map(pVM, pRegion, GCPhysHypercallPage); -
trunk/src/VBox/VMM/include/GIMHvInternal.h
r62357 r62417 401 401 * @{ 402 402 */ 403 /** The hypercall enable bit. */404 #define MSR_GIM_HV_RESET_ BITRT_BIT_64(0)405 /** Whether the hypercall-page is enabled or not. */406 #define MSR_GIM_HV_RESET_IS_ SET(a) RT_BOOL((a) & MSR_GIM_HV_RESET_BIT)403 /** The reset enable mask. */ 404 #define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0) 405 /** Whether the reset MSR is enabled. */ 406 #define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE) 407 407 /** @} */ 408 408 … … 412 412 /** Guest-physical page frame number of the hypercall-page. */ 413 413 #define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12) 414 /** The hypercall enable bit. */415 #define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE _BITRT_BIT_64(0)414 /** The hypercall enable mask. */ 415 #define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0) 416 416 /** Whether the hypercall-page is enabled or not. */ 417 #define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE _BIT)417 #define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE) 418 418 /** @} */ 419 419 … … 423 423 /** Guest-physical page frame number of the TSC-page. */ 424 424 #define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12) 425 /** The TSC-page enable bit. */426 #define MSR_GIM_HV_REF_TSC_ENABLE _BITRT_BIT_64(0)425 /** The TSC-page enable mask. */ 426 #define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0) 427 427 /** Whether the TSC-page is enabled or not. */ 428 #define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE _BIT)428 #define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE) 429 429 /** @} */ 430 430 … … 432 432 * @{ 433 433 */ 434 /** The Crash Notify bit. */435 #define MSR_GIM_HV_CRASH_CTL_NOTIFY _BITRT_BIT_64(63)434 /** The Crash Control notify mask. */ 435 #define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63) 436 436 /** @} */ 437 437 … … 460 460 /** Guest-physical page frame number of the APIC-assist page. */ 461 461 #define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12) 462 /** The hypercall enable bit. */ 463 #define MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT RT_BIT_64(0) 464 /** Whether the hypercall-page is enabled or not. */ 465 #define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT) 462 /** The APIC-assist page enable mask. */ 463 #define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0) 464 /** Whether the APIC-assist page is enabled or not. */ 465 #define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE) 466 /** @} */ 467 468 /** @name Hyper-V MSR - Synthetic Interrupt Event Flags page 469 * (MSR_GIM_HV_SIEFP). 470 * @{ 471 */ 472 /** Guest-physical page frame number of the APIC-assist page. */ 473 #define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12) 474 /** The SIEF enable mask. */ 475 #define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0) 476 /** Whether the SIEF page is enabled or not. */ 477 #define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE) 466 478 /** @} */ 467 479 … … 699 711 */ 700 712 /** Debug send buffer operation success. */ 701 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS _BITRT_BIT_64(0)713 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0) 702 714 /** Debug receive buffer operation success. */ 703 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS _BITRT_BIT_64(2)715 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2) 704 716 /** Debug connection was reset. */ 705 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET _BITRT_BIT_64(3)717 #define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3) 706 718 /** @} */ 707 719 … … 710 722 * @{ 711 723 */ 712 /** The interrupt masked bit. */713 #define MSR_GIM_HV_SINT_MASKED _BITRT_BIT_64(16)724 /** The interrupt masked mask. */ 725 #define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16) 714 726 /** Whether the interrupt source is masked. */ 715 #define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED _BIT)727 #define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED) 716 728 /** Interrupt vector. */ 717 729 #define MSR_GIM_HV_SINT_VECTOR(a) ((a) & UINT64_C(0xff)) … … 722 734 * @{ 723 735 */ 724 /** The SIMP enable d bit. */725 #define MSR_GIM_HV_SIMP_ENABLE D_BITRT_BIT_64(0)736 /** The SIMP enable mask. */ 737 #define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0) 726 738 /** Whether the SIMP is enabled. */ 727 #define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE D_BIT)739 #define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE) 728 740 /** The SIMP guest-physical address. */ 729 741 #define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000)) … … 765 777 /** VMBus connection ID. */ 766 778 #define GIM_HV_VMBUS_MSG_CONNECTION_ID 1 767 /** VMBus synthetic interrupt source. */ 779 /** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux 780 * sources). */ 768 781 #define GIM_HV_VMBUS_MSG_SINT 2 769 782 /** @} */ 770 783 784 /** @name SynIC. 785 * Synthetic Interrupt Controller definitions. 786 */ 787 /** SynIC version register. */ 788 #define GIM_HV_SVERSION 1 789 /** Number of synthetic interrupt sources. */ 790 #define GIM_HV_SINT_COUNT 16 791 /** Lowest valid vector for synthetic interrupt. */ 792 #define GIM_HV_SINT_VECTOR_VALID_MIN 16 793 /** Highest valid vector for synthetic interrupt. */ 794 #define GIM_HV_SINT_VECTOR_VALID_MAX 255 795 /** @} */ 771 796 772 797 /** @name Hyper-V synthetic interrupt message type. … … 1120 1145 /** Synthetic interrupt message page MSR. */ 1121 1146 uint64_t uSimpMsr; 1122 /** Interrupt source 2 MSR. */ 1123 uint64_t uSint2Msr; 1147 /** Interrupt source MSRs. */ 1148 uint64_t auSintXMsr[GIM_HV_SINT_COUNT]; 1149 /** Synethtic interrupt events flag page MSR. */ 1150 uint64_t uSiefpMsr; 1124 1151 /** APIC-assist page MSR. */ 1125 1152 uint64_t uApicAssistPageMsr; … … 1151 1178 VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup); 1152 1179 1153 VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVM pVM); 1154 VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVM pVM, RTGCPHYS GCPhysTscPage); 1180 VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu); 1181 VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage); 1182 VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage); 1183 VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu); 1184 VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu); 1185 VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage); 1155 1186 VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM); 1156 1187 VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
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