Changeset 62540 in vbox for trunk/src/VBox

Timestamp:

Jul 25, 2016 9:31:02 AM (8 years ago)

Author:

vboxsync

Message:

VMM/GIM/HyperV: Synthetic interrupt controller bits.

File:

• trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp

@@ -909 +909 @@
         }
 
-        case MSR_GIM_HV_SINT2:
-        {
-            if (!pHv->fDbgEnabled)
+        case MSR_GIM_HV_SINT0:    case MSR_GIM_HV_SINT1:    case MSR_GIM_HV_SINT2:    case MSR_GIM_HV_SINT3:
+        case MSR_GIM_HV_SINT4:    case MSR_GIM_HV_SINT5:    case MSR_GIM_HV_SINT6:    case MSR_GIM_HV_SINT7:
+        case MSR_GIM_HV_SINT8:    case MSR_GIM_HV_SINT9:    case MSR_GIM_HV_SINT10:   case MSR_GIM_HV_SINT11:
+        case MSR_GIM_HV_SINT12:   case MSR_GIM_HV_SINT13:   case MSR_GIM_HV_SINT14:   case MSR_GIM_HV_SINT15:
+        {
+#ifndef IN_RING3
+            /** @todo make this RZ later? */
+            return VINF_CPUM_R3_MSR_WRITE;
+#else
+            PGIMHVCPU    pHvCpu     = &pVCpu->gim.s.u.HvCpu;
+            uint8_t      uVector    = MSR_GIM_HV_SINT_VECTOR(uRawValue);
+            bool const   fVMBusMsg  = RT_BOOL(idMsr == GIM_HV_VMBUS_MSG_SINT);
+            size_t const idxSintMsr = idMsr - MSR_GIM_HV_SINT0;
+            const char  *pszDesc    = fVMBusMsg ? "VMBus Message" : "Generic";
+            if (uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
+            {
+                LogRel(("GIM: HyperV%u: Programmed an invalid vector in SINT%u (%s), uVector=%u -> #GP(0)\n", pVCpu->idCpu,
+                        idxSintMsr, pszDesc, uVector));
                 return VERR_CPUM_RAISE_GP_0;
-#ifndef IN_RING3
-            return VINF_CPUM_R3_MSR_WRITE;
-#else
-            PGIMHVCPU pHvCpu  = &pVCpu->gim.s.u.HvCpu;
-            uint8_t   uVector = MSR_GIM_HV_SINT_VECTOR(uRawValue);
-            if (  !MSR_GIM_HV_SINT_IS_MASKED(uRawValue)
-                && uVector < GIM_HV_SINT_VECTOR_VALID_MIN)
-            {
-                LogRel(("GIM: HyperV: Programmed an invalid vector in SINT2 (VMBUS_MSG_SINT), uVector=%u -> #GP(0)\n", uVector));
-                return VERR_CPUM_RAISE_GP_0;
-            }
-
-            pHvCpu->auSintXMsr[GIM_HV_VMBUS_MSG_SINT] = uRawValue;
-            if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
-                LogRel(("GIM: HyperV: Masked SINT2 (VMBUS_MSG_SINT)\n"));
-            else
-                LogRel(("GIM: HyperV: Unmasked SINT2 (VMBUS_MSG_SINT), uVector=%u\n", uVector));
+            }
+
+            pHvCpu->auSintXMsr[idxSintMsr] = uRawValue;
+            if (fVMBusMsg)
+            {
+                if (MSR_GIM_HV_SINT_IS_MASKED(uRawValue))
+                    LogRel(("GIM: HyperV%u: Masked SINT%u (%s)\n", pVCpu->idCpu, idxSintMsr, pszDesc));
+                else
+                    LogRel(("GIM: HyperV%u: Unmasked SINT%u (%s), uVector=%u\n", pVCpu->idCpu, idxSintMsr, pszDesc, uVector));
+            }
             return VINF_SUCCESS;
 #endif