- Timestamp:
- Jul 28, 2016 11:23:36 AM (8 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r62514 r62618 1486 1486 { 1487 1487 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); 1488 int rc = VINF_SUCCESS;1488 RT_NOREF_PV(pvUser); 1489 1489 1490 1490 /* Ignore non-dword accesses. */ … … 1515 1515 break; 1516 1516 } 1517 return rc; 1517 1518 return VINF_SUCCESS; 1518 1519 } 1519 1520 … … 1532 1533 { 1533 1534 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE); 1534 int rc = VINF_SUCCESS;1535 RT_NOREF_PV(pvUser); 1535 1536 1536 1537 /* Ignore non-dword accesses. */ … … 1565 1566 break; 1566 1567 } 1567 return rc;1568 return VINF_SUCCESS; 1568 1569 } 1569 1570 -
trunk/src/VBox/Devices/Network/DevE1000Phy.cpp
r62511 r62618 174 174 static void Phy::regWriteForbidden(PPHY pPhy, uint32_t index, uint16_t u16Value) 175 175 { 176 RT_NOREF_PV(pPhy); RT_NOREF_PV(index); RT_NOREF_PV(u16Value); 176 177 PhyLog(("PHY#%d At %02d write attempted to read-only '%s'\n", 177 178 pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName)); … … 189 190 static uint16_t Phy::regReadUnimplemented(PPHY pPhy, uint32_t index) 190 191 { 192 RT_NOREF_PV(pPhy); RT_NOREF_PV(index); 191 193 PhyLog(("PHY#%d At %02d read attempted from unimplemented '%s'\n", 192 194 pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName)); … … 204 206 static void Phy::regWriteUnimplemented(PPHY pPhy, uint32_t index, uint16_t u16Value) 205 207 { 208 RT_NOREF_PV(pPhy); RT_NOREF_PV(index); RT_NOREF_PV(u16Value); 206 209 PhyLog(("PHY#%d At %02d write attempted to unimplemented '%s'\n", 207 210 pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName)); … … 441 444 static uint16_t Phy::regReadPSTATUS(PPHY pPhy, uint32_t index) 442 445 { 446 RT_NOREF_PV(pPhy); RT_NOREF_PV(index); 447 443 448 /* Read latched value */ 444 449 uint16_t u16 = REG(PSTATUS); … … 459 464 static uint16_t Phy::regReadGSTATUS(PPHY pPhy, uint32_t index) 460 465 { 466 RT_NOREF_PV(pPhy); RT_NOREF_PV(index); 467 461 468 /* 462 469 * - Link partner is capable of 1000BASE-T half duplex -
trunk/src/VBox/Devices/Network/DevVirtioNet.cpp
r62511 r62618 292 292 DECLINLINE(int) vnetCsRxEnter(PVNETSTATE pThis, int rcBusy) 293 293 { 294 RT_NOREF_PV(pThis); 295 RT_NOREF_PV(rcBusy); 294 296 // STAM_PROFILE_START(&pThis->CTXSUFF(StatCsRx), a); 295 297 // int rc = PDMCritSectEnter(&pThis->csRx, rcBusy); … … 301 303 DECLINLINE(void) vnetCsRxLeave(PVNETSTATE pThis) 302 304 { 305 RT_NOREF_PV(pThis); 303 306 // PDMCritSectLeave(&pThis->csRx); 304 307 } … … 367 370 static DECLCALLBACK(uint32_t) vnetIoCb_GetHostFeatures(void *pvState) 368 371 { 372 RT_NOREF_PV(pvState); 373 369 374 /* We support: 370 375 * - Host-provided MAC address … … 398 403 static DECLCALLBACK(uint32_t) vnetIoCb_GetHostMinimalFeatures(void *pvState) 399 404 { 405 RT_NOREF_PV(pvState); 400 406 return VNET_F_MAC; 401 407 } -
trunk/src/VBox/Devices/Parallel/DrvHostParallel.cpp
r62510 r62618 172 172 /** 173 173 * R0 mode function to write byte value to data port. 174 * 174 175 * @returns VBox status code. 175 176 * @param pDrvIns Driver instance. … … 186 187 187 188 /** 188 * R0 mode function to write byte value to parallel port control 189 * register.189 * R0 mode function to write byte value to parallel port control register. 190 * 190 191 * @returns VBox status code. 191 192 * @param pDrvIns Driver instance. … … 201 202 202 203 /** 203 * R0 mode function to ready byte value from the parallel port 204 * data register204 * R0 mode function to ready byte value from the parallel port data register. 205 * 205 206 * @returns VBox status code. 206 207 * @param pDrvIns Driver instance. 207 * @param u64Arg Not used. 208 */ 209 static int drvR0HostParallelReqRead(PPDMDRVINS pDrvIns, uint64_t u64Arg) 210 { 211 uint8_t u8Data; 208 */ 209 static int drvR0HostParallelReqRead(PPDMDRVINS pDrvIns) 210 { 212 211 PDRVHOSTPARALLEL pThis = PDMINS_2_DATA(pDrvIns, PDRVHOSTPARALLEL); 213 u 8Data = ASMInU8(pThis->u32LptAddr);212 uint8_t u8Data = ASMInU8(pThis->u32LptAddr); 214 213 LogFlowFunc(("read from data port=%#x val=%#x\n", pThis->u32LptAddr, u8Data)); 215 214 pThis->u8ReadIn = u8Data; … … 218 217 219 218 /** 220 * R0 mode function to ready byte value from the parallel port 221 * control register.219 * R0 mode function to ready byte value from the parallel port control register. 220 * 222 221 * @returns VBox status code. 223 222 * @param pDrvIns Driver instance. 224 * @param u64Arg Not used. 225 */ 226 static int drvR0HostParallelReqReadControl(PPDMDRVINS pDrvIns, uint64_t u64Arg) 227 { 228 uint8_t u8Data; 223 */ 224 static int drvR0HostParallelReqReadControl(PPDMDRVINS pDrvIns) 225 { 229 226 PDRVHOSTPARALLEL pThis = PDMINS_2_DATA(pDrvIns, PDRVHOSTPARALLEL); 230 u 8Data = ASMInU8(pThis->u32LptAddrControl);227 uint8_t u8Data = ASMInU8(pThis->u32LptAddrControl); 231 228 LogFlowFunc(("read from ctrl port=%#x val=%#x\n", pThis->u32LptAddr, u8Data)); 232 229 pThis->u8ReadInControl = u8Data; … … 235 232 236 233 /** 237 * R0 mode function to ready byte value from the parallel port 238 * status register.234 * R0 mode function to ready byte value from the parallel port status register. 235 * 239 236 * @returns VBox status code. 240 237 * @param pDrvIns Driver instance. 241 * @param u64Arg Not used. 242 */ 243 static int drvR0HostParallelReqReadStatus(PPDMDRVINS pDrvIns, uint64_t u64Arg) 244 { 245 uint8_t u8Data; 238 */ 239 static int drvR0HostParallelReqReadStatus(PPDMDRVINS pDrvIns) 240 { 246 241 PDRVHOSTPARALLEL pThis = PDMINS_2_DATA(pDrvIns, PDRVHOSTPARALLEL); 247 u 8Data = ASMInU8(pThis->u32LptAddrStatus);242 uint8_t u8Data = ASMInU8(pThis->u32LptAddrStatus); 248 243 LogFlowFunc(("read from status port=%#x val=%#x\n", pThis->u32LptAddr, u8Data)); 249 244 pThis->u8ReadInStatus = u8Data; … … 254 249 * R0 mode function to set the direction of parallel port - 255 250 * operate in bidirectional mode or single direction. 251 * 256 252 * @returns VBox status code. 257 253 * @param pDrvIns Driver instance. … … 291 287 { 292 288 case DRVHOSTPARALLELR0OP_READ: 293 rc = drvR0HostParallelReqRead(pDrvIns , u64Arg);289 rc = drvR0HostParallelReqRead(pDrvIns); 294 290 break; 295 291 case DRVHOSTPARALLELR0OP_READSTATUS: 296 rc = drvR0HostParallelReqReadStatus(pDrvIns , u64Arg);292 rc = drvR0HostParallelReqReadStatus(pDrvIns); 297 293 break; 298 294 case DRVHOSTPARALLELR0OP_READCONTROL: 299 rc = drvR0HostParallelReqReadControl(pDrvIns , u64Arg);295 rc = drvR0HostParallelReqReadControl(pDrvIns); 300 296 break; 301 297 case DRVHOSTPARALLELR0OP_WRITE: -
trunk/src/VBox/Devices/Storage/DevBusLogic.cpp
r62506 r62618 2408 2408 PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb) 2409 2409 { 2410 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb); 2411 2410 2412 /* the linux driver does not make use of the MMIO area. */ 2411 2413 AssertMsgFailed(("MMIO Read\n")); … … 2426 2428 PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb) 2427 2429 { 2430 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb); 2431 2428 2432 /* the linux driver does not make use of the MMIO area. */ 2429 2433 AssertMsgFailed(("MMIO Write\n")); … … 2446 2450 PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC); 2447 2451 unsigned iRegister = Port % 4; 2452 RT_NOREF_PV(pvUser); RT_NOREF_PV(cb); 2448 2453 2449 2454 Assert(cb == 1); -
trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp
r62506 r62618 1688 1688 uint32_t offReg = Port - pThis->IOPortBase; 1689 1689 int rc; 1690 RT_NOREF_PV(pvUser); 1690 1691 1691 1692 if (!(offReg & 3)) … … 1711 1712 PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI); 1712 1713 uint32_t offReg = Port - pThis->IOPortBase; 1714 RT_NOREF_PV(pvUser); 1715 RT_NOREF_PV(cb); 1713 1716 1714 1717 int rc = lsilogicRegisterRead(pThis, offReg & ~(uint32_t)3, pu32); … … 1728 1731 uint32_t u32; 1729 1732 int rc; 1733 RT_NOREF_PV(pvUser); 1730 1734 1731 1735 /* See comments in lsilogicR3Map regarding size and alignment. */ … … 1761 1765 uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase; 1762 1766 Assert(!(offReg & 3)); Assert(cb == 4); 1767 RT_NOREF_PV(pvUser); 1763 1768 1764 1769 return lsilogicRegisterRead(pThis, offReg, (uint32_t *)pv); … … 1773 1778 #endif 1774 1779 1780 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb); 1775 1781 return VINF_SUCCESS; 1776 1782 } … … 1784 1790 #endif 1785 1791 1792 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pvUser); RT_NOREF_PV(GCPhysAddr); RT_NOREF_PV(pv); RT_NOREF_PV(cb); 1786 1793 return VINF_SUCCESS; 1787 1794 } -
trunk/src/VBox/Devices/VirtIO/Virtio.cpp
r62504 r62618 272 272 int vpciRaiseInterrupt(VPCISTATE *pState, int rcBusy, uint8_t u8IntCause) 273 273 { 274 RT_NOREF_PV(rcBusy); 274 275 // int rc = vpciCsEnter(pState, rcBusy); 275 276 // if (RT_UNLIKELY(rc != VINF_SUCCESS)) … … 327 328 int rc = VINF_SUCCESS; 328 329 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a); 330 RT_NOREF_PV(pvUser); 329 331 330 332 /* … … 425 427 bool fHasBecomeReady; 426 428 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a); 429 RT_NOREF_PV(pvUser); 427 430 428 431 Port -= pState->IOPortBase;
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