Index: /trunk/src/VBox/Devices/USB/DevOHCI.cpp
===================================================================
--- /trunk/src/VBox/Devices/USB/DevOHCI.cpp	(revision 62621)
+++ /trunk/src/VBox/Devices/USB/DevOHCI.cpp	(revision 62622)
@@ -4191,4 +4191,5 @@
 static int HcRevision_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF2(pThis, iReg);
     Log2(("HcRevision_r() -> 0x10\n"));
     *pu32Value = 0x10; /* OHCI revision 1.0, no emulation. */
@@ -4201,4 +4202,5 @@
 static int HcRevision_w(POHCI pThis, uint32_t iReg, uint32_t u32Value)
 {
+    RT_NOREF3(pThis, iReg, u32Value);
     Log2(("HcRevision_w(%#010x) - denied\n", u32Value));
     AssertMsgFailed(("Invalid operation!!! u32Value=%#010x\n", u32Value));
@@ -4211,4 +4213,5 @@
 static int HcControl_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF1(iReg);
     uint32_t ctl = pThis->ctl;
     Log2(("HcControl_r -> %#010x - CBSR=%d PLE=%d IE=%d CLE=%d BLE=%d HCFS=%#x IR=%d RWC=%d RWE=%d\n",
@@ -4224,4 +4227,6 @@
 static int HcControl_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
+
     /* log it. */
     uint32_t chg = pThis->ctl ^ val; NOREF(chg);
@@ -4295,4 +4300,5 @@
           status, status & 1, (status >> 1) & 1, (status >> 2) & 1, (status >> 3) & 1, (status >> 16) & 3));
     *pu32Value = status;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4303,4 +4309,6 @@
 static int HcCommandStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
+
     /* log */
     uint32_t chg = pThis->status ^ val; NOREF(chg);
@@ -4347,4 +4355,5 @@
           (val >> 6) & 1, (val >> 30) & 1));
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4355,4 +4364,6 @@
 static int HcInterruptStatus_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
+
     uint32_t res = pThis->intr_status & ~val;
     uint32_t chg = pThis->intr_status ^ res; NOREF(chg);
@@ -4395,4 +4406,5 @@
           (val >> 6) & 1, (val >> 30) & 1, (val >> 31) & 1));
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4403,4 +4415,5 @@
 static int HcInterruptEnable_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
     uint32_t res = pThis->intr | val;
     uint32_t chg = pThis->intr ^ res; NOREF(chg);
@@ -4445,4 +4458,5 @@
 
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4453,4 +4467,5 @@
 static int HcInterruptDisable_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
     uint32_t res = pThis->intr & ~val;
     uint32_t chg = pThis->intr ^ res; NOREF(chg);
@@ -4487,4 +4502,5 @@
     Log2(("HcHCCA_r() -> %#010x\n", pThis->hcca));
     *pu32Value = pThis->hcca;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4497,4 +4513,5 @@
     Log2(("HcHCCA_w(%#010x) - old=%#010x new=%#010x\n", Value, pThis->hcca, Value & OHCI_HCCA_MASK));
     pThis->hcca = Value & OHCI_HCCA_MASK;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4507,4 +4524,5 @@
     Log2(("HcPeriodCurrentED_r() -> %#010x\n", pThis->per_cur));
     *pu32Value = pThis->per_cur;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4520,4 +4538,5 @@
     AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
     pThis->per_cur = val & ~7;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4530,4 +4549,5 @@
     Log2(("HcControlHeadED_r() -> %#010x\n", pThis->ctrl_head));
     *pu32Value = pThis->ctrl_head;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4541,4 +4561,5 @@
     AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
     pThis->ctrl_head = val & ~7;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4551,4 +4572,5 @@
     Log2(("HcControlCurrentED_r() -> %#010x\n", pThis->ctrl_cur));
     *pu32Value = pThis->ctrl_cur;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4563,4 +4585,5 @@
     AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
     pThis->ctrl_cur = val & ~7;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4573,4 +4596,5 @@
     Log2(("HcBulkHeadED_r() -> %#010x\n", pThis->bulk_head));
     *pu32Value = pThis->bulk_head;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4584,4 +4608,5 @@
     AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
     pThis->bulk_head = val & ~7; /** @todo The ATI OHCI controller on my machine enforces 16-byte address alignment. */
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4594,4 +4619,5 @@
     Log2(("HcBulkCurrentED_r() -> %#010x\n", pThis->bulk_cur));
     *pu32Value = pThis->bulk_cur;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4606,4 +4632,5 @@
     AssertMsg(!(val & 7), ("Invalid alignment, val=%#010x\n", val));
     pThis->bulk_cur = val & ~7;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4617,4 +4644,5 @@
     Log2(("HcDoneHead_r() -> 0x%#08x\n", pThis->done));
     *pu32Value = pThis->done;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4625,4 +4653,5 @@
 static int HcDoneHead_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF3(pThis, iReg, val);
     Log2(("HcDoneHead_w(0x%#08x) - denied!!!\n", val));
     /*AssertMsgFailed(("Illegal operation!!! val=%#010x\n", val)); - OS/2 does this */
@@ -4640,4 +4669,5 @@
           val, val & 0x3fff, (val >> 16) & 0x7fff, val >> 31));
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4648,4 +4678,6 @@
 static int HcFmInterval_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
+
     /* log */
     uint32_t chg = val ^ ((pThis->fit << 31) | (pThis->fsmps << 16) | pThis->fi); NOREF(chg);
@@ -4673,4 +4705,5 @@
 static int HcFmRemaining_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF1(iReg);
     uint32_t Value = pThis->frt << 31;
     if ((pThis->ctl & OHCI_CTL_HCFS) == OHCI_USB_OPERATIONAL)
@@ -4699,4 +4732,5 @@
 static int HcFmRemaining_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF3(pThis, iReg, val);
     Log2(("HcFmRemaining_w(%#010x) - denied\n", val));
     AssertMsgFailed(("Invalid operation!!! val=%#010x\n", val));
@@ -4709,4 +4743,5 @@
 static int HcFmNumber_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF1(iReg);
     uint32_t val = (uint16_t)pThis->HcFmNumber;
     Log2(("HcFmNumber_r() -> %#010x - FN=%#x(%d) (32-bit=%#x(%d))\n", val, val, val, pThis->HcFmNumber, pThis->HcFmNumber));
@@ -4720,4 +4755,5 @@
 static int HcFmNumber_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF3(pThis, iReg, val);
     Log2(("HcFmNumber_w(%#010x) - denied\n", val));
     AssertMsgFailed(("Invalid operation!!! val=%#010x\n", val));
@@ -4731,4 +4767,5 @@
 static int HcPeriodicStart_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF1(iReg);
     Log2(("HcPeriodicStart_r() -> %#010x - PS=%d\n", pThis->pstart, pThis->pstart & 0x3fff));
     *pu32Value = pThis->pstart;
@@ -4742,4 +4779,5 @@
 static int HcPeriodicStart_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
     Log2(("HcPeriodicStart_w(%#010x) => PS=%d\n", val, val & 0x3fff));
     if (val & ~0x3fff)
@@ -4754,4 +4792,5 @@
 static int HcLSThreshold_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF2(pThis, iReg);
     Log2(("HcLSThreshold_r() -> %#010x\n", OHCI_LS_THRESH));
     *pu32Value = OHCI_LS_THRESH;
@@ -4773,4 +4812,5 @@
 static int HcLSThreshold_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF3(pThis, iReg, val);
     Log2(("HcLSThreshold_w(%#010x) => LST=0x%03x(%d)\n", val, val & 0x0fff, val & 0x0fff));
     AssertMsg(val == OHCI_LS_THRESH,
@@ -4785,4 +4825,5 @@
 static int HcRhDescriptorA_r(PCOHCI pThis, uint32_t iReg, uint32_t *pu32Value)
 {
+    RT_NOREF1(iReg);
     uint32_t val = pThis->RootHub.desc_a;
 #if 0 /* annoying */
@@ -4800,4 +4841,5 @@
 static int HcRhDescriptorA_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
     uint32_t chg = val ^ pThis->RootHub.desc_a; NOREF(chg);
     Log2(("HcRhDescriptorA_w(%#010x) => %sNDP=%d %sPSM=%d %sNPS=%d %sDT=%d %sOCPM=%d %sNOCP=%d %sPOTGT=%#x - %sPowerSwitching Set%sPower\n",
@@ -4837,4 +4879,5 @@
           val, val & 0xffff, val >> 16));
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4845,4 +4888,5 @@
 static int HcRhDescriptorB_w(POHCI pThis, uint32_t iReg, uint32_t val)
 {
+    RT_NOREF1(iReg);
     uint32_t chg = pThis->RootHub.desc_b ^ val; NOREF(chg);
     Log2(("HcRhDescriptorB_w(%#010x) => %sDR=0x%04x %sPPCM=0x%04x\n",
@@ -4869,4 +4913,5 @@
               val, val & 1, (val >> 1) & 1, (val >> 15) & 1, (val >> 16) & 1, (val >> 17) & 1, (val >> 31) & 1));
     *pu32Value = val;
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 }
@@ -4926,6 +4971,8 @@
           (chg >> 17) & 1 ? "*" : "", (val >> 17) & 1,
           (chg >> 31) & 1 ? "*" : "", (val >> 31) & 1));
+    RT_NOREF1(iReg);
     return VINF_SUCCESS;
 #else  /* !IN_RING3 */
+    RT_NOREF3(pThis, iReg, val);
     return VINF_IOM_R3_MMIO_WRITE;
 #endif /* !IN_RING3 */
@@ -5063,5 +5110,5 @@
     uint32_t        old_state = p->fReg;
 
-#ifdef LOG_ENABLED
+# ifdef LOG_ENABLED
     /*
      * Log it.
@@ -5083,5 +5130,5 @@
             Log2((" %s", apszCmdNames[j]));
     Log2(("\n"));
-#endif
+# endif
 
     /* Write to clear any of the change bits: CSC, PESC, PSSC, OCIC and PRSC */
@@ -5159,4 +5206,5 @@
     return VINF_SUCCESS;
 #else /* !IN_RING3 */
+    RT_NOREF3(pThis, iReg, val);
     return VINF_IOM_R3_MMIO_WRITE;
 #endif /* !IN_RING3 */
@@ -5224,4 +5272,5 @@
 {
     POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
+    RT_NOREF1(pvUser);
 
     /* Paranoia: Assert that IOMMMIO_FLAGS_READ_DWORD works. */
@@ -5254,4 +5303,5 @@
 {
     POHCI pThis = PDMINS_2_DATA(pDevIns, POHCI);
+    RT_NOREF1(pvUser);
 
     /* Paranoia: Assert that IOMMMIO_FLAGS_WRITE_DWORD_ZEROED works. */
