Changeset 62623 in vbox for trunk/src/VBox/Devices/Storage
- Timestamp:
- Jul 28, 2016 2:58:49 PM (9 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Storage/DevAHCI.cpp (modified) (57 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r62621 r62623 938 938 { 939 939 const char *pszName; 940 int (*pfnRead )(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value);941 int (*pfnWrite)(PAHCI ahci, uint32_t iReg, uint32_t u32Value);940 int (*pfnRead )(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value); 941 int (*pfnWrite)(PAHCI pAhci, uint32_t iReg, uint32_t u32Value); 942 942 } AHCIOPREG; 943 943 … … 948 948 { 949 949 const char *pszName; 950 int (*pfnRead )(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);951 int (*pfnWrite)(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);950 int (*pfnRead )(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value); 951 int (*pfnWrite)(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value); 952 952 } AHCIPORTOPREG; 953 953 … … 1164 1164 } 1165 1165 1166 static int PortCmdIssue_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1167 { 1168 uint32_t uCIValue; 1169 1166 static int PortCmdIssue_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1167 { 1168 RT_NOREF1(iReg); 1170 1169 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); 1171 1170 1172 1171 /* Update the CI register first. */ 1173 u CIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);1172 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0); 1174 1173 pAhciPort->regCI &= ~uCIValue; 1175 1174 … … 1187 1186 /* Send a notification to R3 if u32TasksNew was 0 before our write. */ 1188 1187 if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping)) 1189 ahciIoThreadKick( ahci, pAhciPort);1188 ahciIoThreadKick(pAhci, pAhciPort); 1190 1189 } 1191 1190 … … 1195 1194 } 1196 1195 1197 static int PortCmdIssue_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1198 { 1199 uint32_t uCIValue = 0; 1200 1201 uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0); 1202 1196 static int PortCmdIssue_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1197 { 1198 RT_NOREF1(iReg); 1199 1200 uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0); 1203 1201 ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue)); 1204 1202 1205 1203 pAhciPort->regCI &= ~uCIValue; 1206 1207 1204 *pu32Value = pAhciPort->regCI; 1208 1205 … … 1210 1207 } 1211 1208 1212 static int PortSActive_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1213 { 1209 static int PortSActive_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1210 { 1211 RT_NOREF1(iReg); 1214 1212 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); 1215 1213 … … 1219 1217 } 1220 1218 1221 static int PortSActive_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1222 { 1219 static int PortSActive_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1220 { 1221 RT_NOREF1(iReg); 1222 1223 1223 uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0); 1224 1225 1224 pAhciPort->regSACT &= ~u32TasksFinished; 1226 1225 … … 1233 1232 } 1234 1233 1235 static int PortSError_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1234 static int PortSError_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1236 1235 { 1237 1236 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1254 1253 } 1255 1254 1256 static int PortSError_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1255 static int PortSError_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1257 1256 { 1258 1257 ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR)); … … 1261 1260 } 1262 1261 1263 static int PortSControl_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1262 static int PortSControl_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1264 1263 { 1265 1264 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1273 1272 { 1274 1273 if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true)) 1275 LogRel(("AHCI#%u: Port %d reset\n", ahci->CTX_SUFF(pDevIns)->iInstance,1274 LogRel(("AHCI#%u: Port %d reset\n", pAhci->CTX_SUFF(pDevIns)->iInstance, 1276 1275 pAhciPort->iLUN)); 1277 1276 … … 1287 1286 { 1288 1287 /* Do the port reset here, so the guest sees the new status immediately. */ 1289 if ( ahci->fLegacyPortResetMethod)1288 if (pAhci->fLegacyPortResetMethod) 1290 1289 { 1291 1290 ahciPortResetFinish(pAhciPort); … … 1298 1297 1299 1298 /* Kick the thread to finish the reset. */ 1300 ahciIoThreadKick( ahci, pAhciPort);1299 ahciIoThreadKick(pAhci, pAhciPort); 1301 1300 } 1302 1301 } … … 1308 1307 } 1309 1308 1310 static int PortSControl_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1309 static int PortSControl_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1311 1310 { 1312 1311 ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL)); … … 1319 1318 } 1320 1319 1321 static int PortSStatus_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1320 static int PortSStatus_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1322 1321 { 1323 1322 ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS)); … … 1330 1329 } 1331 1330 1332 static int PortSignature_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1331 static int PortSignature_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1333 1332 { 1334 1333 ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG)); … … 1337 1336 } 1338 1337 1339 static int PortTaskFileData_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1338 static int PortTaskFileData_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1340 1339 { 1341 1340 ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD)); … … 1350 1349 * Read from the port command register. 1351 1350 */ 1352 static int PortCmd_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1351 static int PortCmd_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1353 1352 { 1354 1353 ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot))); … … 1372 1371 * This is the register where all the data transfer is started 1373 1372 */ 1374 static int PortCmd_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1373 static int PortCmd_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1375 1374 { 1376 1375 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1418 1417 ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI); 1419 1418 #ifdef IN_RC 1420 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc( ahci->CTX_SUFF(pNotifierQueue));1419 PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue)); 1421 1420 AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n")); 1422 1421 1423 1422 pItem->iPort = pAhciPort->iLUN; 1424 PDMQueueInsert( ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);1423 PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem); 1425 1424 #else 1426 1425 LogFlowFunc(("Signal event semaphore\n")); 1427 int rc = SUPSemEventSignal( ahci->pSupDrvSession, pAhciPort->hEvtProcess);1426 int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess); 1428 1427 AssertRC(rc); 1429 1428 #endif … … 1518 1517 * Read from the port interrupt enable register. 1519 1518 */ 1520 static int PortIntrEnable_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1519 static int PortIntrEnable_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1521 1520 { 1522 1521 ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE)); … … 1538 1537 * Write to the port interrupt enable register. 1539 1538 */ 1540 static int PortIntrEnable_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1539 static int PortIntrEnable_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1541 1540 { 1542 1541 int rc = VINF_SUCCESS; … … 1559 1558 1560 1559 if (u32Value & u32IntrStatus) 1561 rc = ahciHbaSetInterrupt( ahci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);1560 rc = ahciHbaSetInterrupt(pAhci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE); 1562 1561 1563 1562 if (rc == VINF_SUCCESS) … … 1570 1569 * Read from the port interrupt status register. 1571 1570 */ 1572 static int PortIntrSts_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1571 static int PortIntrSts_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1573 1572 { 1574 1573 ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS)); … … 1590 1589 * Write to the port interrupt status register. 1591 1590 */ 1592 static int PortIntrSts_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1591 static int PortIntrSts_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1593 1592 { 1594 1593 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1601 1600 * Read from the port FIS base address upper 32bit register. 1602 1601 */ 1603 static int PortFisAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1602 static int PortFisAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1604 1603 { 1605 1604 ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU)); … … 1611 1610 * Write to the port FIS base address upper 32bit register. 1612 1611 */ 1613 static int PortFisAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1612 static int PortFisAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1614 1613 { 1615 1614 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1624 1623 * Read from the port FIS base address register. 1625 1624 */ 1626 static int PortFisAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1625 static int PortFisAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1627 1626 { 1628 1627 ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB)); … … 1634 1633 * Write to the port FIS base address register. 1635 1634 */ 1636 static int PortFisAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1635 static int PortFisAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1637 1636 { 1638 1637 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1649 1648 * Write to the port command list base address upper 32bit register. 1650 1649 */ 1651 static int PortCmdLstAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1650 static int PortCmdLstAddrUp_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1652 1651 { 1653 1652 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1662 1661 * Read from the port command list base address upper 32bit register. 1663 1662 */ 1664 static int PortCmdLstAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1663 static int PortCmdLstAddrUp_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1665 1664 { 1666 1665 ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU)); … … 1672 1671 * Read from the port command list base address register. 1673 1672 */ 1674 static int PortCmdLstAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1673 static int PortCmdLstAddr_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1675 1674 { 1676 1675 ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB)); … … 1682 1681 * Write to the port command list base address register. 1683 1682 */ 1684 static int PortCmdLstAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1683 static int PortCmdLstAddr_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1685 1684 { 1686 1685 ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); … … 1697 1696 * Read from the global Version register. 1698 1697 */ 1699 static int HbaVersion_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1700 { 1701 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, ahci->regHbaVs));1702 *pu32Value = ahci->regHbaVs;1698 static int HbaVersion_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1699 { 1700 Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, pAhci->regHbaVs)); 1701 *pu32Value = pAhci->regHbaVs; 1703 1702 return VINF_SUCCESS; 1704 1703 } … … 1707 1706 * Read from the global Ports implemented register. 1708 1707 */ 1709 static int HbaPortsImplemented_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1710 { 1711 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, ahci->regHbaPi));1712 *pu32Value = ahci->regHbaPi;1708 static int HbaPortsImplemented_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1709 { 1710 Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, pAhci->regHbaPi)); 1711 *pu32Value = pAhci->regHbaPi; 1713 1712 return VINF_SUCCESS; 1714 1713 } … … 1717 1716 * Write to the global interrupt status register. 1718 1717 */ 1719 static int HbaInterruptStatus_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)1718 static int HbaInterruptStatus_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value) 1720 1719 { 1721 1720 int rc; 1722 1721 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); 1723 1722 1724 rc = PDMCritSectEnter(& ahci->lock, VINF_IOM_R3_MMIO_WRITE);1723 rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_WRITE); 1725 1724 if (rc != VINF_SUCCESS) 1726 1725 return rc; 1727 1726 1728 ahci->regHbaIs &= ~(u32Value);1727 pAhci->regHbaIs &= ~(u32Value); 1729 1728 1730 1729 /* … … 1733 1732 */ 1734 1733 bool fClear = true; 1735 ahci->regHbaIs |= ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);1736 if (! ahci->regHbaIs)1734 pAhci->regHbaIs |= ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0); 1735 if (!pAhci->regHbaIs) 1737 1736 { 1738 1737 unsigned i = 0; … … 1743 1742 if (u32Value & 0x01) 1744 1743 { 1745 PAHCIPort pAhciPort = & ahci->ahciPort[i];1744 PAHCIPort pAhciPort = &pAhci->ahciPort[i]; 1746 1745 1747 1746 if (pAhciPort->regIE & pAhciPort->regIS) 1748 1747 { 1749 1748 Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i)); 1750 ASMAtomicOrU32(& ahci->u32PortsInterrupted, 1 << i);1749 ASMAtomicOrU32(&pAhci->u32PortsInterrupted, 1 << i); 1751 1750 fClear = false; 1752 1751 break; … … 1761 1760 1762 1761 if (fClear) 1763 ahciHbaClearInterrupt( ahci);1762 ahciHbaClearInterrupt(pAhci); 1764 1763 else 1765 1764 { 1766 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->u32PortsInterrupted));1765 Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->u32PortsInterrupted)); 1767 1766 /* 1768 1767 * We need to set the interrupt again because the I/O APIC does not set it again even if the … … 1770 1769 * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes. 1771 1770 */ 1772 PDMDevHlpPCISetIrq( ahci->CTX_SUFF(pDevIns), 0, 0);1773 PDMDevHlpPCISetIrq( ahci->CTX_SUFF(pDevIns), 0, 1);1774 } 1775 1776 PDMCritSectLeave(& ahci->lock);1771 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0); 1772 PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1); 1773 } 1774 1775 PDMCritSectLeave(&pAhci->lock); 1777 1776 return VINF_SUCCESS; 1778 1777 } … … 1781 1780 * Read from the global interrupt status register. 1782 1781 */ 1783 static int HbaInterruptStatus_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1782 static int HbaInterruptStatus_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1784 1783 { 1785 1784 uint32_t u32PortsInterrupted; 1786 1785 int rc; 1787 1786 1788 rc = PDMCritSectEnter(& ahci->lock, VINF_IOM_R3_MMIO_READ);1787 rc = PDMCritSectEnter(&pAhci->lock, VINF_IOM_R3_MMIO_READ); 1789 1788 if (rc != VINF_SUCCESS) 1790 1789 return rc; 1791 1790 1792 u32PortsInterrupted = ASMAtomicXchgU32(& ahci->u32PortsInterrupted, 0);1793 1794 PDMCritSectLeave(& ahci->lock);1795 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->regHbaIs, u32PortsInterrupted));1796 1797 ahci->regHbaIs |= u32PortsInterrupted;1791 u32PortsInterrupted = ASMAtomicXchgU32(&pAhci->u32PortsInterrupted, 0); 1792 1793 PDMCritSectLeave(&pAhci->lock); 1794 Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, pAhci->regHbaIs, u32PortsInterrupted)); 1795 1796 pAhci->regHbaIs |= u32PortsInterrupted; 1798 1797 1799 1798 #ifdef LOG_ENABLED 1800 1799 Log(("%s:", __FUNCTION__)); 1801 1800 unsigned i; 1802 for (i = 0; i < ahci->cPortsImpl; i++)1803 { 1804 if (( ahci->regHbaIs >> i) & 0x01)1801 for (i = 0; i < pAhci->cPortsImpl; i++) 1802 { 1803 if ((pAhci->regHbaIs >> i) & 0x01) 1805 1804 Log((" P%d", i)); 1806 1805 } … … 1808 1807 #endif 1809 1808 1810 *pu32Value = ahci->regHbaIs;1809 *pu32Value = pAhci->regHbaIs; 1811 1810 1812 1811 return VINF_SUCCESS; … … 1816 1815 * Write to the global control register. 1817 1816 */ 1818 static int HbaControl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)1817 static int HbaControl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value) 1819 1818 { 1820 1819 Log(("%s: write u32Value=%#010x\n" … … 1831 1830 * reset bit. 1832 1831 */ 1833 ASMAtomicIncU32(& ahci->cThreadsActive);1834 ASMAtomicWriteU32(& ahci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);1832 ASMAtomicIncU32(&pAhci->cThreadsActive); 1833 ASMAtomicWriteU32(&pAhci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE); 1835 1834 1836 1835 /* … … 1838 1837 * the work is deferred to the last active thread otherwise. 1839 1838 */ 1840 uint32_t cThreadsActive = ASMAtomicDecU32(& ahci->cThreadsActive);1839 uint32_t cThreadsActive = ASMAtomicDecU32(&pAhci->cThreadsActive); 1841 1840 if ( (u32Value & AHCI_HBA_CTRL_HR) 1842 1841 && !cThreadsActive) 1843 ahciHBAReset( ahci);1842 ahciHBAReset(pAhci); 1844 1843 1845 1844 return VINF_SUCCESS; … … 1850 1849 * Read the global control register. 1851 1850 */ 1852 static int HbaControl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1851 static int HbaControl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1853 1852 { 1854 1853 Log(("%s: read regHbaCtrl=%#010x\n" 1855 1854 "%s: AE=%d IE=%d HR=%d\n", 1856 __FUNCTION__, ahci->regHbaCtrl,1857 __FUNCTION__, ( ahci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (ahci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,1858 ( ahci->regHbaCtrl & AHCI_HBA_CTRL_HR)));1859 *pu32Value = ahci->regHbaCtrl;1855 __FUNCTION__, pAhci->regHbaCtrl, 1856 __FUNCTION__, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (pAhci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1, 1857 (pAhci->regHbaCtrl & AHCI_HBA_CTRL_HR))); 1858 *pu32Value = pAhci->regHbaCtrl; 1860 1859 return VINF_SUCCESS; 1861 1860 } … … 1864 1863 * Read the global capabilities register. 1865 1864 */ 1866 static int HbaCapabilities_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1865 static int HbaCapabilities_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1867 1866 { 1868 1867 Log(("%s: read regHbaCap=%#010x\n" 1869 1868 "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n", 1870 __FUNCTION__, ahci->regHbaCap,1871 __FUNCTION__, ( ahci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (ahci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,1872 ( ahci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (ahci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,1873 ( ahci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (ahci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,1874 ( ahci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (ahci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,1875 ( ahci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (ahci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,1876 ( ahci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (ahci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,1877 ( ahci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (ahci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,1878 ( ahci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (ahci->regHbaCap & AHCI_HBA_CAP_NP)));1879 *pu32Value = ahci->regHbaCap;1869 __FUNCTION__, pAhci->regHbaCap, 1870 __FUNCTION__, (pAhci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (pAhci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30, 1871 (pAhci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (pAhci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27, 1872 (pAhci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (pAhci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25, 1873 (pAhci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (pAhci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20, 1874 (pAhci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (pAhci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18, 1875 (pAhci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (pAhci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15, 1876 (pAhci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (pAhci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13, 1877 (pAhci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (pAhci->regHbaCap & AHCI_HBA_CAP_NP))); 1878 *pu32Value = pAhci->regHbaCap; 1880 1879 return VINF_SUCCESS; 1881 1880 } … … 1884 1883 * Write to the global command completion coalescing control register. 1885 1884 */ 1886 static int HbaCccCtl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)1885 static int HbaCccCtl_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value) 1887 1886 { 1888 1887 Log(("%s: write u32Value=%#010x\n" … … 1892 1891 AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN))); 1893 1892 1894 ahci->regHbaCccCtl = u32Value;1895 ahci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);1896 ahci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);1897 ahci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);1893 pAhci->regHbaCccCtl = u32Value; 1894 pAhci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value); 1895 pAhci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value); 1896 pAhci->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value); 1898 1897 1899 1898 if (u32Value & AHCI_HBA_CCC_CTL_EN) 1900 1899 { 1901 1900 /* Arm the timer */ 1902 TMTimerSetMillies( ahci->CTX_SUFF(pHbaCccTimer), ahci->uCccTimeout);1901 TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout); 1903 1902 } 1904 1903 else 1905 1904 { 1906 TMTimerStop( ahci->CTX_SUFF(pHbaCccTimer));1905 TMTimerStop(pAhci->CTX_SUFF(pHbaCccTimer)); 1907 1906 } 1908 1907 … … 1913 1912 * Read the global command completion coalescing control register. 1914 1913 */ 1915 static int HbaCccCtl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1914 static int HbaCccCtl_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1916 1915 { 1917 1916 Log(("%s: read regHbaCccCtl=%#010x\n" 1918 1917 "%s: TV=%d CC=%d INT=%d EN=%d\n", 1919 __FUNCTION__, ahci->regHbaCccCtl,1920 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET( ahci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(ahci->regHbaCccCtl),1921 AHCI_HBA_CCC_CTL_INT_GET( ahci->regHbaCccCtl), (ahci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));1922 *pu32Value = ahci->regHbaCccCtl;1918 __FUNCTION__, pAhci->regHbaCccCtl, 1919 __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(pAhci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(pAhci->regHbaCccCtl), 1920 AHCI_HBA_CCC_CTL_INT_GET(pAhci->regHbaCccCtl), (pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN))); 1921 *pu32Value = pAhci->regHbaCccCtl; 1923 1922 return VINF_SUCCESS; 1924 1923 } … … 1927 1926 * Write to the global command completion coalescing ports register. 1928 1927 */ 1929 static int HbaCccPorts_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)1928 static int HbaCccPorts_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value) 1930 1929 { 1931 1930 Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value)); 1932 1931 1933 ahci->regHbaCccPorts = u32Value;1932 pAhci->regHbaCccPorts = u32Value; 1934 1933 1935 1934 return VINF_SUCCESS; … … 1939 1938 * Read the global command completion coalescing ports register. 1940 1939 */ 1941 static int HbaCccPorts_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)1942 { 1943 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, ahci->regHbaCccPorts));1940 static int HbaCccPorts_r(PAHCI pAhci, uint32_t iReg, uint32_t *pu32Value) 1941 { 1942 Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, pAhci->regHbaCccPorts)); 1944 1943 1945 1944 #ifdef LOG_ENABLED 1946 1945 Log(("%s:", __FUNCTION__)); 1947 1946 unsigned i; 1948 for (i = 0; i < ahci->cPortsImpl; i++)1949 { 1950 if (( ahci->regHbaCccPorts >> i) & 0x01)1947 for (i = 0; i < pAhci->cPortsImpl; i++) 1948 { 1949 if ((pAhci->regHbaCccPorts >> i) & 0x01) 1951 1950 Log((" P%d", i)); 1952 1951 } … … 1954 1953 #endif 1955 1954 1956 *pu32Value = ahci->regHbaCccPorts;1955 *pu32Value = pAhci->regHbaCccPorts; 1957 1956 return VINF_SUCCESS; 1958 1957 } … … 1961 1960 * Invalid write to global register 1962 1961 */ 1963 static int HbaInvalid_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)1962 static int HbaInvalid_w(PAHCI pAhci, uint32_t iReg, uint32_t u32Value) 1964 1963 { 1965 1964 Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value)); … … 1970 1969 * Invalid Port write. 1971 1970 */ 1972 static int PortInvalid_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)1971 static int PortInvalid_w(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value) 1973 1972 { 1974 1973 ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value)); … … 1979 1978 * Invalid Port read. 1980 1979 */ 1981 static int PortInvalid_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)1980 static int PortInvalid_r(PAHCI pAhci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value) 1982 1981 { 1983 1982 ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg)); … … 5720 5719 * 5721 5720 * @returns Whether all active tasks were canceled. 5722 * @param pAhciPort The ahciport.5721 * @param pAhciPort The AHCI port. 5723 5722 * @param pAhciReqExcept The given request is excepted from the cancelling 5724 5723 * (used for error page reading).
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