Changeset 62903 in vbox for trunk/src/VBox/Devices/PC
- Timestamp:
- Aug 3, 2016 11:03:45 AM (9 years ago)
- svn:sync-xref-src-repo-rev:
- 109504
- Location:
- trunk/src/VBox/Devices/PC
- Files:
-
- 3 edited
-
DevDMA.cpp (modified) (13 diffs)
-
DevHPET.cpp (modified) (1 diff)
-
DevIoApic.cpp (modified) (15 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/PC/DevDMA.cpp
r62509 r62903 209 209 #define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2) 210 210 211 211 212 /* Perform a master clear (reset) on a DMA controller. */ 212 213 static void dmaClear(DMAControl *dc) … … 217 218 dc->u8ModeCtr = 0; 218 219 dc->fHiByte = false; 219 dc->u8Mask = ~0; 220 } 221 222 /* Read the byte pointer and flip it. */ 223 static inline bool dmaReadBytePtr(DMAControl *dc) 220 dc->u8Mask = UINT8_MAX; 221 } 222 223 224 /** Read the byte pointer and flip it. */ 225 DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc) 224 226 { 225 227 bool bHighByte; … … 230 232 } 231 233 234 232 235 /* DMA address registers writes and reads. */ 233 236 237 /** 238 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf} 239 */ 234 240 static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb) 235 241 { 242 RT_NOREF(pDevIns); 236 243 if (cb == 1) 237 244 { … … 276 283 } 277 284 285 286 /** 287 * @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf} 288 */ 278 289 static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb) 279 290 { 291 RT_NOREF(pDevIns); 280 292 if (cb == 1) 281 293 { … … 301 313 return VINF_SUCCESS; 302 314 } 303 else 304 return VERR_IOM_IOPORT_UNUSED; 315 return VERR_IOM_IOPORT_UNUSED; 305 316 } 306 317 307 318 /* DMA control registers writes and reads. */ 308 319 309 static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, 310 uint32_t u32, unsigned cb) 311 { 320 /** 321 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf} 322 */ 323 static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb) 324 { 325 RT_NOREF(pDevIns); 312 326 if (cb == 1) 313 327 { … … 387 401 } 388 402 403 404 /** 405 * @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf} 406 */ 389 407 static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb) 390 408 { 409 RT_NOREF(pDevIns); 391 410 if (cb == 1) 392 411 { … … 438 457 } 439 458 440 /** DMA page registers. There are 16 R/W page registers for compatibility with 441 * the IBM PC/AT; only some of those registers are used for DMA. The page register 442 * accessible via port 80h may be read to insert small delays or used as a scratch 443 * register by a BIOS. 459 /** 460 */ 461 462 /** 463 * @callback_method_impl{FNIOMIOPORTIN, 464 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f} 465 * 466 * There are 16 R/W page registers for compatibility with the IBM PC/AT; only 467 * some of those registers are used for DMA. The page register accessible via 468 * port 80h may be read to insert small delays or used as a scratch register by 469 * a BIOS. 444 470 */ 445 471 static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb) 446 472 { 473 RT_NOREF(pDevIns); 447 474 DMAControl *dc = (DMAControl *)pvUser; 448 475 int reg; … … 469 496 } 470 497 498 499 /** 500 * @callback_method_impl{FNIOMIOPORTOUT, 501 * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f} 502 */ 471 503 static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb) 472 504 { 505 RT_NOREF(pDevIns); 473 506 DMAControl *dc = (DMAControl *)pvUser; 474 507 int reg; … … 502 535 } 503 536 504 /** 505 * EISA style high page registers, for extending the DMA addresses to cover 506 * the entire 32-bit address space. 537 538 /** 539 * @callback_method_impl{FNIOMIOPORTIN, 540 * EISA style high page registers, for extending the DMA addresses to cover 541 * the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f} 507 542 */ 508 543 static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb) 509 544 { 545 RT_NOREF(pDevIns); 510 546 if (cb == 1) 511 547 { … … 522 558 } 523 559 560 561 /** 562 * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f} 563 */ 524 564 static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb) 525 565 { 566 RT_NOREF(pDevIns); 526 567 if (cb == 1) 527 568 { … … 938 979 static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 939 980 { 940 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *); 941 bool bHighPage = false; 942 PDMDMACREG reg; 943 int rc; 944 981 RT_NOREF(iInstance); 982 DMAState *pThis = PDMINS_2_DATA(pDevIns, DMAState *); 983 984 /* 985 * Initialize data. 986 */ 945 987 pThis->pDevIns = pDevIns; 946 988 … … 951 993 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES; 952 994 995 bool bHighPage = false; 953 996 #if 0 954 997 rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage); … … 960 1003 dmaReset(pDevIns); 961 1004 962 reg.u32Version = PDM_DMACREG_VERSION; 963 reg.pfnRun = dmaRun; 964 reg.pfnRegister = dmaRegister; 965 reg.pfnReadMemory = dmaReadMemory; 966 reg.pfnWriteMemory = dmaWriteMemory; 967 reg.pfnSetDREQ = dmaSetDREQ; 968 reg.pfnGetChannelMode = dmaGetChannelMode; 969 970 rc = PDMDevHlpDMACRegister(pDevIns, ®, &pThis->pHlp); 1005 PDMDMACREG Reg; 1006 Reg.u32Version = PDM_DMACREG_VERSION; 1007 Reg.pfnRun = dmaRun; 1008 Reg.pfnRegister = dmaRegister; 1009 Reg.pfnReadMemory = dmaReadMemory; 1010 Reg.pfnWriteMemory = dmaWriteMemory; 1011 Reg.pfnSetDREQ = dmaSetDREQ; 1012 Reg.pfnGetChannelMode = dmaGetChannelMode; 1013 1014 int rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp); 971 1015 if (RT_FAILURE (rc)) 972 1016 return rc; -
trunk/src/VBox/Devices/PC/DevHPET.cpp
r62509 r62903 1308 1308 static DECLCALLBACK(int) hpetR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 1309 1309 { 1310 RT_NOREF(iInstance); 1310 1311 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); 1311 1312 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *); -
trunk/src/VBox/Devices/PC/DevIoApic.cpp
r62610 r62903 843 843 844 844 #ifdef IN_RING3 845 845 846 /** @interface_method_impl{DBGFREGDESC,pfnGet} */ 846 847 static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 847 848 { 849 RT_NOREF(pDesc); 848 850 pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)); 849 851 return VINF_SUCCESS; 850 852 } 851 853 854 852 855 /** @interface_method_impl{DBGFREGDESC,pfnSet} */ 853 856 static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 854 857 { 858 RT_NOREF(pDesc, pfMask); 855 859 ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8); 856 860 return VINF_SUCCESS; 857 861 } 858 862 863 859 864 /** @interface_method_impl{DBGFREGDESC,pfnGet} */ 860 865 static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 861 866 { 867 RT_NOREF(pDesc); 862 868 pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC))); 863 869 return VINF_SUCCESS; 864 870 } 865 871 872 866 873 /** @interface_method_impl{DBGFREGDESC,pfnSet} */ 867 874 static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 868 875 { 876 RT_NOREF(pDesc, pfMask); 869 877 return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32); 870 878 } 879 871 880 872 881 /** @interface_method_impl{DBGFREGDESC,pfnGet} */ 873 882 static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 874 883 { 884 RT_NOREF(pvUser, pDesc); 875 885 pValue->u32 = ioapicGetVersion(); 876 886 return VINF_SUCCESS; 877 887 } 878 888 889 879 890 /** @interface_method_impl{DBGFREGDESC,pfnGet} */ 880 891 static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue) 881 892 { 882 #if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA 893 RT_NOREF(pvUser, pDesc); 894 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA 883 895 pValue->u32 = ioapicGetArb(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)); 884 # else896 # else 885 897 pValue->u32 = UINT32_C(0xffffffff); 886 # endif898 # endif 887 899 return VINF_SUCCESS; 888 900 } 901 889 902 890 903 /** @interface_method_impl{DBGFREGDESC,pfnGet} */ … … 897 910 } 898 911 912 899 913 /** @interface_method_impl{DBGFREGDESC,pfnSet} */ 900 914 static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask) 901 915 { 916 RT_NOREF(pfMask); 902 917 PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC); 903 918 /* No locks, no checks, just do it. */ … … 906 921 return VINF_SUCCESS; 907 922 } 923 908 924 909 925 /** IOREDTBLn sub fields. */ … … 918 934 { "trigger_mode", 15, 1, 0, 0, NULL, NULL }, 919 935 { "mask", 16, 1, 0, 0, NULL, NULL }, 920 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9936 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9 921 937 { "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL }, 922 # endif938 # endif 923 939 { "dest", 56, 8, 0, 0, NULL, NULL }, 924 940 DBGFREGSUBFIELD_TERMINATOR() 925 941 }; 926 942 943 927 944 /** Register descriptors for DBGF. */ 928 945 static DBGFREGDESC const g_aRegDesc[] = … … 931 948 { "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL }, 932 949 { "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL }, 933 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA950 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA 934 951 { "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL }, 935 # endif952 # endif 936 953 { "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] }, 937 954 { "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] }, … … 967 984 static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs) 968 985 { 986 RT_NOREF(pszArgs); 969 987 PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); 970 988 LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs)); … … 982 1000 pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer)); 983 1001 984 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA1002 # if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA 985 1003 uint32_t const uArb = ioapicGetArb(); 986 1004 pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb); 987 1005 pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb)); 988 # endif1006 # endif 989 1007 990 1008 pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis)); … … 1116 1134 static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta) 1117 1135 { 1136 RT_NOREF(offDelta); 1118 1137 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); 1119 1138 LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta)); … … 1133 1152 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); 1134 1153 1135 # ifndef IOAPIC_WITH_PDM_CRITSECT1154 # ifndef IOAPIC_WITH_PDM_CRITSECT 1136 1155 /* 1137 1156 * Destroy the RTE critical section. … … 1139 1158 if (PDMCritSectIsInitialized(&pThis->CritSect)) 1140 1159 PDMR3CritSectDelete(&pThis->CritSect); 1141 #endif 1160 # else 1161 RT_NOREF_PV(pThis); 1162 # endif 1142 1163 1143 1164 return VINF_SUCCESS; … … 1150 1171 static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) 1151 1172 { 1173 RT_NOREF(iInstance); 1152 1174 PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC); 1153 1175 LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance)); … … 1188 1210 AssertRCReturn(rc, rc); 1189 1211 1190 # ifndef IOAPIC_WITH_PDM_CRITSECT1212 # ifndef IOAPIC_WITH_PDM_CRITSECT 1191 1213 /* 1192 1214 * Setup the critical section to protect concurrent writes to the RTEs. … … 1195 1217 if (RT_FAILURE(rc)) 1196 1218 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc); 1197 # endif1219 # endif 1198 1220 1199 1221 /* … … 1273 1295 AssertRCReturn(rc, rc); 1274 1296 1275 # ifdef VBOX_WITH_STATISTICS1297 # ifdef VBOX_WITH_STATISTICS 1276 1298 /* 1277 1299 * Statistics. … … 1296 1318 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s)."); 1297 1319 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s)."); 1298 # endif1320 # endif 1299 1321 1300 1322 /*
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