Changeset 63478 in vbox for trunk/src/VBox/Devices/USB
- Timestamp:
- Aug 15, 2016 2:04:10 PM (8 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/USB/DevOHCI.cpp
r63016 r63478 772 772 #ifndef VBOX_DEVICE_STRUCT_TESTCASE 773 773 774 #ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 775 /* 776 * Explain 777 */ 778 typedef struct OHCIDESCREADSTATS 779 { 780 uint32_t cReads; 781 uint32_t cPageChange; 782 uint32_t cMinReadsPerPage; 783 uint32_t cMaxReadsPerPage; 784 785 uint32_t cReadsLastPage; 786 uint32_t u32LastPageAddr; 787 } OHCIDESCREADSTATS; 788 typedef OHCIDESCREADSTATS *POHCIDESCREADSTATS; 789 790 typedef struct OHCIPHYSREADSTATS 791 { 792 OHCIDESCREADSTATS ed; 793 OHCIDESCREADSTATS td; 794 OHCIDESCREADSTATS all; 795 796 uint32_t cCrossReads; 797 uint32_t cCacheReads; 798 uint32_t cPageReads; 799 } OHCIPHYSREADSTATS; 800 typedef OHCIPHYSREADSTATS *POHCIPHYSREADSTATS; 801 typedef OHCIPHYSREADSTATS const *PCOHCIPHYSREADSTATS; 802 #endif /* VBOX_WITH_OHCI_PHYS_READ_STATS */ 803 774 804 775 805 /********************************************************************************************************************************* 776 806 * Global Variables * 777 807 *********************************************************************************************************************************/ 808 #if defined(VBOX_WITH_OHCI_PHYS_READ_STATS) && defined(IN_RING3) 809 static OHCIPHYSREADSTATS g_PhysReadState; 810 #endif 811 778 812 #if defined(LOG_ENABLED) && defined(IN_RING3) 779 813 static bool g_fLogBulkEPs = false; … … 873 907 } 874 908 909 #ifdef IN_RING3 910 875 911 /** 876 912 * Set an interrupt, use the wrapper ohciSetInterrupt. … … 895 931 * Set an interrupt wrapper macro for logging purposes. 896 932 */ 897 #define ohciSetInterrupt(ohci, a_rcBusy, intr) ohciSetInterruptInt(ohci, a_rcBusy, intr, #intr) 898 #define ohciR3SetInterrupt(ohci, intr) ohciSetInterruptInt(ohci, VERR_IGNORED, intr, #intr) 899 900 #ifdef IN_RING3 933 # define ohciR3SetInterrupt(ohci, intr) ohciSetInterruptInt(ohci, VERR_IGNORED, intr, #intr) 934 901 935 902 936 /* Carry out a hardware remote wakeup */ … … 1217 1251 VUSBIDevReset(pThis->RootHub.pIDev, fResetOnLinux, NULL, NULL, NULL); 1218 1252 } 1219 #endif /* IN_RING3 */1220 1253 1221 1254 /** … … 1243 1276 { 1244 1277 ohciPhysRead(pThis, Addr, pau32s, c32s * sizeof(uint32_t)); 1245 # ifndef RT_LITTLE_ENDIAN1278 # ifndef RT_LITTLE_ENDIAN 1246 1279 for(int i = 0; i < c32s; i++) 1247 1280 pau32s[i] = RT_H2LE_U32(pau32s[i]); 1248 # endif1281 # endif 1249 1282 } 1250 1283 … … 1254 1287 DECLINLINE(void) ohciPutDWords(POHCI pThis, uint32_t Addr, const uint32_t *pau32s, int cu32s) 1255 1288 { 1256 # ifdef RT_LITTLE_ENDIAN1289 # ifdef RT_LITTLE_ENDIAN 1257 1290 ohciPhysWrite(pThis, Addr, pau32s, cu32s << 2); 1258 # else1291 # else 1259 1292 for (int i = 0; i < c32s; i++, pau32s++, Addr += sizeof(*pau32s)) 1260 1293 { … … 1262 1295 ohciPhysWrite(pThis, Addr, (uint8_t *)&u32Tmp, sizeof(u32Tmp)); 1263 1296 } 1264 #endif 1265 } 1266 1267 1268 #ifdef IN_RING3 1269 1270 #ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1271 struct DescReadStats 1272 { 1273 uint32_t cReads; 1274 uint32_t cPageChange; 1275 uint32_t cMinReadsPerPage; 1276 uint32_t cMaxReadsPerPage; 1277 1278 uint32_t cReadsLastPage; 1279 uint32_t u32LastPageAddr; 1280 }; 1281 1282 struct PhysReadStats 1283 { 1284 struct DescReadStats ed; 1285 struct DescReadStats td; 1286 struct DescReadStats all; 1287 1288 uint32_t cCrossReads; 1289 uint32_t cCacheReads; 1290 uint32_t cPageReads; 1291 }; 1292 1293 static struct PhysReadStats physReadStats; 1294 1295 static void descReadStatsReset(struct DescReadStats *p) 1297 # endif 1298 } 1299 1300 1301 1302 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1303 1304 static void descReadStatsReset(POHCIDESCREADSTATS p) 1296 1305 { 1297 1306 p->cReads = 0; … … 1304 1313 } 1305 1314 1306 static void physReadStatsReset( struct PhysReadStats *p)1315 static void physReadStatsReset(POHCIPHYSREADSTATS p) 1307 1316 { 1308 1317 descReadStatsReset(&p->ed); … … 1315 1324 } 1316 1325 1317 static void physReadStatsUpdateDesc( struct DescReadStats *p, uint32_t u32Addr)1326 static void physReadStatsUpdateDesc(POHCIDESCREADSTATS p, uint32_t u32Addr) 1318 1327 { 1319 1328 const uint32_t u32PageAddr = u32Addr & ~UINT32_C(0xFFF); … … 1345 1354 } 1346 1355 1347 static void physReadStatsPrint( struct PhysReadStats *p)1356 static void physReadStatsPrint(PCOHCIPHYSREADSTATS p) 1348 1357 { 1349 1358 p->ed.cMinReadsPerPage = RT_MIN(p->ed.cMinReadsPerPage, p->ed.cReadsLastPage); … … 1370 1379 physReadStatsReset(p); 1371 1380 } 1372 #endif /* VBOX_WITH_OHCI_PHYS_READ_STATS */ 1373 1374 #ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 1381 1382 # endif /* VBOX_WITH_OHCI_PHYS_READ_STATS */ 1383 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 1384 1375 1385 static POHCIPAGECACHE ohciPhysReadCacheAlloc(void) 1376 1386 { … … 1399 1409 pPageCache->au8PhysReadCache, sizeof(pPageCache->au8PhysReadCache)); 1400 1410 pPageCache->GCPhysReadCacheAddr = PageAddr; 1401 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS1402 ++ physReadStats.cPageReads;1403 # endif1411 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1412 ++g_PhysReadState.cPageReads; 1413 # endif 1404 1414 } 1405 1415 1406 1416 memcpy(pvBuf, &pPageCache->au8PhysReadCache[GCPhys & PAGE_OFFSET_MASK], cbBuf); 1407 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS1408 ++ physReadStats.cCacheReads;1409 # endif1417 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1418 ++g_PhysReadState.cCacheReads; 1419 # endif 1410 1420 } 1411 1421 else 1412 1422 { 1413 1423 PDMDevHlpPhysRead(pThis->pDevInsR3, GCPhys, pvBuf, cbBuf); 1414 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS1415 ++ physReadStats.cCrossReads;1416 # endif1424 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1425 ++g_PhysReadState.cCrossReads; 1426 # endif 1417 1427 } 1418 1428 } … … 1427 1437 ohciPhysReadCacheRead(pThis, pThis->pCacheTD, TdAddr, pTd, sizeof(*pTd)); 1428 1438 } 1429 #endif /* VBOX_WITH_OHCI_PHYS_READ_CACHE */ 1439 1440 # endif /* VBOX_WITH_OHCI_PHYS_READ_CACHE */ 1430 1441 1431 1442 /** … … 1434 1445 DECLINLINE(void) ohciReadEd(POHCI pThis, uint32_t EdAddr, POHCIED pEd) 1435 1446 { 1436 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS1437 physReadStatsUpdateDesc(& physReadStats.ed, EdAddr);1438 physReadStatsUpdateDesc(& physReadStats.all, EdAddr);1439 # endif1447 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1448 physReadStatsUpdateDesc(&g_PhysReadState.ed, EdAddr); 1449 physReadStatsUpdateDesc(&g_PhysReadState.all, EdAddr); 1450 # endif 1440 1451 ohciGetDWords(pThis, EdAddr, (uint32_t *)pEd, sizeof(*pEd) >> 2); 1441 1452 } … … 1446 1457 DECLINLINE(void) ohciReadTd(POHCI pThis, uint32_t TdAddr, POHCITD pTd) 1447 1458 { 1448 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS1449 physReadStatsUpdateDesc(& physReadStats.td, TdAddr);1450 physReadStatsUpdateDesc(& physReadStats.all, TdAddr);1451 # endif1459 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 1460 physReadStatsUpdateDesc(&g_PhysReadState.td, TdAddr); 1461 physReadStatsUpdateDesc(&g_PhysReadState.all, TdAddr); 1462 # endif 1452 1463 ohciGetDWords(pThis, TdAddr, (uint32_t *)pTd, sizeof(*pTd) >> 2); 1453 # ifdef LOG_ENABLED1464 # ifdef LOG_ENABLED 1454 1465 if (LogIs3Enabled()) 1455 1466 { … … 1468 1479 pTd->be, 1469 1480 pTd->hwinfo & TD_HWINFO_UNKNOWN_MASK)); 1470 # if 01481 # if 0 1471 1482 if (LogIs3Enabled()) 1472 1483 { … … 1493 1504 sizeof(abXpTd), &abXpTd[0])); 1494 1505 } 1495 # endif1496 } 1497 # endif1506 # endif 1507 } 1508 # endif 1498 1509 } 1499 1510 … … 1504 1515 { 1505 1516 ohciGetDWords(pThis, ITdAddr, (uint32_t *)pITd, sizeof(*pITd) / sizeof(uint32_t)); 1506 # ifdef LOG_ENABLED1517 # ifdef LOG_ENABLED 1507 1518 if (LogIs3Enabled()) 1508 1519 { … … 1526 1537 pITd->aPSW[7] >> 12, pITd->aPSW[7] & 0xfff)); 1527 1538 } 1528 # endif1539 # endif 1529 1540 } 1530 1541 … … 1535 1546 DECLINLINE(void) ohciWriteEd(POHCI pThis, uint32_t EdAddr, PCOHCIED pEd) 1536 1547 { 1537 # ifdef LOG_ENABLED1548 # ifdef LOG_ENABLED 1538 1549 if (LogIs3Enabled()) 1539 1550 { … … 1558 1569 EdOld.NextED != pEd->NextED ? "*" : "", pEd->NextED)); 1559 1570 } 1560 # endif1571 # endif 1561 1572 1562 1573 ohciPutDWords(pThis, EdAddr, (uint32_t *)pEd, sizeof(*pEd) >> 2); … … 1569 1580 DECLINLINE(void) ohciWriteTd(POHCI pThis, uint32_t TdAddr, PCOHCITD pTd, const char *pszLogMsg) 1570 1581 { 1571 # ifdef LOG_ENABLED1582 # ifdef LOG_ENABLED 1572 1583 if (LogIs3Enabled()) 1573 1584 { … … 1588 1599 pszLogMsg)); 1589 1600 } 1590 # else1601 # else 1591 1602 RT_NOREF(pszLogMsg); 1592 # endif1603 # endif 1593 1604 ohciPutDWords(pThis, TdAddr, (uint32_t *)pTd, sizeof(*pTd) >> 2); 1594 1605 } … … 1599 1610 DECLINLINE(void) ohciWriteITd(POHCI pThis, uint32_t ITdAddr, PCOHCIITD pITd, const char *pszLogMsg) 1600 1611 { 1601 # ifdef LOG_ENABLED1612 # ifdef LOG_ENABLED 1602 1613 if (LogIs3Enabled()) 1603 1614 { … … 1625 1636 (ITdOld.aPSW[7] >> 12) != (pITd->aPSW[7] >> 12) ? "*" : "", pITd->aPSW[7] >> 12, (ITdOld.aPSW[7] & 0xfff) != (pITd->aPSW[7] & 0xfff) ? "*" : "", pITd->aPSW[7] & 0xfff)); 1626 1637 } 1627 # else1638 # else 1628 1639 RT_NOREF(pszLogMsg); 1629 # endif1640 # endif 1630 1641 ohciPutDWords(pThis, ITdAddr, (uint32_t *)pITd, sizeof(*pITd) / sizeof(uint32_t)); 1631 1642 } 1632 1643 1633 1644 1634 # ifdef LOG_ENABLED1645 # ifdef LOG_ENABLED 1635 1646 1636 1647 /** … … 1770 1781 } 1771 1782 1772 # endif /* LOG_ENABLED */1783 # endif /* LOG_ENABLED */ 1773 1784 1774 1785 … … 1804 1815 if (i >= 0) 1805 1816 { 1806 # ifdef LOG_ENABLED1817 # ifdef LOG_ENABLED 1807 1818 pUrb->pHci->u32FrameNo = pThis->HcFmNumber; 1808 # endif1819 # endif 1809 1820 pThis->aInFlight[i].GCPhysTD = GCPhysTD; 1810 1821 pThis->aInFlight[i].pUrb = pUrb; … … 1908 1919 if (i >= 0) 1909 1920 { 1910 # ifdef LOG_ENABLED1921 # ifdef LOG_ENABLED 1911 1922 const int cFramesInFlight = pThis->HcFmNumber - pThis->aInFlight[i].pUrb->pHci->u32FrameNo; 1912 # else1923 # else 1913 1924 const int cFramesInFlight = 0; 1914 # endif1925 # endif 1915 1926 Log2(("ohci_in_flight_remove: reaping TD=%#010x %d frames (%#010x-%#010x)\n", 1916 1927 GCPhysTD, cFramesInFlight, pThis->aInFlight[i].pUrb->pHci->u32FrameNo, pThis->HcFmNumber)); … … 1946 1957 1947 1958 1948 # if defined(VBOX_STRICT) || defined(LOG_ENABLED)1959 # if defined(VBOX_STRICT) || defined(LOG_ENABLED) 1949 1960 1950 1961 /** … … 1981 1992 { 1982 1993 int i = ohci_in_done_queue_find(pThis, GCPhysTD); 1983 # if 01994 # if 0 1984 1995 /* This condition has been observed with the USB tablet emulation or with 1985 1996 * a real USB mouse and an SMP XP guest. I am also not sure if this is … … 1993 2004 */ 1994 2005 AssertMsg(i < 0, ("TD %#010x (i=%d)\n", GCPhysTD, i)); 1995 # endif2006 # endif 1996 2007 return i < 0; 1997 2008 } 1998 2009 1999 2010 2000 # ifdef VBOX_STRICT2011 # ifdef VBOX_STRICT 2001 2012 /** 2002 2013 * Adds a TD to the in-done-queue tracking, checking that it's not there already. … … 2010 2021 pThis->aInDoneQueue[pThis->cInDoneQueue++].GCPhysTD = GCPhysTD; 2011 2022 } 2012 # endif /* VBOX_STRICT */2013 # endif /* defined(VBOX_STRICT) || defined(LOG_ENABLED) */2023 # endif /* VBOX_STRICT */ 2024 # endif /* defined(VBOX_STRICT) || defined(LOG_ENABLED) */ 2014 2025 2015 2026 … … 2524 2535 * Move on to the done list and write back the modified TD. 2525 2536 */ 2526 # ifdef LOG_ENABLED2537 # ifdef LOG_ENABLED 2527 2538 if (!pThis->done) 2528 2539 pThis->u32FmDoneQueueTail = pThis->HcFmNumber; 2529 # ifdef VBOX_STRICT2540 # ifdef VBOX_STRICT 2530 2541 ohci_in_done_queue_add(pThis, ITdAddr); 2542 # endif 2531 2543 # endif 2532 #endif2533 2544 pITd->NextTD = pThis->done; 2534 2545 pThis->done = ITdAddr; … … 2663 2674 * Move on to the done list and write back the modified TD. 2664 2675 */ 2665 # ifdef LOG_ENABLED2676 # ifdef LOG_ENABLED 2666 2677 if (!pThis->done) 2667 2678 pThis->u32FmDoneQueueTail = pThis->HcFmNumber; 2668 # ifdef VBOX_STRICT2679 # ifdef VBOX_STRICT 2669 2680 ohci_in_done_queue_add(pThis, TdAddr); 2681 # endif 2670 2682 # endif 2671 #endif2672 2683 pTd->NextTD = pThis->done; 2673 2684 pThis->done = TdAddr; … … 2943 2954 if (ohciIsTdInFlight(pThis, TdAddr)) 2944 2955 return false; 2945 # if defined(VBOX_STRICT) || defined(LOG_ENABLED)2956 # if defined(VBOX_STRICT) || defined(LOG_ENABLED) 2946 2957 ohci_in_done_queue_check(pThis, TdAddr); 2947 # endif2958 # endif 2948 2959 return ohciServiceTd(pThis, enmType, pEd, EdAddr, TdAddr, &TdAddr, pszListName); 2949 2960 } … … 2973 2984 } Head; 2974 2985 2975 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE2986 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 2976 2987 ohciPhysReadCacheClear(pThis->pCacheTD); 2977 # endif2988 # endif 2978 2989 2979 2990 /* read the head */ 2980 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE2991 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 2981 2992 ohciReadTdCached(pThis, TdAddr, &Head.Td); 2982 # else2993 # else 2983 2994 ohciReadTd(pThis, TdAddr, &Head.Td); 2984 # endif2995 # endif 2985 2996 ohciBufInit(&Head.Buf, Head.Td.cbp, Head.Td.be); 2986 2997 Head.TdAddr = TdAddr; … … 3000 3011 pCur->pNext = NULL; 3001 3012 pCur->TdAddr = pTail->Td.NextTD & ED_PTR_MASK; 3002 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3013 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3003 3014 ohciReadTdCached(pThis, pCur->TdAddr, &pCur->Td); 3004 # else3015 # else 3005 3016 ohciReadTd(pThis, pCur->TdAddr, &pCur->Td); 3006 # endif3017 # endif 3007 3018 ohciBufInit(&pCur->Buf, pCur->Td.cbp, pCur->Td.be); 3008 3019 … … 3121 3132 if (ohciIsTdInFlight(pThis, TdAddr)) 3122 3133 return false; 3123 # if defined(VBOX_STRICT) || defined(LOG_ENABLED)3134 # if defined(VBOX_STRICT) || defined(LOG_ENABLED) 3124 3135 ohci_in_done_queue_check(pThis, TdAddr); 3125 # endif3136 # endif 3126 3137 return ohciServiceTdMultiple(pThis, enmType, pEd, EdAddr, TdAddr, &TdAddr, pszListName); 3127 3138 } … … 3274 3285 AssertCompile(sizeof(pUrb->paTds[0].TdCopy) >= sizeof(*pITd)); 3275 3286 memcpy(pUrb->paTds[0].TdCopy, pITd, sizeof(*pITd)); 3276 # if 0 /* color the data */3287 # if 0 /* color the data */ 3277 3288 memset(pUrb->abData, 0xfe, cbTotal); 3278 # endif3289 # endif 3279 3290 3280 3291 /* copy the data */ … … 3399 3410 else 3400 3411 { 3401 # if 13412 # if 1 3402 3413 /* 3403 3414 * Ok, the launch window for this TD has passed. … … 3422 3433 break; 3423 3434 } 3424 # else /* BAD IDEA: */3435 # else /* BAD IDEA: */ 3425 3436 /* 3426 3437 * Ok, the launch window for this TD has passed. … … 3439 3450 break; 3440 3451 } 3441 # endif3452 # endif 3442 3453 } 3443 3454 … … 3484 3495 static void ohciServiceBulkList(POHCI pThis) 3485 3496 { 3486 # ifdef LOG_ENABLED3497 # ifdef LOG_ENABLED 3487 3498 if (g_fLogBulkEPs) 3488 3499 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk before", true); 3489 3500 if (pThis->bulk_cur) 3490 3501 Log(("ohciServiceBulkList: bulk_cur=%#010x before listprocessing!!! HCD have positioned us!!!\n", pThis->bulk_cur)); 3491 # endif3502 # endif 3492 3503 3493 3504 /* … … 3504 3515 { 3505 3516 OHCIED Ed; 3506 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3517 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3507 3518 ohciReadEdCached(pThis, EdAddr, &Ed); 3508 # else3519 # else 3509 3520 ohciReadEd(pThis, EdAddr, &Ed); 3510 # endif3521 # endif 3511 3522 Assert(!(Ed.hwinfo & ED_HWINFO_ISO)); /* the guest is screwing us */ 3512 3523 if (ohciIsEdReady(&Ed)) … … 3515 3526 pThis->fBulkNeedsCleaning = true; 3516 3527 3517 # if 13528 # if 1 3518 3529 /* 3519 3530 … … 3525 3536 */ 3526 3537 ohciServiceHeadTdMultiple(pThis, VUSBXFERTYPE_BULK, &Ed, EdAddr, "Bulk"); 3527 # else3538 # else 3528 3539 /* 3529 3540 * This alternative code was used before we started reassembling URBs from … … 3550 3561 } while (ohciIsEdReady(&Ed)); 3551 3562 } 3552 # endif3563 # endif 3553 3564 } 3554 3565 else … … 3572 3583 } 3573 3584 3574 # ifdef LOG_ENABLED3585 # ifdef LOG_ENABLED 3575 3586 if (g_fLogBulkEPs) 3576 3587 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk after ", true); 3577 # endif3588 # endif 3578 3589 } 3579 3590 … … 3588 3599 static void ohciUndoBulkList(POHCI pThis) 3589 3600 { 3590 # ifdef LOG_ENABLED3601 # ifdef LOG_ENABLED 3591 3602 if (g_fLogBulkEPs) 3592 3603 ohciDumpEdList(pThis, pThis->bulk_head, "Bulk before", true); 3593 3604 if (pThis->bulk_cur) 3594 3605 Log(("ohciUndoBulkList: bulk_cur=%#010x before list processing!!! HCD has positioned us!!!\n", pThis->bulk_cur)); 3595 # endif3606 # endif 3596 3607 3597 3608 /* This flag follows OHCI_STATUS_BLF, but BLF doesn't change when list processing is disabled. */ … … 3602 3613 { 3603 3614 OHCIED Ed; 3604 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3615 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3605 3616 ohciReadEdCached(pThis, EdAddr, &Ed); 3606 # else3617 # else 3607 3618 ohciReadEd(pThis, EdAddr, &Ed); 3608 # endif3619 # endif 3609 3620 Assert(!(Ed.hwinfo & ED_HWINFO_ISO)); /* the guest is screwing us */ 3610 3621 if (ohciIsEdPresent(&Ed)) … … 3633 3644 static void ohciServiceCtrlList(POHCI pThis) 3634 3645 { 3635 # ifdef LOG_ENABLED3646 # ifdef LOG_ENABLED 3636 3647 if (g_fLogControlEPs) 3637 3648 ohciDumpEdList(pThis, pThis->ctrl_head, "Ctrl before", true); 3638 3649 if (pThis->ctrl_cur) 3639 3650 Log(("ohciServiceCtrlList: ctrl_cur=%010x before list processing!!! HCD have positioned us!!!\n", pThis->ctrl_cur)); 3640 # endif3651 # endif 3641 3652 3642 3653 /* … … 3656 3667 if (ohciIsEdReady(&Ed)) 3657 3668 { 3658 # if 13669 # if 1 3659 3670 /* 3660 3671 * Control TDs depends on order and stage. Only one can be in-flight … … 3673 3684 ohciReadEd(pThis, EdAddr, &Ed); /* It might have been updated on URB completion. */ 3674 3685 } while (ohciIsEdReady(&Ed)); 3675 # else3686 # else 3676 3687 /* Simplistic, for debugging. */ 3677 3688 ohciServiceHeadTd(pThis, VUSBXFERTYPE_CTRL, &Ed, EdAddr, "Control"); 3678 3689 pThis->status |= OHCI_STATUS_CLF; 3679 # endif3690 # endif 3680 3691 } 3681 3692 … … 3684 3695 } 3685 3696 3686 # ifdef LOG_ENABLED3697 # ifdef LOG_ENABLED 3687 3698 if (g_fLogControlEPs) 3688 3699 ohciDumpEdList(pThis, pThis->ctrl_head, "Ctrl after ", true); 3689 # endif3700 # endif 3690 3701 } 3691 3702 … … 3707 3718 ohciGetDWords(pThis, pThis->hcca + iList * sizeof(EdAddr), &EdAddr, 1); 3708 3719 3709 # ifdef LOG_ENABLED3720 # ifdef LOG_ENABLED 3710 3721 const uint32_t EdAddrHead = EdAddr; 3711 3722 if (g_fLogInterruptEPs) … … 3715 3726 ohciDumpEdList(pThis, EdAddrHead, sz, true); 3716 3727 } 3717 # endif3728 # endif 3718 3729 3719 3730 /* … … 3723 3734 { 3724 3735 OHCIED Ed; 3725 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3736 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3726 3737 ohciReadEdCached(pThis, EdAddr, &Ed); 3727 # else3738 # else 3728 3739 ohciReadEd(pThis, EdAddr, &Ed); 3729 # endif3740 # endif 3730 3741 3731 3742 if (ohciIsEdReady(&Ed)) … … 3771 3782 } 3772 3783 3773 # ifdef LOG_ENABLED3784 # ifdef LOG_ENABLED 3774 3785 if (g_fLogInterruptEPs) 3775 3786 { … … 3778 3789 ohciDumpEdList(pThis, EdAddrHead, sz, true); 3779 3790 } 3780 # endif3791 # endif 3781 3792 } 3782 3793 … … 3811 3822 Log(("ohci: Writeback Done (%#010x) on frame %#x (age %#x)\n", hcca.done, 3812 3823 pThis->HcFmNumber, pThis->HcFmNumber - pThis->u32FmDoneQueueTail)); 3813 # ifdef LOG_ENABLED3824 # ifdef LOG_ENABLED 3814 3825 ohciDumpTdQueue(pThis, hcca.done & ED_PTR_MASK, "DoneQueue"); 3815 # endif3826 # endif 3816 3827 Assert(RT_OFFSETOF(struct ohci_hcca, done) == 4); 3817 # if defined(VBOX_STRICT) || defined(LOG_ENABLED)3828 # if defined(VBOX_STRICT) || defined(LOG_ENABLED) 3818 3829 ohci_in_done_queue_zap(pThis); 3819 # endif3830 # endif 3820 3831 fWriteDoneHeadInterrupt = true; 3821 3832 } … … 3859 3870 Assert(cLeft == 0); 3860 3871 3861 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3872 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3862 3873 /* Get hcca data to minimize calls to ohciGetDWords/PDMDevHlpPhysRead. */ 3863 3874 uint32_t au32HCCA[OHCI_HCCA_NUM_INTR]; 3864 3875 ohciGetDWords(pThis, pThis->hcca, au32HCCA, OHCI_HCCA_NUM_INTR); 3865 # endif3876 # endif 3866 3877 3867 3878 /* Go over all bulk/control/interrupt endpoint lists; any URB found in these lists … … 3879 3890 break; 3880 3891 default: 3881 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3892 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3882 3893 EdAddr = au32HCCA[i]; 3883 # else3894 # else 3884 3895 ohciGetDWords(pThis, pThis->hcca + i * sizeof(EdAddr), &EdAddr, 1); 3885 # endif3896 # endif 3886 3897 break; 3887 3898 } … … 3890 3901 OHCIED Ed; 3891 3902 OHCITD Td; 3892 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3903 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3893 3904 ohciReadEdCached(pThis, EdAddr, &Ed); 3894 # else3905 # else 3895 3906 ohciReadEd(pThis, EdAddr, &Ed); 3896 # endif3907 # endif 3897 3908 uint32_t TdAddr = Ed.HeadP & ED_PTR_MASK; 3898 3909 uint32_t TailP = Ed.TailP & ED_PTR_MASK; … … 3901 3912 && (TdAddr != TailP)) 3902 3913 { 3903 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3914 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3904 3915 ohciPhysReadCacheClear(pThis->pCacheTD); 3905 # endif3916 # endif 3906 3917 do 3907 3918 { 3908 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE3919 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 3909 3920 ohciReadTdCached(pThis, TdAddr, &Td); 3910 # else3921 # else 3911 3922 ohciReadTd(pThis, TdAddr, &Td); 3912 # endif3923 # endif 3913 3924 j = ohci_in_flight_find(pThis, TdAddr); 3914 3925 if (j > -1) … … 3956 3967 static void ohciStartOfFrame(POHCI pThis) 3957 3968 { 3958 # ifdef LOG_ENABLED3969 # ifdef LOG_ENABLED 3959 3970 const uint32_t status_old = pThis->status; 3960 # endif3971 # endif 3961 3972 3962 3973 /* … … 3973 3984 || pThis->hcca < ~OHCI_HCCA_MASK); 3974 3985 3975 # if 13986 # if 1 3976 3987 /* 3977 3988 * Update the HCCA. … … 3980 3991 if (fValidHCCA) 3981 3992 ohciUpdateHCCA(pThis); 3982 # endif3993 # endif 3983 3994 3984 3995 /* "After writing to HCCA, HC will set SF in HcInterruptStatus" - guest isn't executing, so ignore the order! */ … … 4022 4033 ohciUndoBulkList(pThis); /* If list disabled but not empty, abort endpoints. */ 4023 4034 4024 # if 04035 # if 0 4025 4036 /* 4026 4037 * Update the HCCA after processing the lists and everything. A bit experimental. … … 4037 4048 */ 4038 4049 ohciUpdateHCCA(pThis); 4039 # endif4040 4041 # ifdef LOG_ENABLED4050 # endif 4051 4052 # ifdef LOG_ENABLED 4042 4053 if (pThis->status ^ status_old) 4043 4054 { … … 4052 4063 chg & (3<<16)? "*" : "", (val >> 16) & 3)); 4053 4064 } 4054 # endif4065 # endif 4055 4066 } 4056 4067 … … 4078 4089 pThis->fIdle = true; 4079 4090 4080 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS4081 physReadStatsReset(& physReadStats);4082 # endif4083 4084 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE4091 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 4092 physReadStatsReset(&g_PhysReadState); 4093 # endif 4094 4095 # ifdef VBOX_WITH_OHCI_PHYS_READ_CACHE 4085 4096 ohciPhysReadCacheClear(pThis->pCacheED); 4086 4097 ohciPhysReadCacheClear(pThis->pCacheTD); 4087 # endif4098 # endif 4088 4099 4089 4100 /* Frame boundary, so do EOF stuff here. */ … … 4098 4109 ohciStartOfFrame(pThis); 4099 4110 4100 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS4101 physReadStatsPrint(& physReadStats);4102 # endif4111 # ifdef VBOX_WITH_OHCI_PHYS_READ_STATS 4112 physReadStatsPrint(&g_PhysReadState); 4113 # endif 4103 4114 4104 4115 RTCritSectLeave(&pThis->CritSect);
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