Changeset 63648 in vbox for trunk/src/VBox/VMM/include

Timestamp:

Aug 26, 2016 11:44:40 AM (9 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

110381

Message:

VMM/GIM/HyperV: Add partial support for synthetic interrupt controller (still disabled, i.e. not exposed to guest).

File:

• trunk/src/VBox/VMM/include/GIMHvInternal.h (modified) (7 diffs)

trunk/src/VBox/VMM/include/GIMHvInternal.h

@@ -476 +476 @@
 /** Whether the SIEF page is enabled or not. */
 #define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a)        RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
+/** @} */
+
+/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
+ * @{
+ */
+/** The SControl enable mask. */
+#define MSR_GIM_HV_SCONTROL_ENABLE                RT_BIT_64(0)
+/** Whether SControl is enabled or not. */
+#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a)         RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
+/** @} */
+
+/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
+ * @{
+ */
+/** The Stimer enable mask. */
+#define MSR_GIM_HV_STIMER_ENABLE                  RT_BIT_64(0)
+/** Whether Stimer is enabled or not. */
+#define MSR_GIM_HV_STIMER_IS_ENABLED(a)           RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
+/** The Stimer periodic mask. */
+#define MSR_GIM_HV_STIMER_PERIODIC                RT_BIT_64(1)
+/** Whether Stimer is enabled or not. */
+#define MSR_GIM_HV_STIMER_IS_PERIODIC(a)          RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
+/** The Stimer lazy mask. */
+#define MSR_GIM_HV_STIMER_LAZY                    RT_BIT_64(2)
+/** Whether Stimer is enabled or not. */
+#define MSR_GIM_HV_STIMER_IS_LAZY(a)              RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
+/** The Stimer auto-enable mask. */
+#define MSR_GIM_HV_STIMER_AUTO_ENABLE             RT_BIT_64(3)
+/** Whether Stimer is enabled or not. */
+#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a)      RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
+/** The Stimer SINTx mask (bits 16:19). */
+#define MSR_GIM_HV_STIMER_SINTX                   UINT64_C(0xf0000)
+/** Gets the Stimer synthetic interrupt source. */
+#define MSR_GIM_HV_STIMER_GET_SINTX(a)            (((a) >> 16) & 0xf)
+/** The Stimer valid read/write mask. */
+#define MSR_GIM_HV_STIMER_RW_VALID                (  MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC    \
+                                                   | MSR_GIM_HV_STIMER_LAZY   | MSR_GIM_HV_STIMER_AUTO_ENABLE \
+                                                   | MSR_GIM_HV_STIMER_SINTX)
 /** @} */
 
@@ -726 +764 @@
 /** Whether the interrupt source is masked. */
 #define MSR_GIM_HV_SINT_IS_MASKED(a)                   RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
-/** Interrupt vector. */
-#define MSR_GIM_HV_SINT_VECTOR(a)                      ((a) & UINT64_C(0xff))
+/** Gets the interrupt vector. */
+#define MSR_GIM_HV_SINT_GET_VECTOR(a)                  ((a) & UINT64_C(0xff))
+/** The AutoEoi mask. */
+#define MSR_GIM_HV_SINT_AUTOEOI                        RT_BIT_64(17)
+/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
+#define MSR_GIM_HV_SINT_IS_AUTOEOI(a)                  RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
 /** @} */
 
@@ -787 +829 @@
 /** SynIC version register. */
 #define GIM_HV_SVERSION                           1
-/** Number of synthetic interrupt sources. */
+/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
 #define GIM_HV_SINT_COUNT                         16
 /** Lowest valid vector for synthetic interrupt. */
@@ -793 +835 @@
 /** Highest valid vector for synthetic interrupt. */
 #define GIM_HV_SINT_VECTOR_VALID_MAX              255
+/** Number of synthetic timers. */
+#define GIM_HV_STIMER_COUNT                       4
 /** @} */
 
 /** @name Hyper-V synthetic interrupt message type.
+ * See 14.8.2 "SynIC Message Types"
  * @{
  */
@@ -1136 +1181 @@
 
 /**
- * GIM Hyper-V VCPU instance data.
+ * Hyper-V per-VCPU synthetic timer.
+ */
+typedef struct GIMHVSTIMER
+{
+    /** Synthetic timer object - R0 ptr. */
+    PTMTIMERR0                  pTimerR0;
+    /** Synthetic timer object - R3 ptr. */
+    PTMTIMERR3                  pTimerR3;
+    /** Synthetic timer object - RC ptr. */
+    PTMTIMERRC                  pTimerRC;
+    /** RC alignment padding. */
+    RTRCPTR                     uAlignment0;
+    /** Virtual CPU ID this timer belongs to (for reverse mapping). */
+    VMCPUID                     idCpu;
+    /** The index of this timer in the auStimers array (for reverse mapping). */
+    uint32_t                    idxStimer;
+    /** Synthetic timer config MSR. */
+    uint64_t                    uStimerConfigMsr;
+    /** Synthetic timer count MSR. */
+    uint64_t                    uStimerCountMsr;
+    /** Timer description. */
+    char                        szTimerDesc[24];
+
+} GIMHVSTIMER;
+/** Pointer to per-VCPU Hyper-V synthetic timer. */
+typedef GIMHVSTIMER *PGIMHVSTIMER;
+/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
+typedef GIMHVSTIMER const *PCGIMHVSTIMER;
+AssertCompileSizeAlignment(GIMHVSTIMER, 8);
+
+/**
+ * Hyper-V VCPU instance data.
  * Changes to this must checked against the padding of the gim union in VMCPU!
  */
@@ -1146 +1222 @@
     uint64_t                    uSimpMsr;
     /** Interrupt source MSRs. */
-    uint64_t                    auSintXMsr[GIM_HV_SINT_COUNT];
+    uint64_t                    auSintMsrs[GIM_HV_SINT_COUNT];
     /** Synethtic interrupt events flag page MSR. */
     uint64_t                    uSiefpMsr;
     /** APIC-assist page MSR. */
     uint64_t                    uApicAssistPageMsr;
+    /** Synthetic interrupt control MSR. */
+    uint64_t                    uSControlMsr;
+    /** Synthetic timers. */
+    GIMHVSTIMER                 aStimers[GIM_HV_STIMER_COUNT];
+    /** @} */
+
+    /** @name Statistics.
+     * @{ */
+    STAMCOUNTER                 aStatStimerFired[GIM_HV_STIMER_COUNT];
     /** @} */
 } GIMHVCPU;
@@ -1205 +1290 @@
 VMM_INT_DECL(VBOXSTRICTRC)      gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
 
+VMM_INT_DECL(void)              gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer);
+
 RT_C_DECLS_END