Changeset 642 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Feb 5, 2007 4:10:45 PM (18 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Network/DevPCNet.cpp
r638 r642 239 239 PRTREQQUEUE pSendQueue; 240 240 RTTHREAD hSendThread; 241 242 struct 243 { 244 HCPTRTYPE(void *) pBuffer; 245 uint32_t cb; 246 uint32_t fTaken; 247 } paMemCache[PCNET_TRQUEUE_DEPTH]; 241 248 #endif 242 249 … … 308 315 STAMCOUNTER StatXmitAsync; 309 316 STAMCOUNTER StatXmitInTxThread; 310 STAMPROFILE StatXmitQueueAsync; 317 STAMPROFILE StatXmitQueueAsyncPrep; 318 STAMPROFILE StatXmitQueueAsyncReq; 319 STAMCOUNTER StatXmitQueueAsyncCacheMiss; 320 STAMCOUNTER StatXmitQueueAsyncCacheHit; 311 321 #endif /* VBOX_WITH_STATISTICS */ 312 322 }; … … 1800 1810 * Send packet(s) to the network driver. 1801 1811 */ 1802 static DECLCALLBACK(void) pcnetSendAsyncPacket(PCNetState *pData, unsigned cFrames, uint32_t *pacbFrame, uint8_t *pBuf)1812 static DECLCALLBACK(void) pcnetSendAsyncPacket(PCNetState *pData, unsigned iCacheSlot, unsigned cFrames, uint32_t *pacbFrame, uint8_t *pBuf) 1803 1813 { 1804 1814 Assert(pData && pData->pDrv && pData->pDrv->pfnSend); … … 1810 1820 pBuf += RT_ALIGN_32(pacbFrame[i], 16); 1811 1821 } 1812 RTMemFree(pacbFrame); 1822 if (iCacheSlot < ELEMENTS(pData->paMemCache)) 1823 { 1824 pData->paMemCache[iCacheSlot].fTaken = 0; 1825 } 1826 else 1827 RTMemFree(pacbFrame); 1828 1829 #ifdef PCNET_DELAY_INT 1830 if (cFrames) 1831 { 1832 /** @note this part needs to be protected; perhaps we can change the code to drop this requirement. */ 1833 int rc = PDMCritSectEnter(&pData->CritSect, VERR_PERMISSION_DENIED); 1834 AssertReleaseRC(rc); 1835 1836 /* Update TXSTRT and TINT. */ 1837 pData->aCSR[4] |= 0x0004; /* set TXSTRT */ 1838 pData->aCSR[0] |= 0x0200; /* set TINT */ 1839 pcnetUpdateIrq(pData); 1840 1841 PDMCritSectLeave(&pData->CritSect); 1842 } 1843 #endif 1813 1844 } 1814 1845 # endif … … 1846 1877 { 1847 1878 uint32_t cbTotal = 0; 1848 uint32_t *pacbFrame ;1879 uint32_t *pacbFrame = 0; 1849 1880 uint8_t *pBuf; 1850 1851 STAM_PROFILE_START(&pData->StatXmitQueueAsync, b); 1852 for (unsigned i = 0; i < pData->iFrame; i++) 1881 unsigned i, iCacheSlot = ~0; 1882 1883 STAM_PROFILE_START(&pData->StatXmitQueueAsyncPrep, b); 1884 for (i = 0; i < pData->iFrame; i++) 1853 1885 cbTotal += RT_ALIGN_32(pData->aFrames[i].cb, 16); 1854 1886 1855 pacbFrame = (uint32_t *)RTMemAlloc(cbTotal + sizeof(uint32_t) * pData->iFrame); 1887 /* Plus room for size array */ 1888 cbTotal += sizeof(uint32_t) * pData->iFrame; 1889 1890 /* See if there's a free cache entry. */ 1891 for (i=0;i<ELEMENTS(pData->paMemCache);i++) 1892 { 1893 if ( pData->paMemCache[i].cb >= cbTotal 1894 && !pData->paMemCache[i].fTaken) 1895 { 1896 pData->paMemCache[i].fTaken = 1; 1897 pacbFrame = (uint32_t *)pData->paMemCache[i].pBuffer; 1898 iCacheSlot = i; 1899 break; 1900 } 1901 } 1902 if (!pacbFrame) 1903 { 1904 STAM_COUNTER_INC(&pData->StatXmitQueueAsyncCacheMiss); 1905 pacbFrame = (uint32_t *)RTMemAlloc(cbTotal); 1906 } 1907 else 1908 STAM_COUNTER_INC(&pData->StatXmitQueueAsyncCacheHit); 1909 1856 1910 Assert(pacbFrame); 1857 1911 pBuf = (uint8_t *)&pacbFrame[pData->iFrame]; … … 1874 1928 LOG_PACKET("xmit", pv, pData->aFrames[i].cb); 1875 1929 } 1930 STAM_PROFILE_STOP(&pData->StatXmitQueueAsyncPrep, b); 1931 STAM_PROFILE_START(&pData->StatXmitQueueAsyncReq, c); 1876 1932 if (pcnetIsLinkUp(pData)) 1877 1933 { 1878 1934 pBuf = (uint8_t *)&pacbFrame[pData->iFrame]; 1879 1935 1880 rc = RTReqCallEx(pData->pSendQueue, NULL, 0, RTREQFLAGS_NO_WAIT | RTREQFLAGS_VOID, (PFNRT)pcnetSendAsyncPacket, 4, pData, pData->iFrame, pacbFrame, pBuf);1936 rc = RTReqCallEx(pData->pSendQueue, NULL, 0, RTREQFLAGS_NO_WAIT | RTREQFLAGS_VOID, (PFNRT)pcnetSendAsyncPacket, 5, pData, iCacheSlot, pData->iFrame, pacbFrame, pBuf); 1881 1937 AssertRC(rc); 1882 1938 } 1883 STAM_PROFILE_STOP(&pData->StatXmitQueueAsync , b);1939 STAM_PROFILE_STOP(&pData->StatXmitQueueAsyncReq, c); 1884 1940 } 1885 1941 #else … … 1898 1954 } 1899 1955 } 1900 #endif /* PCNET_ASYNC_SEND */1901 1902 1956 #ifdef PCNET_DELAY_INT 1903 1957 if (pData->iFrame) … … 1915 1969 } 1916 1970 #endif 1971 1972 #endif /* PCNET_ASYNC_SEND */ 1917 1973 1918 1974 pData->fTransmitting = false; … … 4323 4379 4324 4380 Assert(pData->hSendThread != NIL_RTTHREAD && pData->pSendQueue); 4381 4382 /* Create some buffer memory to avoid allocating every time we process an async send packet. */ 4383 for (unsigned j=0;j<ELEMENTS(pData->paMemCache);j++) 4384 { 4385 pData->paMemCache[j].cb = sizeof(pData->abFrameBuf) + sizeof(uint32_t) * ELEMENTS(pData->abFrameBuf); 4386 pData->paMemCache[j].fTaken = 0; 4387 pData->paMemCache[j].pBuffer = RTMemAlloc(pData->paMemCache[j].cb); 4388 Assert(pData->paMemCache[j].pBuffer); 4389 } 4325 4390 #endif 4326 4391 … … 4350 4415 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueue, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet xmit queue", "/Devices/PCNet%d/XmitQueue", iInstance); 4351 4416 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueFlushGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet xmit queue flushes from GC", "/Devices/PCNet%d/XmitQueueFlushGC", iInstance); 4352 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueAsync, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet xmit queue async", "/Devices/PCNet%d/XmitQueueAsync", iInstance); 4417 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueAsyncPrep, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet xmit queue async", "/Devices/PCNet%d/XmitQueueASPrep", iInstance); 4418 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueAsyncReq, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet xmit queue async", "/Devices/PCNet%d/XmitQueueASReq", iInstance); 4419 4420 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueAsyncCacheMiss, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr asycn mem cache misses", "/Devices/PCNet%d/Xmit/Cache/Miss", iInstance); 4421 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitQueueAsyncCacheHit, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr asycn mem cache hits", "/Devices/PCNet%d/Xmit/Cache/Hit", iInstance); 4353 4422 4354 4423 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatDeferredXmit, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of deferred xmits queue flushes", "/Devices/PCNet%d/Xmit/Deferred", iInstance);
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