Changeset 64393 in vbox
- Timestamp:
- Oct 24, 2016 2:42:05 PM (8 years ago)
- Location:
- trunk
- Files:
-
- 13 edited
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include/VBox/vmm/pdmpcidev.h (modified) (1 diff)
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src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (1 diff)
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src/VBox/Devices/Bus/DevPCI.cpp (modified) (23 diffs)
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src/VBox/Devices/Bus/DevPciIch9.cpp (modified) (9 diffs)
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src/VBox/Devices/Bus/MsiCommon.cpp (modified) (7 diffs)
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src/VBox/Devices/Bus/MsixCommon.cpp (modified) (1 diff)
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src/VBox/Devices/Network/DevPCNet.cpp (modified) (1 diff)
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src/VBox/Devices/PC/DevACPI.cpp (modified) (5 diffs)
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src/VBox/Devices/PC/DevLPC.cpp (modified) (4 diffs)
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src/VBox/Devices/Serial/DevSerial.cpp (modified) (1 diff)
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src/VBox/Devices/Storage/DevAHCI.cpp (modified) (2 diffs)
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src/VBox/Devices/Storage/DevATA.cpp (modified) (3 diffs)
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src/VBox/Devices/VirtIO/Virtio.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/pdmpcidev.h
r64392 r64393 127 127 typedef struct PDMPCIDEV 128 128 { 129 union 130 { 131 /** PCI config space. */ 132 uint8_t abConfig[256]; 133 #ifndef PDMPCIDEVICE_NO_DEPRECATED 134 /** @deprecated Use abConfig! */ 135 uint8_t config[256]; 136 #endif 137 }; 129 /** PCI config space. */ 130 uint8_t abConfig[256]; 138 131 139 132 /** Internal data. */ -
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r64389 r64393 2812 2812 2813 2813 /* PCI Device (the assertions will be removed later) */ 2814 PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev. config[0x00] == 0x86); Assert(pThis->PciDev.config[0x01] == 0x80);2815 PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev. config[0x02] == 0x15); Assert(pThis->PciDev.config[0x03] == 0x24);2816 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev. config[0x04] == 0x00); Assert(pThis->PciDev.config[0x05] == 0x00);2817 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev. config[0x06] == 0x80); Assert(pThis->PciDev.config[0x07] == 0x02);2818 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev. config[0x08] == 0x01);2819 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev. config[0x09] == 0x00);2820 PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev. config[0x0a] == 0x01);2821 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev. config[0x0b] == 0x04);2822 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev. config[0x0e] == 0x00);2814 PCIDevSetVendorId (&pThis->PciDev, 0x8086); /* 00 ro - intel. */ Assert(pThis->PciDev.abConfig[0x00] == 0x86); Assert(pThis->PciDev.abConfig[0x01] == 0x80); 2815 PCIDevSetDeviceId (&pThis->PciDev, 0x2415); /* 02 ro - 82801 / 82801aa(?). */ Assert(pThis->PciDev.abConfig[0x02] == 0x15); Assert(pThis->PciDev.abConfig[0x03] == 0x24); 2816 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */ Assert(pThis->PciDev.abConfig[0x04] == 0x00); Assert(pThis->PciDev.abConfig[0x05] == 0x00); 2817 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_FAST_BACK); /* 06 rwc?,ro? - pcists. */ Assert(pThis->PciDev.abConfig[0x06] == 0x80); Assert(pThis->PciDev.abConfig[0x07] == 0x02); 2818 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */ Assert(pThis->PciDev.abConfig[0x08] == 0x01); 2819 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */ Assert(pThis->PciDev.abConfig[0x09] == 0x00); 2820 PCIDevSetClassSub (&pThis->PciDev, 0x01); /* 0a ro - scc; 01 == Audio. */ Assert(pThis->PciDev.abConfig[0x0a] == 0x01); 2821 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */ Assert(pThis->PciDev.abConfig[0x0b] == 0x04); 2822 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */ Assert(pThis->PciDev.abConfig[0x0e] == 0x00); 2823 2823 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - nambar - native audio mixer base. */ 2824 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev. config[0x10] == 0x01); Assert(pThis->PciDev.config[0x11] == 0x00); Assert(pThis->PciDev.config[0x12] == 0x00); Assert(pThis->PciDev.config[0x13] == 0x00);2824 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.abConfig[0x10] == 0x01); Assert(pThis->PciDev.abConfig[0x11] == 0x00); Assert(pThis->PciDev.abConfig[0x12] == 0x00); Assert(pThis->PciDev.abConfig[0x13] == 0x00); 2825 2825 PCIDevSetBaseAddress (&pThis->PciDev, 1, /* 14 rw - nabmbar - native audio bus mastering. */ 2826 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev. config[0x14] == 0x01); Assert(pThis->PciDev.config[0x15] == 0x00); Assert(pThis->PciDev.config[0x16] == 0x00); Assert(pThis->PciDev.config[0x17] == 0x00);2827 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev. config[0x3c] == 0x00);2828 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev. config[0x3d] == 0x01);2826 true /* fIoSpace */, false /* fPrefetchable */, false /* f64Bit */, 0x00000000); Assert(pThis->PciDev.abConfig[0x14] == 0x01); Assert(pThis->PciDev.abConfig[0x15] == 0x00); Assert(pThis->PciDev.abConfig[0x16] == 0x00); Assert(pThis->PciDev.abConfig[0x17] == 0x00); 2827 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */ Assert(pThis->PciDev.abConfig[0x3c] == 0x00); 2828 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */ Assert(pThis->PciDev.abConfig[0x3d] == 0x01); 2829 2829 2830 2830 if (pThis->uCodecModel == AC97_CODEC_AD1980) -
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r64392 r64393 259 259 uint32_t last_addr, new_addr, config_ofs; 260 260 261 cmd = RT_LE2H_U16(*(uint16_t *)(d-> config + PCI_COMMAND));261 cmd = RT_LE2H_U16(*(uint16_t *)(d->abConfig + PCI_COMMAND)); 262 262 for(i = 0; i < PCI_NUM_REGIONS; i++) { 263 263 r = &d->Int.s.aIORegions[i]; … … 270 270 if (r->type & PCI_ADDRESS_SPACE_IO) { 271 271 if (cmd & PCI_COMMAND_IO) { 272 new_addr = RT_LE2H_U32(*(uint32_t *)(d-> config +272 new_addr = RT_LE2H_U32(*(uint32_t *)(d->abConfig + 273 273 config_ofs)); 274 274 new_addr = new_addr & ~(r->size - 1); … … 284 284 } else { 285 285 if (cmd & PCI_COMMAND_MEMORY) { 286 new_addr = RT_LE2H_U32(*(uint32_t *)(d-> config +286 new_addr = RT_LE2H_U32(*(uint32_t *)(d->abConfig + 287 287 config_ofs)); 288 288 /* the ROM slot has a specific enable bit */ … … 313 313 /* NOTE: specific hack for IDE in PC case: 314 314 only one byte must be mapped. */ 315 devclass = d-> config[0x0a] | (d->config[0x0b] << 8);315 devclass = d->abConfig[0x0a] | (d->abConfig[0x0b] << 8); 316 316 if (devclass == 0x0101 && r->size == 4) { 317 317 int rc = PDMDevHlpIOPortDeregister(d->Int.s.CTX_SUFF(pDevIns), r->addr + 2, 1); … … 355 355 switch(len) { 356 356 case 1: 357 val = d-> config[address];357 val = d->abConfig[address]; 358 358 break; 359 359 case 2: 360 val = RT_LE2H_U16(*(uint16_t *)(d-> config + address));360 val = RT_LE2H_U16(*(uint16_t *)(d->abConfig + address)); 361 361 break; 362 362 default: 363 363 case 4: 364 val = RT_LE2H_U32(*(uint32_t *)(d-> config + address));364 val = RT_LE2H_U32(*(uint32_t *)(d->abConfig + address)); 365 365 break; 366 366 } … … 396 396 val |= r->type; 397 397 } 398 *(uint32_t *)(d-> config + address) = RT_H2LE_U32(val);398 *(uint32_t *)(d->abConfig + address) = RT_H2LE_U32(val); 399 399 pci_update_mappings(d); 400 400 return; … … 405 405 for(i = 0; i < len; i++) { 406 406 /* default read/write accesses */ 407 switch(d-> config[0x0e]) {407 switch(d->abConfig[0x0e]) { 408 408 case 0x00: /* normal device */ 409 409 case 0x80: /* multi-function device */ … … 460 460 /* don't change reserved bits (11-15) */ 461 461 val &= ~UINT32_C(0xf8); 462 d-> config[addr] = val;462 d->abConfig[addr] = val; 463 463 } 464 464 else if (addr == 0x06) /* Status register, bits 0-7. */ … … 467 467 val &= ~UINT32_C(0xff); 468 468 /* status register, low part: clear bits by writing a '1' to the corresponding bit */ 469 d-> config[addr] &= ~val;469 d->abConfig[addr] &= ~val; 470 470 } 471 471 else if (addr == 0x07) /* Status register, bits 8-15. */ … … 474 474 val &= ~UINT32_C(0x06); 475 475 /* status register, high part: clear bits by writing a '1' to the corresponding bit */ 476 d-> config[addr] &= ~val;476 d->abConfig[addr] &= ~val; 477 477 } 478 478 else 479 479 #endif 480 480 if (can_write) { 481 d-> config[addr] = val;481 d->abConfig[addr] = val; 482 482 } 483 483 addr++; … … 672 672 { 673 673 PPCIBUS pBus = &pGlobals->PciBus; 674 uint8_t *pbCfg = pGlobals->PIIX3State.dev. config;675 const bool fIsAcpiDevice = pPciDev-> config[2] == 0x13 && pPciDev->config[3] == 0x71;674 uint8_t *pbCfg = pGlobals->PIIX3State.dev.abConfig; 675 const bool fIsAcpiDevice = pPciDev->abConfig[2] == 0x13 && pPciDev->abConfig[3] == 0x71; 676 676 /* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door 677 677 * is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC. … … 697 697 * PCI device configuration space). 698 698 */ 699 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev-> config[PCI_INTERRUPT_LINE], uTagSrc);699 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->abConfig[PCI_INTERRUPT_LINE], uTagSrc); 700 700 else 701 701 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc); … … 706 706 { 707 707 /* As per above treat ACPI in a special way */ 708 pic_irq = pPciDev-> config[PCI_INTERRUPT_LINE];708 pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE]; 709 709 pGlobals->acpi_irq = pic_irq; 710 710 pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH; … … 789 789 ("Device is not a PCI bridge but on the list of PCI bridges\n")); 790 790 791 if ( iBus >= pBridgeTemp-> config[VBOX_PCI_SECONDARY_BUS]792 && iBus <= pBridgeTemp-> config[VBOX_PCI_SUBORDINATE_BUS])791 if ( iBus >= pBridgeTemp->abConfig[VBOX_PCI_SECONDARY_BUS] 792 && iBus <= pBridgeTemp->abConfig[VBOX_PCI_SUBORDINATE_BUS]) 793 793 return pBridgeTemp; 794 794 } … … 800 800 static void pciR3Piix3Reset(PIIX3State *d) 801 801 { 802 uint8_t *pci_conf = d->dev. config;802 uint8_t *pci_conf = d->dev.abConfig; 803 803 804 804 pci_conf[0x04] = 0x07; /* master, memory and I/O */ … … 1275 1275 { 1276 1276 SSMR3PutU32(pSSM, i); 1277 SSMR3PutMem(pSSM, pDev-> config, sizeof(pDev->config));1277 SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig)); 1278 1278 1279 1279 int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState); … … 1424 1424 */ 1425 1425 uint8_t const fBridge = fIsBridge ? 2 : 1; 1426 uint8_t *pbDstConfig = &pDev-> config[0];1426 uint8_t *pbDstConfig = &pDev->abConfig[0]; 1427 1427 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++) 1428 1428 if (s_aFields[i].fBridge & fBridge) … … 1476 1476 * restoring functionality governed by these registers. 1477 1477 */ 1478 for (uint32_t off = 0x40; off < sizeof(pDev-> config); off++)1478 for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++) 1479 1479 if (pbDstConfig[off] != pbSrcConfig[off]) 1480 1480 { … … 1559 1559 /* get the data */ 1560 1560 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */ 1561 SSMR3GetMem(pSSM, DevTmp. config, sizeof(DevTmp.config));1561 SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig)); 1562 1562 if (uVersion < 3) 1563 1563 { … … 1588 1588 1589 1589 /* match the vendor id assuming that this will never be changed. */ 1590 if ( DevTmp.config[0] != pDev->config[0]1591 || DevTmp.config[1] != pDev->config[1])1590 if ( DevTmp.abConfig[0] != pDev->abConfig[0] 1591 || DevTmp.abConfig[1] != pDev->abConfig[1]) 1592 1592 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"), 1593 i, pDev->pszNameR3, DevTmp.config, pDev->config);1593 i, pDev->pszNameR3, DevTmp.abConfig, pDev->abConfig); 1594 1594 1595 1595 /* commit the loaded device config. */ 1596 pciR3CommonRestoreConfig(pDev, &DevTmp. config[0], false ); /** @todo fix bridge fun! */1596 pciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0], false ); /** @todo fix bridge fun! */ 1597 1597 1598 1598 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState; … … 2256 2256 2257 2257 /* If the current bus is not the target bus search for the bus which contains the device. */ 2258 if (iBus != pBus->PciDev. config[VBOX_PCI_SECONDARY_BUS])2258 if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS]) 2259 2259 { 2260 2260 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus); … … 2289 2289 2290 2290 /* If the current bus is not the target bus search for the bus which contains the device. */ 2291 if (iBus != pBus->PciDev. config[VBOX_PCI_SECONDARY_BUS])2291 if (iBus != pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS]) 2292 2292 { 2293 2293 PPDMPCIDEV pBridgeDevice = pciR3FindBridge(pBus, iBus); … … 2343 2343 2344 2344 /* Reset config space to default values. */ 2345 pBus->PciDev. config[VBOX_PCI_PRIMARY_BUS] = 0;2346 pBus->PciDev. config[VBOX_PCI_SECONDARY_BUS] = 0;2347 pBus->PciDev. config[VBOX_PCI_SUBORDINATE_BUS] = 0;2345 pBus->PciDev.abConfig[VBOX_PCI_PRIMARY_BUS] = 0; 2346 pBus->PciDev.abConfig[VBOX_PCI_SECONDARY_BUS] = 0; 2347 pBus->PciDev.abConfig[VBOX_PCI_SUBORDINATE_BUS] = 0; 2348 2348 } 2349 2349 -
trunk/src/VBox/Devices/Bus/DevPciIch9.cpp
r64392 r64393 1064 1064 SSMR3PutU32(pSSM, i); 1065 1065 /* PCI config registers */ 1066 SSMR3PutMem(pSSM, pDev-> config, sizeof(pDev->config));1066 SSMR3PutMem(pSSM, pDev->abConfig, sizeof(pDev->abConfig)); 1067 1067 1068 1068 /* Device flags */ … … 1303 1303 uint8_t const fBridge = fIsBridge ? 2 : 1; 1304 1304 Assert(!pciDevIsPassthrough(pDev)); 1305 uint8_t *pbDstConfig = &pDev-> config[0];1305 uint8_t *pbDstConfig = &pDev->abConfig[0]; 1306 1306 1307 1307 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++) … … 1356 1356 * restoring functionality governed by these registers. 1357 1357 */ 1358 for (uint32_t off = 0x40; off < sizeof(pDev-> config); off++)1358 for (uint32_t off = 0x40; off < sizeof(pDev->abConfig); off++) 1359 1359 if (pbDstConfig[off] != pbSrcConfig[off]) 1360 1360 { … … 1449 1449 DevTmp.Int.s.u8MsixCapSize = 0; 1450 1450 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */ 1451 SSMR3GetMem(pSSM, DevTmp. config, sizeof(DevTmp.config));1451 SSMR3GetMem(pSSM, DevTmp.abConfig, sizeof(DevTmp.abConfig)); 1452 1452 1453 1453 SSMR3GetU32(pSSM, &DevTmp.Int.s.fFlags); … … 1494 1494 /* commit the loaded device config. */ 1495 1495 Assert(!pciDevIsPassthrough(pDev)); 1496 pciR3CommonRestoreConfig(pDev, &DevTmp. config[0], false ); /** @todo fix bridge fun! */1496 pciR3CommonRestoreConfig(pDev, &DevTmp.abConfig[0], false ); /** @todo fix bridge fun! */ 1497 1497 1498 1498 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState; … … 2185 2185 u8Val &= ~UINT32_C(0xff); 2186 2186 /* status register, low part: clear bits by writing a '1' to the corresponding bit */ 2187 pPciDev-> config[addr] &= ~u8Val;2187 pPciDev->abConfig[addr] &= ~u8Val; 2188 2188 break; 2189 2189 case VBOX_PCI_STATUS+1: /* Status register, bits 8-15. */ … … 2191 2191 u8Val &= ~UINT32_C(0x06); 2192 2192 /* status register, high part: clear bits by writing a '1' to the corresponding bit */ 2193 pPciDev-> config[addr] &= ~u8Val;2193 pPciDev->abConfig[addr] &= ~u8Val; 2194 2194 break; 2195 2195 case VBOX_PCI_ROM_ADDRESS: case VBOX_PCI_ROM_ADDRESS +1: case VBOX_PCI_ROM_ADDRESS +2: case VBOX_PCI_ROM_ADDRESS +3: … … 2611 2611 { 2612 2612 /* Extracted from MsiPciConfigWrite(). */ 2613 pDev-> config[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e;2613 pDev->abConfig[pDev->Int.s.u8MsiCapOffset + VBOX_MSI_CAP_MESSAGE_CONTROL] &= 0x8e; 2614 2614 } 2615 2615 … … 2618 2618 { 2619 2619 /* Extracted from MsixPciConfigWrite(); no side effects. */ 2620 pDev-> config[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f;2620 pDev->abConfig[pDev->Int.s.u8MsixCapOffset + VBOX_MSIX_CAP_MESSAGE_CONTROL + 1] &= 0x3f; 2621 2621 } 2622 2622 } -
trunk/src/VBox/Devices/Bus/MsiCommon.cpp
r64387 r64393 50 50 return NULL; 51 51 iOff += pDev->Int.s.u8MsiCapOffset; 52 return (uint32_t*)(pDev-> config + iOff);52 return (uint32_t*)(pDev->abConfig + iOff); 53 53 } 54 54 … … 60 60 return NULL; 61 61 iOff += pDev->Int.s.u8MsiCapOffset; 62 return (uint32_t*)(pDev-> config + iOff);62 return (uint32_t*)(pDev->abConfig + iOff); 63 63 } 64 64 … … 140 140 /* don't change read-only bits: 1-3,7 */ 141 141 u8Val &= UINT8_C(~0x8e); 142 pDev-> config[uAddr] = u8Val | (pDev->config[uAddr] & UINT8_C(0x8e));142 pDev->abConfig[uAddr] = u8Val | (pDev->abConfig[uAddr] & UINT8_C(0x8e)); 143 143 break; 144 144 case VBOX_MSI_CAP_MESSAGE_CONTROL + 1: … … 146 146 break; 147 147 default: 148 if (pDev-> config[uAddr] != u8Val)148 if (pDev->abConfig[uAddr] != u8Val) 149 149 { 150 150 int32_t maskUpdated = -1; … … 175 175 uint32_t uVector = maskUpdated*8 + iBitNum; 176 176 177 if (msiBitJustCleared(pDev-> config[uAddr], u8Val, iBit))177 if (msiBitJustCleared(pDev->abConfig[uAddr], u8Val, iBit)) 178 178 { 179 179 Log(("msi: mask updated bit %d@%x (%d)\n", iBitNum, uAddr, maskUpdated)); 180 180 181 181 /* To ensure that we're no longer masked */ 182 pDev-> config[uAddr] &= ~iBit;182 pDev->abConfig[uAddr] &= ~iBit; 183 183 if ((*puPending & (1 << uVector)) != 0) 184 184 { … … 187 187 } 188 188 } 189 if (msiBitJustSet(pDev-> config[uAddr], u8Val, iBit))189 if (msiBitJustSet(pDev->abConfig[uAddr], u8Val, iBit)) 190 190 { 191 191 Log(("msi: mask vector: %d\n", uVector)); … … 194 194 } 195 195 196 pDev-> config[uAddr] = u8Val;196 pDev->abConfig[uAddr] = u8Val; 197 197 } 198 198 } -
trunk/src/VBox/Devices/Bus/MsixCommon.cpp
r64390 r64393 310 310 { 311 311 /* don't change read-only bits 8-13 */ 312 u8NewVal = (u8Val & UINT8_C(~0x3f)) | (pDev-> config[uAddr] & UINT8_C(0x3f));312 u8NewVal = (u8Val & UINT8_C(~0x3f)) | (pDev->abConfig[uAddr] & UINT8_C(0x3f)); 313 313 /* If just enabled globally - check pending vectors */ 314 fJustEnabled |= msixBitJustCleared(pDev-> config[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_ENABLE >> 8);315 fJustEnabled |= msixBitJustCleared(pDev-> config[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_FUNCMASK >> 8);316 pDev-> config[uAddr] = u8NewVal;314 fJustEnabled |= msixBitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_ENABLE >> 8); 315 fJustEnabled |= msixBitJustCleared(pDev->abConfig[uAddr], u8NewVal, VBOX_PCI_MSIX_FLAGS_FUNCMASK >> 8); 316 pDev->abConfig[uAddr] = u8NewVal; 317 317 break; 318 318 } -
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r64387 r64393 4954 4954 PCIDevSetVendorId(&pThis->PciDev, 0x1022); 4955 4955 PCIDevSetDeviceId(&pThis->PciDev, 0x2000); 4956 pThis->PciDev. config[0x04] = 0x07; /* command */4957 pThis->PciDev. config[0x05] = 0x00;4958 pThis->PciDev. config[0x06] = 0x80; /* status */4959 pThis->PciDev. config[0x07] = 0x02;4960 pThis->PciDev. config[0x08] = pThis->fAm79C973 ? 0x40 : 0x10; /* revision */4961 pThis->PciDev. config[0x09] = 0x00;4962 pThis->PciDev. config[0x0a] = 0x00; /* ethernet network controller */4963 pThis->PciDev. config[0x0b] = 0x02;4964 pThis->PciDev. config[0x0e] = 0x00; /* header_type */4965 4966 pThis->PciDev. config[0x10] = 0x01; /* IO Base */4967 pThis->PciDev. config[0x11] = 0x00;4968 pThis->PciDev. config[0x12] = 0x00;4969 pThis->PciDev. config[0x13] = 0x00;4970 pThis->PciDev. config[0x14] = 0x00; /* MMIO Base */4971 pThis->PciDev. config[0x15] = 0x00;4972 pThis->PciDev. config[0x16] = 0x00;4973 pThis->PciDev. config[0x17] = 0x00;4956 pThis->PciDev.abConfig[0x04] = 0x07; /* command */ 4957 pThis->PciDev.abConfig[0x05] = 0x00; 4958 pThis->PciDev.abConfig[0x06] = 0x80; /* status */ 4959 pThis->PciDev.abConfig[0x07] = 0x02; 4960 pThis->PciDev.abConfig[0x08] = pThis->fAm79C973 ? 0x40 : 0x10; /* revision */ 4961 pThis->PciDev.abConfig[0x09] = 0x00; 4962 pThis->PciDev.abConfig[0x0a] = 0x00; /* ethernet network controller */ 4963 pThis->PciDev.abConfig[0x0b] = 0x02; 4964 pThis->PciDev.abConfig[0x0e] = 0x00; /* header_type */ 4965 4966 pThis->PciDev.abConfig[0x10] = 0x01; /* IO Base */ 4967 pThis->PciDev.abConfig[0x11] = 0x00; 4968 pThis->PciDev.abConfig[0x12] = 0x00; 4969 pThis->PciDev.abConfig[0x13] = 0x00; 4970 pThis->PciDev.abConfig[0x14] = 0x00; /* MMIO Base */ 4971 pThis->PciDev.abConfig[0x15] = 0x00; 4972 pThis->PciDev.abConfig[0x16] = 0x00; 4973 pThis->PciDev.abConfig[0x17] = 0x00; 4974 4974 4975 4975 /* subsystem and subvendor IDs */ 4976 pThis->PciDev. config[0x2c] = 0x22; /* subsystem vendor id */4977 pThis->PciDev. config[0x2d] = 0x10;4978 pThis->PciDev. config[0x2e] = 0x00; /* subsystem id */4979 pThis->PciDev. config[0x2f] = 0x20;4980 pThis->PciDev. config[0x3d] = 1; /* interrupt pin 0 */4981 pThis->PciDev. config[0x3e] = 0x06;4982 pThis->PciDev. config[0x3f] = 0xff;4976 pThis->PciDev.abConfig[0x2c] = 0x22; /* subsystem vendor id */ 4977 pThis->PciDev.abConfig[0x2d] = 0x10; 4978 pThis->PciDev.abConfig[0x2e] = 0x00; /* subsystem id */ 4979 pThis->PciDev.abConfig[0x2f] = 0x20; 4980 pThis->PciDev.abConfig[0x3d] = 1; /* interrupt pin 0 */ 4981 pThis->PciDev.abConfig[0x3e] = 0x06; 4982 pThis->PciDev.abConfig[0x3f] = 0xff; 4983 4983 4984 4984 /* -
trunk/src/VBox/Devices/PC/DevACPI.cpp
r64387 r64393 793 793 { 794 794 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN) 795 && (pThis->dev. config[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)796 && (pThis->dev. config[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT795 && (pThis->dev.abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN) 796 && (pThis->dev.abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT 797 797 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK); 798 798 } … … 1927 1927 static void acpiR3PmPCIBIOSFake(ACPIState *pThis) 1928 1928 { 1929 pThis->dev. config[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */1930 pThis->dev. config[PMBA+1] = pThis->uPmIoPortBase >> 8;1931 pThis->dev. config[PMBA+2] = 0x00;1932 pThis->dev. config[PMBA+3] = 0x00;1929 pThis->dev.abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */ 1930 pThis->dev.abConfig[PMBA+1] = pThis->uPmIoPortBase >> 8; 1931 pThis->dev.abConfig[PMBA+2] = 0x00; 1932 pThis->dev.abConfig[PMBA+3] = 0x00; 1933 1933 } 1934 1934 … … 2228 2228 static void acpiR3SMBusPCIBIOSFake(ACPIState *pThis) 2229 2229 { 2230 pThis->dev. config[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */2231 pThis->dev. config[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;2232 pThis->dev. config[SMBBA+2] = 0x00;2233 pThis->dev. config[SMBBA+3] = 0x00;2234 pThis->dev. config[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */2235 pThis->dev. config[SMBSLVC] = 0x00; /* SMBSLVC */2236 pThis->dev. config[SMBSHDW1] = 0x00; /* SMBSHDW1 */2237 pThis->dev. config[SMBSHDW2] = 0x00; /* SMBSHDW2 */2238 pThis->dev. config[SMBREV] = 0x00; /* SMBREV */2230 pThis->dev.abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */ 2231 pThis->dev.abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8; 2232 pThis->dev.abConfig[SMBBA+2] = 0x00; 2233 pThis->dev.abConfig[SMBBA+3] = 0x00; 2234 pThis->dev.abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */ 2235 pThis->dev.abConfig[SMBSLVC] = 0x00; /* SMBSLVC */ 2236 pThis->dev.abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */ 2237 pThis->dev.abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */ 2238 pThis->dev.abConfig[SMBREV] = 0x00; /* SMBREV */ 2239 2239 } 2240 2240 … … 3301 3301 RTIOPORT NewIoPortBase = 0; 3302 3302 /* Check Power Management IO Space Enable (PMIOSE) bit */ 3303 if (pPciDev-> config[PMREGMISC] & 0x01)3303 if (pPciDev->abConfig[PMREGMISC] & 0x01) 3304 3304 { 3305 3305 NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, PMBA); … … 3315 3315 RTIOPORT NewIoPortBase = 0; 3316 3316 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */ 3317 if (pPciDev-> config[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)3317 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN) 3318 3318 { 3319 3319 NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, SMBBA); -
trunk/src/VBox/Devices/PC/DevLPC.cpp
r64387 r64393 190 190 LogFlow(("lpcInfo: \n")); 191 191 192 if (pThis->dev. config[0xde] == 0xbe && pThis->dev.config[0xad] == 0xef)192 if (pThis->dev.abConfig[0xde] == 0xbe && pThis->dev.abConfig[0xad] == 0xef) 193 193 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n"); 194 194 else 195 195 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", 196 pThis->dev. config[0xde], pThis->dev.config[0xad]);196 pThis->dev.abConfig[0xde], pThis->dev.abConfig[0xad]); 197 197 198 198 … … 246 246 247 247 /* 40h - 43h PMBASE 40-43 ACPI Base Address */ 248 pThis->dev. config[0x40] = 0x01; /* IO space */249 pThis->dev. config[0x41] = 0x80; /* base address / 128, see DevACPI.cpp */248 pThis->dev.abConfig[0x40] = 0x01; /* IO space */ 249 pThis->dev.abConfig[0x41] = 0x80; /* base address / 128, see DevACPI.cpp */ 250 250 251 251 /* 44h ACPI_CNTL ACPI Control */ 252 pThis->dev. config[0x44] = 0x00 | (1<<7); /* SCI is IRQ9, ACPI enabled */252 pThis->dev.abConfig[0x44] = 0x00 | (1<<7); /* SCI is IRQ9, ACPI enabled */ 253 253 /* 48h–4Bh GPIOBASE GPIO Base Address */ 254 254 255 255 /* 4C GC GPIO Control */ 256 pThis->dev. config[0x4c] = 0x4d;256 pThis->dev.abConfig[0x4c] = 0x4d; 257 257 /* ???? */ 258 pThis->dev. config[0x4e] = 0x03;259 pThis->dev. config[0x4f] = 0x00;258 pThis->dev.abConfig[0x4e] = 0x03; 259 pThis->dev.abConfig[0x4f] = 0x00; 260 260 261 261 /* 60h-63h PIRQ[n]_ROUT PIRQ[A-D] Routing Control */ 262 pThis->dev. config[0x60] = 0x0b; /* PCI A -> IRQ 11 */263 pThis->dev. config[0x61] = 0x09; /* PCI B -> IRQ 9 */264 pThis->dev. config[0x62] = 0x0b; /* PCI C -> IRQ 11 */265 pThis->dev. config[0x63] = 0x09; /* PCI D -> IRQ 9 */262 pThis->dev.abConfig[0x60] = 0x0b; /* PCI A -> IRQ 11 */ 263 pThis->dev.abConfig[0x61] = 0x09; /* PCI B -> IRQ 9 */ 264 pThis->dev.abConfig[0x62] = 0x0b; /* PCI C -> IRQ 11 */ 265 pThis->dev.abConfig[0x63] = 0x09; /* PCI D -> IRQ 9 */ 266 266 267 267 /* 64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO */ 268 pThis->dev. config[0x64] = 0x10;268 pThis->dev.abConfig[0x64] = 0x10; 269 269 270 270 /* 68h-6Bh PIRQ[n]_ROUT PIRQ[E-H] Routing Control */ 271 pThis->dev. config[0x68] = 0x80;272 pThis->dev. config[0x69] = 0x80;273 pThis->dev. config[0x6A] = 0x80;274 pThis->dev. config[0x6B] = 0x80;271 pThis->dev.abConfig[0x68] = 0x80; 272 pThis->dev.abConfig[0x69] = 0x80; 273 pThis->dev.abConfig[0x6A] = 0x80; 274 pThis->dev.abConfig[0x6B] = 0x80; 275 275 276 276 /* 6C-6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W */ 277 pThis->dev. config[0x70] = 0x80;278 pThis->dev. config[0x76] = 0x0c;279 pThis->dev. config[0x77] = 0x0c;280 pThis->dev. config[0x78] = 0x02;281 pThis->dev. config[0x79] = 0x00;277 pThis->dev.abConfig[0x70] = 0x80; 278 pThis->dev.abConfig[0x76] = 0x0c; 279 pThis->dev.abConfig[0x77] = 0x0c; 280 pThis->dev.abConfig[0x78] = 0x02; 281 pThis->dev.abConfig[0x79] = 0x00; 282 282 /* 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W */ 283 283 /* 82h-83h LPC_EN LPC I/F Enables 0000h R/W */ … … 288 288 289 289 /* A0h-CFh Power Management */ 290 pThis->dev. config[0xa0] = 0x08;291 pThis->dev. config[0xa2] = 0x00;292 pThis->dev. config[0xa3] = 0x00;293 pThis->dev. config[0xa4] = 0x00;294 pThis->dev. config[0xa5] = 0x00;295 pThis->dev. config[0xa6] = 0x00;296 pThis->dev. config[0xa7] = 0x00;297 pThis->dev. config[0xa8] = 0x0f;298 pThis->dev. config[0xaa] = 0x00;299 pThis->dev. config[0xab] = 0x00;300 pThis->dev. config[0xac] = 0x00;301 pThis->dev. config[0xae] = 0x00;290 pThis->dev.abConfig[0xa0] = 0x08; 291 pThis->dev.abConfig[0xa2] = 0x00; 292 pThis->dev.abConfig[0xa3] = 0x00; 293 pThis->dev.abConfig[0xa4] = 0x00; 294 pThis->dev.abConfig[0xa5] = 0x00; 295 pThis->dev.abConfig[0xa6] = 0x00; 296 pThis->dev.abConfig[0xa7] = 0x00; 297 pThis->dev.abConfig[0xa8] = 0x0f; 298 pThis->dev.abConfig[0xaa] = 0x00; 299 pThis->dev.abConfig[0xab] = 0x00; 300 pThis->dev.abConfig[0xac] = 0x00; 301 pThis->dev.abConfig[0xae] = 0x00; 302 302 303 303 /* D0h-D3h FWH_SEL1 Firmware Hub Select 1 */ … … 311 311 312 312 /* F0h-F3h RCBA Root Complex Base Address */ 313 pThis->dev. config[0xf0] = RT_BYTE1(RCBA_BASE | 1); /* enabled */314 pThis->dev. config[0xf1] = RT_BYTE2(RCBA_BASE);315 pThis->dev. config[0xf2] = RT_BYTE3(RCBA_BASE);316 pThis->dev. config[0xf3] = RT_BYTE4(RCBA_BASE);313 pThis->dev.abConfig[0xf0] = RT_BYTE1(RCBA_BASE | 1); /* enabled */ 314 pThis->dev.abConfig[0xf1] = RT_BYTE2(RCBA_BASE); 315 pThis->dev.abConfig[0xf2] = RT_BYTE3(RCBA_BASE); 316 pThis->dev.abConfig[0xf3] = RT_BYTE4(RCBA_BASE); 317 317 318 318 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pThis->dev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_NOT_MANDATORY_NO, -
trunk/src/VBox/Devices/Serial/DevSerial.cpp
r64387 r64393 1189 1189 #ifdef VBOX_SERIAL_PCI 1190 1190 /* the PCI device */ 1191 pThis->PciDev. config[0x00] = 0xee; /* Vendor: ??? */1192 pThis->PciDev. config[0x01] = 0x80;1193 pThis->PciDev. config[0x02] = 0x01; /* Device: ??? */1194 pThis->PciDev. config[0x03] = 0x01;1195 pThis->PciDev. config[0x04] = PCI_COMMAND_IOACCESS;1196 pThis->PciDev. config[0x09] = 0x01; /* Programming interface: 16450 */1197 pThis->PciDev. config[0x0a] = 0x00; /* Subclass: Serial controller */1198 pThis->PciDev. config[0x0b] = 0x07; /* Class: Communication controller */1199 pThis->PciDev. config[0x0e] = 0x00; /* Header type: standard */1200 pThis->PciDev. config[0x3c] = irq_lvl; /* preconfigure IRQ number (0 = autoconfig)*/1201 pThis->PciDev. config[0x3d] = 1; /* interrupt pin 0 */1191 pThis->PciDev.abConfig[0x00] = 0xee; /* Vendor: ??? */ 1192 pThis->PciDev.abConfig[0x01] = 0x80; 1193 pThis->PciDev.abConfig[0x02] = 0x01; /* Device: ??? */ 1194 pThis->PciDev.abConfig[0x03] = 0x01; 1195 pThis->PciDev.abConfig[0x04] = PCI_COMMAND_IOACCESS; 1196 pThis->PciDev.abConfig[0x09] = 0x01; /* Programming interface: 16450 */ 1197 pThis->PciDev.abConfig[0x0a] = 0x00; /* Subclass: Serial controller */ 1198 pThis->PciDev.abConfig[0x0b] = 0x07; /* Class: Communication controller */ 1199 pThis->PciDev.abConfig[0x0e] = 0x00; /* Header type: standard */ 1200 pThis->PciDev.abConfig[0x3c] = irq_lvl; /* preconfigure IRQ number (0 = autoconfig)*/ 1201 pThis->PciDev.abConfig[0x3d] = 1; /* interrupt pin 0 */ 1202 1202 #endif /* VBOX_SERIAL_PCI */ 1203 1203 -
trunk/src/VBox/Devices/Storage/DevAHCI.cpp
r64387 r64393 5867 5867 PCIDevSetInterruptPin (&pThis->dev, 0x01); 5868 5868 5869 pThis->dev. config[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */5870 pThis->dev. config[0x71] = 0xa8; /* next */5871 pThis->dev. config[0x72] = 0x03; /* version ? */5872 5873 pThis->dev. config[0x90] = 0x40; /* AHCI mode. */5874 pThis->dev. config[0x92] = 0x3f;5875 pThis->dev. config[0x94] = 0x80;5876 pThis->dev. config[0x95] = 0x01;5877 pThis->dev. config[0x97] = 0x78;5878 5879 pThis->dev. config[0xa8] = 0x12;/* SATACR capability */5880 pThis->dev. config[0xa9] = 0x00;/* next */5869 pThis->dev.abConfig[0x70] = VBOX_PCI_CAP_ID_PM; /* Capability ID: PCI Power Management Interface */ 5870 pThis->dev.abConfig[0x71] = 0xa8; /* next */ 5871 pThis->dev.abConfig[0x72] = 0x03; /* version ? */ 5872 5873 pThis->dev.abConfig[0x90] = 0x40; /* AHCI mode. */ 5874 pThis->dev.abConfig[0x92] = 0x3f; 5875 pThis->dev.abConfig[0x94] = 0x80; 5876 pThis->dev.abConfig[0x95] = 0x01; 5877 pThis->dev.abConfig[0x97] = 0x78; 5878 5879 pThis->dev.abConfig[0xa8] = 0x12; /* SATACR capability */ 5880 pThis->dev.abConfig[0xa9] = 0x00; /* next */ 5881 5881 PCIDevSetWord(&pThis->dev, 0xaa, 0x0010); /* Revision */ 5882 5882 PCIDevSetDWord(&pThis->dev, 0xac, 0x00000028); /* SATA Capability Register 1 */ … … 6071 6071 /* Mark that a device is present on that port */ 6072 6072 if (i < 6) 6073 pThis->dev. config[0x93] |= (1 << i);6073 pThis->dev.abConfig[0x93] |= (1 << i); 6074 6074 6075 6075 /* -
trunk/src/VBox/Devices/Storage/DevATA.cpp
r64387 r64393 7416 7416 PCIDevSetDeviceId(&pThis->dev, 0x269e); /* ICH6 IDE */ 7417 7417 /** @todo do we need it? Do we need anything else? */ 7418 pThis->dev. config[0x48] = 0x00; /* UDMACTL */7419 pThis->dev. config[0x4A] = 0x00; /* UDMATIM */7420 pThis->dev. config[0x4B] = 0x00;7418 pThis->dev.abConfig[0x48] = 0x00; /* UDMACTL */ 7419 pThis->dev.abConfig[0x4A] = 0x00; /* UDMATIM */ 7420 pThis->dev.abConfig[0x4B] = 0x00; 7421 7421 { 7422 7422 /* … … 7428 7428 */ 7429 7429 uint16_t u16Config = (1<<10) | (1<<7) | (1<<6) | (1<<5) | (1<<4) ; 7430 pThis->dev. config[0x54] = u16Config & 0xff;7431 pThis->dev. config[0x55] = u16Config >> 8;7430 pThis->dev.abConfig[0x54] = u16Config & 0xff; 7431 pThis->dev.abConfig[0x55] = u16Config >> 8; 7432 7432 } 7433 7433 break; … … 7435 7435 PCIDevSetDeviceId(&pThis->dev, 0x7111); /* PIIX4 IDE */ 7436 7436 PCIDevSetRevisionId(&pThis->dev, 0x01); /* PIIX4E */ 7437 pThis->dev. config[0x48] = 0x00; /* UDMACTL */7438 pThis->dev. config[0x4A] = 0x00; /* UDMATIM */7439 pThis->dev. config[0x4B] = 0x00;7437 pThis->dev.abConfig[0x48] = 0x00; /* UDMACTL */ 7438 pThis->dev.abConfig[0x4A] = 0x00; /* UDMATIM */ 7439 pThis->dev.abConfig[0x4B] = 0x00; 7440 7440 break; 7441 7441 case CHIPSET_PIIX3: -
trunk/src/VBox/Devices/VirtIO/Virtio.cpp
r64387 r64393 619 619 } 620 620 621 /**622 * Sets 8-bit register in PCI configuration space.623 * @param refPciDev The PCI device.624 * @param uOffset The register offset.625 * @param u16Value The value to store in the register.626 * @thread EMT627 */628 DECLINLINE(void) vpciCfgSetU8(PDMPCIDEV& refPciDev, uint32_t uOffset, uint8_t u8Value)629 {630 Assert(uOffset < sizeof(refPciDev.config));631 refPciDev.config[uOffset] = u8Value;632 }633 634 /**635 * Sets 16-bit register in PCI configuration space.636 * @param refPciDev The PCI device.637 * @param uOffset The register offset.638 * @param u16Value The value to store in the register.639 * @thread EMT640 */641 DECLINLINE(void) vpciCfgSetU16(PDMPCIDEV& refPciDev, uint32_t uOffset, uint16_t u16Value)642 {643 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));644 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;645 }646 621 647 622 #if 0 /* unused */ … … 807 782 PCIDevSetVendorId(&pci, DEVICE_PCI_VENDOR_ID); 808 783 PCIDevSetDeviceId(&pci, DEVICE_PCI_BASE_ID + uDeviceId); 809 vpciCfgSetU16(pci,VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID);810 vpciCfgSetU16(pci,VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId);784 PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, DEVICE_PCI_SUBSYSTEM_VENDOR_ID); 785 PDMPciDevSetWord(&pci, VBOX_PCI_SUBSYSTEM_ID, DEVICE_PCI_SUBSYSTEM_BASE_ID + uDeviceId); 811 786 812 787 /* ABI version, must be equal 0 as of 2.6.30 kernel. */ 813 vpciCfgSetU8( pci,VBOX_PCI_REVISION_ID, 0x00);788 PDMPciDevSetByte(&pci, VBOX_PCI_REVISION_ID, 0x00); 814 789 /* Ethernet adapter */ 815 vpciCfgSetU8( pci,VBOX_PCI_CLASS_PROG, 0x00);816 vpciCfgSetU16(pci, VBOX_PCI_CLASS_DEVICE,uClass);790 PDMPciDevSetByte(&pci, VBOX_PCI_CLASS_PROG, 0x00); 791 PDMPciDevSetWord(&pci, VBOX_PCI_CLASS_DEVICE, uClass); 817 792 /* Interrupt Pin: INTA# */ 818 vpciCfgSetU8( pci,VBOX_PCI_INTERRUPT_PIN, 0x01);793 PDMPciDevSetByte(&pci, VBOX_PCI_INTERRUPT_PIN, 0x01); 819 794 820 795 #ifdef VBOX_WITH_MSI_DEVICES 821 PCIDevSetCapabilityList 822 PCIDevSetStatus (&pci,VBOX_PCI_STATUS_CAP_LIST);796 PCIDevSetCapabilityList(&pci, 0x80); 797 PCIDevSetStatus( &pci, VBOX_PCI_STATUS_CAP_LIST); 823 798 #endif 824 799 }
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